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From: Chris <chr...@ym...> - 2020-04-09 16:26:10
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/"It is a common thing for an electronic component to have multiple ports connected to the same wire, this is not a bug nor an error."/ /"as far as I know the 4th connection of the BJT model is the substrate...Qucs has also symbols for BJT with the substrate connection available. " / OK, the board designer will have to deal with it then... /"//Only the unlabeled nets are assigned a name starting with "_"//"/ Well I'm very glad I asked then! I didn' t realise that. I'll assume they are all nets whatever the name, until I get to a field which contains '=' (for example 'L="1 nH"'), in which case it is a component detail field. Thanks Claudio! On 09/04/2020 4:38 pm, Claudio Girardi via Qucs-devel wrote: > Hello, > as far as I know the 4th connection of the BJT model is the substrate and for 3-terminal BJTs it's always shorted to the collector. Qucs has also symbols for BJT with the substrate connection available. > > Regarding "gnd", it's the only net with a special name, as far as I know. Note that any net (wire) on the schematic can be given a label, which will be used in the netlist, so if you label a wire "mygnd" you'll find a net with this name there (and if you label a net "gnd" it will be connected to ground). > Only the unlabeled nets are assigned a name starting with "_", AFAIK. > > Regards, > Claudio > >> Il 9 aprile 2020 alle 14.56 Chris via Qucs-devel <quc...@li...> ha scritto: >> >> >> That confirms what I thought. I have written something robust enough to >> deal with this, but I wanted to be sure that my guesses were correct. >> Thanks Thomas! >> >> I have already posted the questions below, but since I now have your >> attention :) >> >> 1) This component line in a sim file refers to the same net twice, >> that doesn't look right to me. >> >> BJT:T1 _net16 *_net17* _net18 *_net17* Type="npn" >> >> 2) In the component lines in a sim file, the net names appear to >> start with '_net', but there is also 'gnd', are there any other >> special net names like this? >> >> I'm hoping these are the last questions, as the script is working apart >> from problems with (1). >> >> Chris >> >> >> >> On 09/04/2020 1:45 pm, Thomas.lepoix wrote: >>> I don't remember having ever found a documentation about the netlist format. >>> >>> As far as I know, each line follow the same model : >>> >>> type:label net property="value" >>> >>> net fields are "wire" labels, for example, in the following sequence there is a wire that connects the second port of the diode D1, the first port of D2 and the first port of D3. >>> >>> Diode:D1 _net0 _net1 Is="1E-11" N="1.27" Rs="3.858 ... >>> Diode:D2 _net1 _net2 Is="1E-11" N="1.27" Rs="3.858 ... >>> Diode:D3 _net1 _net3 Is="1E-11" N="1.27" Rs="3.858 ... >>> >>> property fields are also present in the .sch file. >>> >>> It seems to me that def paragraphs wrap subcircuits. "Z_Diodes_1N756" is a particular model of diode. So this library component is a subcircuit wrapping a classic diode component with particular properties. >>> >>> "PVR100AZ_B12V_mod" is a more complex library component so it wraps another subcircuit "PVR100AZ_B12V" with its own def paragraph and then used through the "sub" component. that's why defs can be nested, a def contain a piece of schematic. >>> >>> however that is true that the file indentation is rather strange.. I guess your parser have to be robust enough to this kind of randomness. >>> >>> >>> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ >>> On Thursday 9 April 2020 00:13, Chris via Qucs-devel <quc...@li...> wrote: >>> >>>> Files created using qucs -i filename1 -o filename2 -n >>>> >>>> Is there a definition of these files, and if so where? >>>> >>>> I think I can just use the component list at the end, so I need to skip >>>> the '.Def's, but they are confusing, since sometimes the .Def:End starts >>>> in the first column and sometimes not, and sometimes the .Def paragraphs >>>> are nested. Are they supposed to be that way? >>>> >>>> .Def*:*Z_Diodes_1N756 _net0 _net1 >>>> Diode:D1 _net0 _net1 Is="1E-11" N="1.27" Rs="3.858" >>>> Cj0="2.749E-10" Vj="0.75" M="0.33" Fc="0.5" Tt="5E-8" Bv="8.123" >>>> Ibv="0.01" Af="1" Kf="0" >>>> .Def:End >>>> >>>> .Def:PVR100AZ_B12V_mod _net4 _net1 _net2 _net3 _ref >>>> Sub:X1 _ref _net1 _net2 _net3 _net4 Type="PVR100AZ_B12V" >>>> .Def:PVR100AZ_B12V _ref _net1 _net2 _net3 _net4 >>>> BJT:Q1 _net1 _net4 _net3 _ref Type="npn" Is="9.198e-014" Nf="1.003" >>>> Ise="4.468e-016" Ne="1.65" Bf="338.8" Ikf="0.4913" Vaf="107.9" >>>> Nr="1.002" Isc="5.109e-015" Nc="1.071" Br="29.48" Ikr="0.193" Var="25" >>>> Rb="1" Irb="1000" Rbm="1" Re="0.2126" Rc="0.143" Xtb="0" Eg="1.11" >>>> Xti="3" Cje="3.825e-011" Vje="0.7004" Mje="0.364" Tf="5.229e-010" >>>> Xtf="219.7" Vtf="3.502" Itf="7.257" Ptf="0" Cjc="1.27e-011" Vjc="0.4431" >>>> Mjc="0.3983" Xcjc="0.4555" Tr="7e-011" Cjs="0" Vjs="0.75" Mjs="0.333" >>>> Fc="0.905" >>>> Diode:D1 _net1 _net2 Is="9.794e-015" N="1.101" Bv="13" Ibv="0.005" >>>> Rs="0.3363" Cj0="4.377e-011" Vj="0.5656" M="0.3289" Fc="0.5" >>>> .Def:End >>>> .Def:End >>>> >>>> Qucs-devel mailing list >>>> Quc...@li... >>>> https://lists.sourceforge.net/lists/listinfo/qucs-devel >> >> _______________________________________________ >> Qucs-devel mailing list >> Quc...@li... >> https://lists.sourceforge.net/lists/listinfo/qucs-devel > > _______________________________________________ > Qucs-devel mailing list > Quc...@li... > https://lists.sourceforge.net/lists/listinfo/qucs-devel |