Re: [Qucs-devel] Verilog HDL

[<Mic...@al...>]

> Hello!

Hello,

> I just added some code by Ozgur for the D-FlipFlop which creates
> Verilog HDL code.
>
> If Qucs is ever supporting Verilog HDL, the following tested route
> could be gone:
>
>   1. create Verilog HDL code from the GUI (very likely VHDL)
>   2. run a "qucsveri.sh" script which
>      - runs iverilog + vvd (both GPL and also available for Win32)
>      - this creates a .vcd file (if there is a $dumpfile() and
>        $dumpvars() statement)
>      - qucsconv can then convert this into a Qucs dataset
>   3. the GUI can read-back the dataset and display results
>
> Please tell if you like the idea, and if you are going to support it or
> not.  What do you think?

I don't like that idea, because it don't really opens the user a new
opportunity. Which language Qucs uses internally to perform a simulation
is not that important for the user. It also creates the problem that
the user may place a "VHDL-file-component" on the schematic that cannot
be simulated with Verilog.

I think it would make much more sense to support Verilog-AMS. This way,
the user can include his own models into Qucs.

Regards,
     Michael