[Qucs-devel] Verilog HDL

[Stefan J. <st...@gr...>]

Hello!

I just added some code by Ozgur for the D-FlipFlop which creates Verilog
HDL code.

If Qucs is ever supporting Verilog HDL, the following tested route could
be gone:

  1. create Verilog HDL code from the GUI (very likely VHDL)
  2. run a "qucsveri.sh" script which
     - runs iverilog + vvd (both GPL and also available for Win32)
     - this creates a .vcd file (if there is a $dumpfile() and
       $dumpvars() statement)
     - qucsconv can then convert this into a Qucs dataset
  3. the GUI can read-back the dataset and display results

Please tell if you like the idea, and if you are going to support it or
not.  What do you think?

Cheers, Stefan.