Re: [Qucs-devel] Mixed-signal support (and other stuff)

[Frans S. <fra...@gm...>]

Dear Kevin,

I think mixed singnal VHDL would be a very nice to have addition to the
already powerful qucs simulator. My experience with vhdl is purely digital,
but i am willing to learn. The only thing is that my time is limited and i
might not be able to help a lot with this new feature.  For now my biggest
priority is to get the qt4 gui working properly and stable, other people
are mainly working on matlab scripts and models right now.
Could you explain a bit more in detail what you have in mind? How many
people would you like to help with your code and what kind of skills?
If you want write access to the git repository please let me know your
username.

Regards Frans
Op 5 apr. 2013 19:26 schreef "Kevin Cameron" <cam...@gm...> het
volgende:

> Just to introduce myself -
>
> I have worked on a couple of VHDL simulators, Verilog (VCS), Verilog-AMS
> (HSpice), and participated in the language development of Verilog-AMS since
> the start, and some of SystemVerilog.
>
> I designed the mixed-signal "connect module" methodology for Verilog-AMS
> that allows automatic connection of analog and digital parts of simulation.
>
> History:
>
> My original design for the AMS stuff got broken by Cadence during the
> standardization and has never worked properly in commercial tools (except
> maybe Antrim's which Cadence bought and shelved).
>
> Cadence blocked moving Verilog-AMS into SystemVerilog and off to the IEEE,
> and the IEEE effort has been constrained to IEEE-SA members only
> ($5k+/year) - most of whom are not interested in mixed-signal (or anything
> that smells of analog).
>
> So the only IEEE HDL that supports both analog and digital is VHDL, but it
> has a bunch of semantic problems that make it difficult to use.
>
> Plan:
>
> Since the official language development committees don't seem to be able to
> address mixed-signal issues sensibly I'd like to fix this in the open
> source community, and VHDL seems like it might be a better option at the
> moment since it has no conflicting methodology.
>
> The goal of the exercise is to support better modeling for SoC with power
> management (variable voltage supplies) and wiring issues, so it's not
> particularly about precision analog, and I would like to support discrete
> modeling of analog (for parasitic Rs &Cs). However, a precision analog
> kernel may become available in open-source soon and I may look at how to
> integrate that.
>
> Longer term I would like to develop a C++ API layer so I can bolt together
> the VHDL and Verilog stuff independent of the higher level language specs,
> and I have a project to support that on a back burner (http://parallel.cc
> ).
>
>
> So if anybody would like to help make VHDL be the language it should have
> been, I'll post what I think needs to be done at the language level and
> internally to the simulator(s).
>
> Kev.
>
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