#163 BJT modeling error

[Dwight Wildon]

Hi,

I am an engineer building a HF transistor library NXP SiGe_C transistors
the published models have the transit time parameters:
Tf="1.3236e-12" Xtf="43.92" Vtf="-17.68" Itf="89e-3"
QUCS gives Range ERROR for Vtf, and and aborts Sim.
Have manually computed the Tff value from Tech paper, and results are quite reasonable. I beleive the range checking code needs modification.

[Guilherme]

Maybe we can change the Error into a Warning. Can you provide further details?

The error is about Vtf orTf`?

Currently Qucs expects Vtf > 0.

It might happen that in order to fit the measured devices to the bjt model (Spice Gummel-Poon I believe) the manufacturer is tweaking the model parameters.

[Dwight Wildon]

I'm sure tweeking was what it was.
Error to Warning sounds reasonable, as long as it conyinues the
simulation.

Attached is a zip file of pertinent data:

NXP model source
My library
test project
pdf data sheet for one of the transistors.

You should note that NXP publishes the exact same model for all of the
transistors in the family.The "area" factors were added by me to obtain
a complete model for all of the series except for BFU710F which the
original model fits with an area of 1.0.

Dwight Wildon dwildon@cfl.rr.com

[Guilherme]

The attached patch allow the simulation to continue and issuing a warning instead of failing. Something like:

creating netlist...
NOTIFY: SW1: running netlist for Ibb = 5e-06
NOTIFY: SW2: running netlist for Vdd = 0
WARNING: Unphysical model parameter Vtf = -17.68 in BJT `BFU790F.SUB1.chip_790'
NOTIFY: DC1: creating node list for DC analysis
NOTIFY: DC1: solving DC netlist
NOTIFY: DC1: convergence reached after 10 iterations

Are you compiling from source or using a distributed binary?

I see that the BUF710 has Vtf=0 while the others three models have Vtf=-17.68.

May I ask how do you calculate the Vtf parameter? When you say 'original model fits', are you fitting to the datasheet curves?

[Dwight Wildon]

Sorry, I changed all of the Vtf params to "0" so that I could optimize
the Area param. I must have forgotten to change the BFU710 back after
testing the DCs

Vtf param does not affect the DC characteristics, so it can be made 0 to
run DC's for area calculation testing.

I took Vtf from the NXP model without change. When I said the original
model ran correctly, I meant the DC's matched the published typical
curves without scaling. Iin Spice the Area factor is normally part of
the model call, that is it is supplied with the net list insertion. In
qucs, it is part of the model. I tink this is better for discrete part
simulation, but the spice way probably works better for IC transistor
level modeling.

Thanks for your help, will try patch when I get a chance.

Am currently running from compiled code, but I can re-compile if needed.
Version Ubuntu 14.04, qucs-0.0.18.131128

[Dwight Wildon]

Please find attached the final version of the NXP SiGe family of
transistors. The devices have two emitter connections. the "fat" one has
lower inductance. At low <10GHz frequencies if simply tied together
adequate modeling will result. At higher frequencies, the delay and
parasitics in the connection must be considered.

Have a good day!

[Guilherme]

Thank you for sharing!

[Guilherme]

The patch is now merged into the repository.
It will soon be available in the next snapshot or stable release.
If you wish to contribute and to have the component library integrated into Qucs, please attach its final version.