#28 Structures/records with named members

[Wesley J. Landaker]

One thing I think a future version of PHDL could really use is structures (called records in VHDL) that allow grouping a set of named nets. This is similar to arrays, which we alreay support, as they are also just a collection of nets. However, the index into arrays is always a number, whereas the index into a structure is a name.

This kind of thing is very useful for passing around buses of related signals that need to go between levels of hierarchy. Without structure support, split blocks up into hierarchies is much more tedious that it necessarily needs to be.

For example, if I have a 128-bit data bus, I get a lot of power out of having arrays, because instead of:

data1 = something_data1
data2 = something_data2
data3 = something_data3
... etc ...

I can just do:

data = something_data

Now, if this is a big bus, say from a memory-like device, I still have to do something like this:

address = something_address
data = something_data
parity = something_parity
clk = something_clk
oe = something_oe
cs = something_cs
ras = something_ras
cas = something_cas
clk_en = something_clk_en
data_strobes = something_data_strobes
... etc ...

Whereas, if I could wrap the different parts into a structure/record, this would change to:

memory_bus = something_memory_bus

If we decide to add this feature, we basically need a couple things added to the syntax. One is a way to declare a net that is a structure rather than a single bit or an array. The other is a way to address a member of the net structure.

After that, we would need to make sure that the semantics of these nets works as expected in all situations.

[Pedro]

I tried typing in a little example code to see how it would feel. The net structure really cleans up the top level of the design.

// FPGA Config Bus
net[25:1] cfg_addr; 
net[15:0] cfg_data; 
net cfg_we_n, cfg_oe_n, cfg_cclk, cfg_reset_n, cfg_ce_n;

If this went down through a hierarchy level that assignment would look like this.

subInst fpga1 of fpga {
    ....
    cfg_addr = cfg_addr;
    cfg_data = cfg_data;
    cfg_we_n = cfg_we_n;
    cfg_oe_n = cfg_oe_n;
    cfg_cclk = cfg_cclk;
    cfg_reset_n = cfg_reset_n;
    cfg_ce_n = cfg_ce_n;
    ....
}

This is a little bit of a bad example because the FPGA configuration bus should not go through a level of hierarchy but for argument's sake the structure might look like this.

// FPGA Config Bus
netstruct config_bus{
    net[25:1] addr;
    net[15:0] data;
    net we_n, oe_n, adv_n, wait, clk, reset_n, wp_n, ce_n;
}

and the assignment to the hierarchy block would be a lot cleaner.

subInst fpga1 of fpga {
    ....
    config_bus = config_bus;
    ....
}

My gut tells me this is a nice feature that can be postponed for quite a while.

Pete