[perfmon2] [PATCH] libpfm3: Add support for up to 6 counters (AMD Family 15h cpus)

[Robert R. <rob...@am...>]

Though Family 15h support has been added earlier, there was a
limitation to use only 4 counters. This patch implements support for
up to 6 counters.

Signed-off-by: Robert Richter <rob...@am...>
---
 lib/pfmlib_amd64.c      |   27 +++++++++++++++++----------
 lib/pfmlib_amd64_priv.h |   31 +++++++++++++++++++++----------
 2 files changed, 38 insertions(+), 20 deletions(-)

diff --git a/lib/pfmlib_amd64.c b/lib/pfmlib_amd64.c
index ab417e3..0194269 100644
--- a/lib/pfmlib_amd64.c
+++ b/lib/pfmlib_amd64.c
@@ -72,8 +72,10 @@
  * 	1 -> PMD1 -> PERCTR1 -> MSR @ 0xc0010005
  * 	...
  */
-#define AMD64_SEL_BASE	0xc0010000
-#define AMD64_CTR_BASE	0xc0010004
+#define AMD64_SEL_BASE		0xc0010000
+#define AMD64_CTR_BASE		0xc0010004
+#define AMD64_SEL_BASE_F15H	0xc0010200
+#define AMD64_CTR_BASE_F15H	0xc0010201
 
 static struct {
 	amd64_rev_t	revision;
@@ -213,6 +215,7 @@ pfm_amd64_setup(amd64_rev_t revision)
 		amd64_support.pme_count	= amd64_fam15h_table.num;
 		amd64_pmu.cpu_clks	= amd64_fam15h_table.cpu_clks;
 		amd64_pmu.ret_inst	= amd64_fam15h_table.ret_inst;
+		amd64_support.num_cnt   = PMU_AMD64_NUM_COUNTERS_F15H;
 		amd64_support.pmc_count	= PMU_AMD64_NUM_PERFSEL;
 		amd64_support.pmd_count	= PMU_AMD64_NUM_PERFCTR;
 		return;
@@ -522,15 +525,19 @@ pfm_amd64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_amd64_input_param_
 			if ((IS_FAM10H_ONLY(reg)) && !IS_FAMILY_10H())
 				return PFMLIB_ERR_BADHOST;
 
-			pc[j].reg_value = reg.val;
-			pc[j].reg_addr  = AMD64_SEL_BASE+assign[j];
-			pc[j].reg_alt_addr = AMD64_SEL_BASE+assign[j];
+			if (amd64_support.num_cnt == PMU_AMD64_NUM_COUNTERS_F15H) {
+				pc[j].reg_addr = AMD64_SEL_BASE_F15H + (assign[j] << 1);
+				pd[j].reg_addr = AMD64_CTR_BASE_F15H + (assign[j] << 1);
+			} else {
+				pc[j].reg_addr = AMD64_SEL_BASE + assign[j];
+				pd[j].reg_addr = AMD64_CTR_BASE + assign[j];
+			}
 
+			pc[j].reg_value = reg.val;
+			pc[j].reg_alt_addr = pc[j].reg_addr;
 
 			pd[j].reg_num  = assign[j];
-			pd[j].reg_addr = AMD64_CTR_BASE+assign[j];
-			/* index to use with RDPMC */
-			pd[j].reg_alt_addr = assign[j];
+			pd[j].reg_alt_addr = assign[j];		/* index to use with RDPMC */
 
 			__pfm_vbprintf("[PERFSEL%u(pmc%u)=0x%llx emask=0x%x umask=0x%x os=%d usr=%d inv=%d en=%d int=%d edge=%d cnt_mask=%d] %s\n",
 					assign[j],
@@ -671,7 +678,7 @@ pfm_amd64_dispatch_events(
 static int
 pfm_amd64_get_event_code(unsigned int i, unsigned int cnt, int *code)
 {
-	if (cnt != PFMLIB_CNT_FIRST && cnt > 3)
+	if (cnt != PFMLIB_CNT_FIRST && cnt >= amd64_support.num_cnt)
 		return PFMLIB_ERR_INVAL;
 
 	*code = pfm_amd64_get_event_entry(i)->pme_code;
@@ -727,7 +734,7 @@ pfm_amd64_get_impl_counters(pfmlib_regmask_t *impl_counters)
 	unsigned int i = 0;
 
 	/* counting pmds are contiguous */
-	for(i=0; i < 4; i++)
+	for(i=0; i < amd64_support.num_cnt; i++)
 		pfm_regmask_set(impl_counters, i);
 }
 
diff --git a/lib/pfmlib_amd64_priv.h b/lib/pfmlib_amd64_priv.h
index 5def153..55a29ed 100644
--- a/lib/pfmlib_amd64_priv.h
+++ b/lib/pfmlib_amd64_priv.h
@@ -25,16 +25,27 @@
 #ifndef __PFMLIB_AMD64_PRIV_H__
 #define __PFMLIB_AMD64_PRIV_H__
 
-/* PERFSEL/PERFCTR include IBS registers of family 10h */
-#define PMU_AMD64_NUM_PERFSEL	6	/* total number of PMCs defined */
-#define PMU_AMD64_NUM_PERFCTR	14	/* total number of PMDs defined */
-#define PMU_AMD64_NUM_COUNTERS	4	/* total numbers of EvtSel/EvtCtr */
-#define PMU_AMD64_COUNTER_WIDTH	48	/* hardware counter bit width */
-#define PMU_AMD64_CNT_MASK_MAX	4 	/* max cnt_mask value */
-#define PMU_AMD64_IBSFETCHCTL_PMC 4	/* IBS: fetch PMC base */
-#define PMU_AMD64_IBSFETCHCTL_PMD 4	/* IBS: fetch PMD base */
-#define PMU_AMD64_IBSOPCTL_PMC 5	/* IBS: op PMC base */
-#define PMU_AMD64_IBSOPCTL_PMD 7	/* IBS: op PMD base */
+/*
+ * PERFSEL/PERFCTR include IBS registers:
+ *
+ *		PMCs	PMDs
+ *
+ * PERFCTRS	6	6
+ * IBS FETCH	1	3
+ * IBS OP	1	7
+ *
+ * total	8	16
+ */
+#define PMU_AMD64_NUM_PERFSEL		8	/* number of PMCs defined */
+#define PMU_AMD64_NUM_PERFCTR		16	/* number of PMDs defined */
+#define PMU_AMD64_NUM_COUNTERS		4	/* number of EvtSel/EvtCtr */
+#define PMU_AMD64_NUM_COUNTERS_F15H	6	/* number of EvtSel/EvtCtr */
+#define PMU_AMD64_COUNTER_WIDTH		48	/* hw counter bit width */
+#define PMU_AMD64_CNT_MASK_MAX		4 	/* max cnt_mask value */
+#define PMU_AMD64_IBSFETCHCTL_PMC	6	/* IBS: fetch PMC base */
+#define PMU_AMD64_IBSFETCHCTL_PMD 	6	/* IBS: fetch PMD base */
+#define PMU_AMD64_IBSOPCTL_PMC		7	/* IBS: op PMC base */
+#define PMU_AMD64_IBSOPCTL_PMD		9	/* IBS: op PMD base */
 
 #define PFMLIB_AMD64_MAX_UMASK	13
 
-- 
1.7.3.4