[perfmon2] [PATCH 3/7] libpfm: add AMD Family 10h RevC (Shanghai) events
Status: Beta
Brought to you by:
seranian
From: Robert R. <rob...@am...> - 2009-02-12 16:41:39
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This patch updates the event table for AMD Family 10h RevC (Shanghai) cpus. Signed-off-by: Robert Richter <rob...@am...> --- lib/amd64_events_fam10h.h | 196 +++++++++++++++++++++++++++++++-------------- 1 files changed, 135 insertions(+), 61 deletions(-) diff --git a/lib/amd64_events_fam10h.h b/lib/amd64_events_fam10h.h index 1aa94d3..587fdc3 100644 --- a/lib/amd64_events_fam10h.h +++ b/lib/amd64_events_fam10h.h @@ -25,13 +25,23 @@ /* History * - * Dec 12 2007 -- Robert Richter, rob...@am... + * Feb 06 2009 -- Robert Richter, rob...@am...: + * + * Update for Family 10h RevC (Shanghai) from: BIOS and Kernel + * Developerâs Guide (BKDG) For AMD Family 10h Processors, 31116 Rev + * 3.20 - February 04, 2009 + * + * + * Dec 12 2007 -- Robert Richter, rob...@am...: * * Created from: BIOS and Kernel Developerâs Guide (BKDG) For AMD * Family 10h Processors, 31116 Rev 3.00 - September 07, 2007 */ static pme_amd64_entry_t amd64_fam10h_pe[]={ + +/* Family 10h RevB, Barcelona */ + /* 0 */{.pme_name = "DISPATCHED_FPU", .pme_code = 0x00, .pme_desc = "Dispatched FPU Operations", @@ -123,11 +133,11 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_numasks = 5, .pme_umasks = { { .pme_uname = "LOW_QW_MOVE_UOPS", - .pme_udesc = "Merging low Quadword move uops", + .pme_udesc = "Merging low quadword move uops", .pme_ucode = 0x01, }, { .pme_uname = "HIGH_QW_MOVE_UOPS", - .pme_udesc = "Merging high Quadword move uops", + .pme_udesc = "Merging high quadword move uops", .pme_ucode = 0x02, }, { .pme_uname = "ALL_OTHER_MERGING_MOVE_UOPS", @@ -323,7 +333,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_numasks = 6, .pme_umasks = { { .pme_uname = "SYSTEM", - .pme_udesc = "Refill from the northbridge", + .pme_udesc = "Refill from the Northbridge", .pme_ucode = 0x01, }, { .pme_uname = "L2_SHARED", @@ -350,7 +360,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ }, /* 19 */{.pme_name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .pme_code = 0x43, - .pme_desc = "Data Cache Refills from the northbridge", + .pme_desc = "Data Cache Refills from the Northbridge", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { @@ -424,7 +434,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_code = 0x45, .pme_desc = "L1 DTLB Miss and L2 DTLB Hit", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, - .pme_numasks = 3, + .pme_numasks = 4, .pme_umasks = { { .pme_uname = "L2_4K_TLB_HIT", .pme_udesc = "L2 4K TLB hit", @@ -434,9 +444,14 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_udesc = "L2 2M TLB hit", .pme_ucode = 0x02, }, + { .pme_uname = "L2_1G_TLB_HIT", + .pme_udesc = "L2 1G TLB hit", + .pme_ucode = 0x04, + .pme_uflags = PFMLIB_AMD64_FAM10H_REV_C, + }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", - .pme_ucode = 0x03, + .pme_ucode = 0x07, }, }, }, @@ -640,7 +655,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_code = 0x6C, .pme_desc = "Northbridge Read Responses by Coherency State", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, - .pme_numasks = 5, + .pme_numasks = 6, .pme_umasks = { { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", @@ -654,24 +669,28 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_udesc = "Shared", .pme_ucode = 0x04, }, + { .pme_uname = "OWNED", + .pme_udesc = "Owned", + .pme_ucode = 0x08, + }, { .pme_uname = "DATA_ERROR", .pme_udesc = "Data Error", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", - .pme_ucode = 0x17, + .pme_ucode = 0x1F, }, }, }, /* 35 */{.pme_name = "QUADWORDS_WRITTEN_TO_SYSTEM", .pme_code = 0x6D, - .pme_desc = "Quadwords Written to System", + .pme_desc = "Octwords Written to System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "QUADWORD_WRITE_TRANSFER", - .pme_udesc = "Quadword write transfer", + .pme_udesc = "Octword write transfer", .pme_ucode = 0x01, }, { .pme_uname = "ALL", @@ -832,7 +851,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_code = 0x8C, .pme_desc = "Instruction Cache Lines Invalidated", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, - .pme_numasks = 5, + .pme_numasks = 3, .pme_umasks = { { .pme_uname = "INVALIDATING_PROBE_NO_IN_FLIGHT", .pme_udesc = "Invalidating probe that did not hit any in-flight instructions.", @@ -842,17 +861,9 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_udesc = "Invalidating probe that hit one or more in-flight instructions.", .pme_ucode = 0x02, }, - { .pme_uname = "SMC_NO_IN_FLIGHT", - .pme_udesc = "SMC that did not hit any in-flight instructions.", - .pme_ucode = 0x04, - }, - { .pme_uname = "SMC_ONE_OR_MORE_IN_FLIGHT", - .pme_udesc = "SMC that hit one or more in-flight instructions", - .pme_ucode = 0x08, - }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", - .pme_ucode = 0x0F, + .pme_ucode = 0x03, }, }, }, @@ -923,7 +934,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x02, }, { .pme_uname = "PACKED_SSE_AND_SSE2", - .pme_udesc = "SSE and SSE2 instructions", + .pme_udesc = "SSE instructions (SSE, SSE2, SSE3, and SSE4A)", .pme_ucode = 0x04, }, { .pme_uname = "ALL", @@ -1060,7 +1071,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_code = 0xE0, .pme_desc = "DRAM Accesses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, - .pme_numasks = 9, + .pme_numasks = 7, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "DCT0 Page hit", @@ -1086,17 +1097,9 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_udesc = "DCT1 Page Conflict", .pme_ucode = 0x20, }, - { .pme_uname = "WRITE_REQUEST", - .pme_udesc = "Write request", - .pme_ucode = 0x40, - }, - { .pme_uname = "READ_REQUEST", - .pme_udesc = "Read request", - .pme_ucode = 0x80, - }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", - .pme_ucode = 0xFF, + .pme_ucode = 0x3F, }, }, }, @@ -1303,7 +1306,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x10, }, { .pme_uname = "READ_TO_DIRTY", - .pme_udesc = "Change to Dirty (first store to clean block already in cache)", + .pme_udesc = "Change-to-Dirty (first store to clean block already in cache)", .pme_ucode = 0x20, }, { .pme_uname = "ALL", @@ -1323,15 +1326,15 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x01, }, { .pme_uname = "NON_POSTED_WRITE_DWORD", - .pme_udesc = "Non-Posted SzWr Dword (1-16 dwords) Legacy or mapped IO, typically 1 dword", + .pme_udesc = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD", .pme_ucode = 0x02, }, { .pme_uname = "POSTED_WRITE_BYTE", - .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of", + .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .pme_ucode = 0x04, }, { .pme_uname = "POSTED_WRITE_DWORD", - .pme_udesc = "Posted SzWr Dword (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also", + .pme_udesc = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .pme_ucode = 0x08, }, { .pme_uname = "READ_BYTE_4_BYTES", @@ -1339,7 +1342,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x10, }, { .pme_uname = "READ_DWORD_1_16_DWORDS", - .pme_udesc = "SzRd Dword (1-16 dwords) Block-oriented DMA reads, typically cache-line size", + .pme_udesc = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .pme_ucode = 0x20, }, { .pme_uname = "ALL", @@ -1587,7 +1590,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", - .pme_udesc = "Change to Dirty", + .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_0", @@ -1631,7 +1634,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", - .pme_udesc = "Change to Dirty", + .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_0", @@ -1675,7 +1678,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", - .pme_udesc = "Change to Dirty", + .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_4", @@ -1719,7 +1722,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", - .pme_udesc = "Change to Dirty", + .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_4", @@ -1839,23 +1842,23 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", - .pme_udesc = "Command dword sent", + .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", - .pme_udesc = "Data dword sent", + .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", - .pme_udesc = "Buffer release dword sent", + .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", - .pme_udesc = "Nop dword sent (idle)", + .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", - .pme_udesc = "Address extension dword sent", + .pme_udesc = "Address extension DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", @@ -1879,23 +1882,23 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", - .pme_udesc = "Command dword sent", + .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", - .pme_udesc = "Data dword sent", + .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", - .pme_udesc = "Buffer release dword sent", + .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", - .pme_udesc = "Nop dword sent (idle)", + .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", - .pme_udesc = "Address extension dword sent", + .pme_udesc = "Address extension DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", @@ -1919,23 +1922,23 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", - .pme_udesc = "Command dword sent", + .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", - .pme_udesc = "Data dword sent", + .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", - .pme_udesc = "Buffer release dword sent", + .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", - .pme_udesc = "Nop dword sent (idle)", + .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", - .pme_udesc = "Address extension dword sent", + .pme_udesc = "Address extension DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", @@ -1959,23 +1962,23 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", - .pme_udesc = "Command dword sent", + .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", - .pme_udesc = "Data dword sent", + .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", - .pme_udesc = "Buffer release dword sent", + .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", - .pme_udesc = "Nop dword sent (idle)", + .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", - .pme_udesc = "Address extension dword sent", + .pme_udesc = "Address DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", @@ -2144,6 +2147,77 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={ }, }, }, + +/* Family 10h RevC, Shanghai */ + +/* 114 */{.pme_name = "PAGE_SIZE_MISMATCHES", + .pme_code = 0x165, + .pme_desc = "Page Size Mismatches", + .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_C, + .pme_numasks = 4, + .pme_umasks = { + { .pme_uname = "GUEST_LARGER", + .pme_udesc = "Guest page size is larger than the host page size.", + .pme_ucode = 0x01, + }, + { .pme_uname = "MTRR_MISMATCH", + .pme_udesc = "MTRR mismatch.", + .pme_ucode = 0x02, + }, + { .pme_uname = "HOST_LARGER", + .pme_udesc = "Host page size is larger than the guest page size.", + .pme_ucode = 0x04, + }, + { .pme_uname = "ALL", + .pme_udesc = "All sub-events selected", + .pme_ucode = 0x07, + }, + }, + }, +/* 115 */{.pme_name = "RETIRED_X87_OPS", + .pme_code = 0x1C0, + .pme_desc = "Retired x87 Floating Point Operations", + .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_C, + .pme_numasks = 4, + .pme_umasks = { + { .pme_uname = "ADD_SUB_OPS", + .pme_udesc = "Add/subtract ops", + .pme_ucode = 0x01, + }, + { .pme_uname = "MUL_OPS", + .pme_udesc = "Multiply ops", + .pme_ucode = 0x02, + }, + { .pme_uname = "DIV_OPS", + .pme_udesc = "Divide ops", + .pme_ucode = 0x04, + }, + { .pme_uname = "ALL", + .pme_udesc = "All sub-events selected", + .pme_ucode = 0x07, + }, + }, + }, +/* 116 */{.pme_name = "IBS_OPS_TAGGED", + .pme_code = 0x1CF, + .pme_desc = "IBS Ops Tagged", + .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, + }, +/* 117 */{.pme_name = "LFENCE_INST_RETIRED", + .pme_code = 0x1D3, + .pme_desc = "LFENCE Instructions Retired", + .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, + }, +/* 118 */{.pme_name = "SFENCE_INST_RETIRED", + .pme_code = 0x1D4, + .pme_desc = "SFENCE Instructions Retired", + .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, + }, +/* 119 */{.pme_name = "MFENCE_INST_RETIRED", + .pme_code = 0x1D5, + .pme_desc = "MFENCE Instructions Retired", + .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, + }, }; #define PME_AMD64_FAM10H_EVENT_COUNT (sizeof(amd64_fam10h_pe)/sizeof(pme_amd64_entry_t)) -- 1.6.1.2 |