Re: [perfmon2] [patch 1/5] libpfm: Add IBS support for AMD CPUs

[Robert R. <rob...@am...>]

On 04.04.08 11:17:35, stephane eranian wrote:
> Yes, I do. No need to expose fields the user cannot influence on input.

I will rework this section.

> The rule of libpfm is that PMD related to events (hosted in counting PMD)
> are ALWAYS put first in pfp_pmds[] AND in the order the events where
> specified. Here is an example:
> 
>    I want to measure events A, B. If event A is measured by PMD3 and B
> by PMD1, then
>    pfp_pmd[0].reg_num = 3
>    pfp_pmd[1].reg_num = 1
> 
> After those PMDs, there can be more PMDs but there is no order
> guarantee. Those PMDs
> are related to extended features which use PMDs. The values return by
> libpfm for those
> are mostly informational. It is expected that programs using extended
> features KNOW
> which PMD to use and know how to decode their content.

The issue becomes visible in setup_pmu_ibsop() of smpl_amd64_ibs.c.
After calling the dispatch function I want to enable sampling for IBS.

pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY;
...
pd[0].reg_smpl_pmds[0] = ...
...

For this I have to know which register of outp.pfp_pmds is for
IBS. When using only IBS, this is always the first register. But it is
not necessarily known, if counter or other features of the PMU are
used. The programm does not know the index of the register and thus,
it may only use the base registers.

Alternately one could implement a search routine that scans
reg_num for the IbsOpCtl register, but this may also change e.g. on a
CPU with more counters. So I see now other way than the library has to
tell the index.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: rob...@am...