Re: [perfmon2] MIPS patches 3/3 - reserved bits mask patch

[Philip M. <mu...@cs...>]

On Dec 13, 2007, at 1:18 PM, Stephane Eranian wrote:

> PHil,
>
> On Thu, Dec 13, 2007 at 11:54:38AM +0100, Philip Mucci wrote:
>>
>> Congrats on getting this working. However, the below patch is correct
>> for the 64 bit MIPS cores.
>>
>> For the 5K series, it is only a 4 bit field. For the 20K series, it
>> is a 6 bit field, however only the bottom 4 bits have valid events
>> and thus, it should be set as a 4 bit field. events 0x10-0x3f are
>> reserved and undefined.
>>
> Let me make sure I understand:
> 	- 5k   : 4 bits
> 	- 20k  : 4 bits
>

Correct!

>> I've checked all the 32 bit cores, and for them, your patch is
>> correct. They all seem to have both a 6 bit event field and events
>> that span the range.
>>
>> Stefane, can you make the change in your patch?
>>
> Did I get this right?
>
>> Note that you will have to make some similar changes to the libpfm
>> code for MIPS as there is a mask in there for the event field width.
>>


> Please provide a patch.
>

Ok, stay tuned.

> --
> -Stephane