Re: [perfmon2] [PATCH] 1/1 - add kernel support for POWER4 and POWER6 to perfmon2

[Stephane E. <er...@hp...>]

Phil,

On Thu, Nov 29, 2007 at 12:07:52PM +0100, Philip Mucci wrote:
> Hi folks,
> 
> The Sparc64 port has registers like this as well. While I've long  
> argued that perfmon2 should have a general mechanism to support  
> counters without an interrupt bit (indeed even architectures that  
> don't give you a PMU interrupt), I'd be just as happy in this case if:
> 
> a) perfmon complained if the user requested notification/sampling on  
> a non-interrupting counter
> b) PAPI had knowledge of counters that could not interrupt
> 
I looked at the code again. I had forgotten about something which was
added for Barcelona. I was wrong about perfmon2 not knowing about
interrupt-generating data register. There is a flag (PFM_REG_INTR)
which is used to build a bitmask of interrupt-generating pmds.
The idea is to limit scanning of PMD on interrupt to those known
to generate some.

Today, pfm_write_pmds() ignores PFM_REGFL_OVFL_NOTIFY on non counter.
I think we can easily change that to return an error when set on
non-interrupting data registers. I'll make that change if that helps.