[Pcb-bugs] [Bug 1035979] Re: default silk layer names are the same for top and bottom

[Bert T. <10...@bu...>]

Hi Kai-Martin and all,

I have updated the topic branch "LP1035979" onto git://git.geda-
project.org/pcb with the above mentioned patches.

Seems to work as advertised.

Kind regards,

Bert Timmerman.

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https://bugs.launchpad.net/bugs/1035979

Title:
  default silk layer names are the same for top and bottom

Status in PCB: Printed Circuit Board CAD package:
  In Progress

Bug description:
  The default layer stack as set by PCB for a new layout contains two
  silk layers. Both of them bear the same name "silk". The name does not
  actually show in the GUI. Still, it is irritating when editing the pcb
  file manually. In addition, the duplicate name complicates scripted
  manipulation of the file.

  The attached patch sets the default name to "top silk" and "bottom silk" respectively.
  ---<)kaimartin(>---

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