Re: Preliminary Pentium M support

[Philippe E. <ph...@wa...>]

On Mon, 16 Feb 2004 at 22:28 +0000, John Levon wrote:

> On Mon, Feb 16, 2004 at 03:26:21PM -0500, Will Cohen wrote:
> 
> > Maybe
> > 
> > 	if (model->reset_int_hw)
> > 	      apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) &
> > 			~APIC_LVT_MASKED);
> 
> That would be fine.
> 
> > should be fairly straightforward to adapt that code to get the cost of 
> > the actual nmi interrupt handler. This would give us a better handle on 
> > the overall cost of adding samples. It would also give us an idea how 
> > much a performance difference this type of change would make in the 
> > interrupt routine.
> 
> I've  been meeaning to do something like this for a long, long time

nobody can do a kernel compile test with and w/o this chunk ?

And anyway if you want to optimize this function it's better to use
rdpmc rather rdmsr, it's orthogonal but results:

http://marc.theaimsgroup.com/?l=oprofile-list&m=105840481716898&w=2

show it save 60 cycles on P6 core and

http://marc.theaimsgroup.com/?l=oprofile-list&m=105840481716899&w=2

show kernel compile doesn't improve, it's only measurable on bz2 test,
so I guess it's not really worth to add a conditinal branch here
(it'll surely not good for pentium mobile, the branch will be
mispredicted, if we add a likely or unlikely we will pessimize either
P6 or pentium mobile) We increase pressure on BTB buffer too.

if (model->int_hw_reset)

In short word I'm not conveincing we need to optimize that.


regards,
Phil