Menu
▾
▴
[oprof-cvs] CVS: oprofile-www/docs amd-family10-events.php, NONE, 1.1 amd-family11h-events.php, NONE, 1.1 arm-mpcore-events.php, NONE, 1.1 arm-v6-events.php, NONE, 1.1 arm-v7-events.php, NONE, 1.1 arv32-events.php, NONE, 1.1 intel-atom-events.php, NONE, 1.1 intel-core-events.php, NONE, 1.1 intel-core2-events.php, NONE, 1.1 intel-corei7-events.php, NONE, 1.1 intel-perfmon-events.php, NONE, 1.1 ppc-7450-events.php, NONE, 1.1 ppc-e300-events.php, NONE, 1.1 ppc-e500v2-events, NONE, 1.1 ppc-e500v2-events.php, NONE, 1.1 ppc64-970MP-events.php, NONE, 1.1 ppc64-cellBE-events.php, NONE, 1.1 ppc64-compatv1-events.php, NONE, 1.1 ppc64-pa6t-events.php, NONE, 1.1 ppc64-power5p-events.php, NONE, 1.1 ppc64-power5pp-events.php, NONE, 1.1 ppc64-power6-events.php, NONE, 1.1 ppc64-power7-events.php, NONE, 1.1 amd-hammer-events.php, 1.1, 1.2
Update of /cvsroot/oprofile/oprofile-www/docs In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv16856/docs Modified Files: amd-hammer-events.php Added Files: amd-family10-events.php amd-family11h-events.php arm-mpcore-events.php arm-v6-events.php arm-v7-events.php arv32-events.php intel-atom-events.php intel-core-events.php intel-core2-events.php intel-corei7-events.php intel-perfmon-events.php ppc-7450-events.php ppc-e300-events.php ppc-e500v2-events ppc-e500v2-events.php ppc64-970MP-events.php ppc64-cellBE-events.php ppc64-compatv1-events.php ppc64-pa6t-events.php ppc64-power5p-events.php ppc64-power5pp-events.php ppc64-power6-events.php ppc64-power7-events.php Log Message: Add new php files for generating missing event descriptions for newly-added processors --- NEW FILE: amd-family10-events.php --- <?php require("../start_page.php"); start_page("docs/amd-family10-events.php", "AMD64 family 10 performance counter events"); ?> <h2>AMD family 10 events</h2> <p> This is a list of AMD64 family 10's CPU's performance counter event types. Please see the AMD Optimization Manual for more details. Note that any counter can be used for any event. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: amd-family11h-events.php --- <?php require("../start_page.php"); start_page("docs/amd-family11h-events.php", "AMD64 family 11h performance counter events"); ?> <h2>AMD family 11h events</h2> <p> This is a list of AMD64 family 11h's CPU's performance counter event types. See BIOS and Kernel Developer's Guide for AMD Family 11h Processors, (31116.pdf), Section 3.14.</p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: arm-mpcore-events.php --- <?php require("../start_page.php"); start_page("docs/arm-mpcore-events.php", "ARM MPCore processor events"); ?> <h2>ARM MPCore events</h2> <p> This is a list of all ARM MPCore's performance counter event types. Please see ARM11 MPCore Processor Technical Reference Manual r1p0, Page 3-70, performance counters. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: arm-v6-events.php --- <?php require("../start_page.php"); start_page("docs/arm-v6-events.php", "ARM V6 processor events"); ?> <h2>ARM V6 events</h2> <p> This is a list of all ARM V6's performance counter event types. Please see ARM11 Technical Reference Manual. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: arm-v7-events.php --- <?php require("../start_page.php"); start_page("docs/arm-v7-events.php", "ARM V7 processor events"); ?> <h2>ARM V7 events</h2> <p> This is a list of all ARM V7's performance counter event types. Please see ARM11 Technical Reference Manual. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: arv32-events.php --- <?php require("../start_page.php"); start_page("docs/arv32-events.php", "ARV32 processor events"); ?> <h2>ARV32 events</h2> <p> This is a list of all ARV32's performance counter event types. See <a href="http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf">AVR32 Architecture Manual, Chapter 6: Performance Counters</a>. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: intel-atom-events.php --- <?php require("../start_page.php"); start_page("docs/intel-atom-events.php", "First generation Intel Atom performance counter events"); ?> <h2>First generation Intel Atom events</h2> <p> This is a list of all Intel Atom's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: intel-core-events.php --- <?php require("../start_page.php"); start_page("docs/intel-core-events.php", "Intel Core Solo/Duo performance counter events"); ?> <h2>Intel Core Solo/Duo events</h2> <p> This is a list of all Core Solo/Duo CPU's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A. Oprofile use syntethised events and doen't provide a low-level access to Core hardware, so the Intel manual is usefull mainly for people trying to add new events in Oprofile rather for end-user. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: intel-core2-events.php --- <?php require("../start_page.php"); start_page("docs/intel-core2-events.php", "Intel Core 2 performance counter events"); ?> <h2>Intel Core 2 events</h2> <p> This is a list of all Core 2 CPU's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A. Oprofile use syntethised events and doen't provide a low-level access to Core 2 hardware, so the Intel manual is usefull mainly for people trying to add new events in Oprofile rather for end-user. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: intel-corei7-events.php --- <?php require("../start_page.php"); start_page("docs/intel-corei7-events.php", "Intel Core i7 (Nehalem) performance counter events"); ?> <h2>Intel Core i7 (Nehalem) events</h2> <p> This is a list of all Core i7 CPU's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A. </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: intel-perfmon-events.php --- <?php require("../start_page.php"); start_page("docs/intel-perfmon-events.php", "Intel architectural perfmon performance counter events"); ?> <h2>Intel architectural perfmon</h2> <p> This is a list of architected performance counter events for newer Intel family processors (Core1+). See Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B (Document 253669) Chapter 18 for architectural perfmon events.</p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc-7450-events.php --- <?php require("../start_page.php"); start_page("docs/ppc-7450-events.php", "PPC 7450 performance counter events"); ?> <h2>PPC 7450 events</h2> <p> This is a list of PPC 7450's performance counter event types. Please see MPC7450 RISC Microprocessor Family Reference Manual, Chapter 11: Performance Monitor. Downloadable from <a href="http://www.freescale.com">freescale.com</a> </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc-e300-events.php --- <?php require("../start_page.php"); start_page("docs/ppc-e300-events.php", "PPC E300 performance counter events"); ?> <h2>PPC E300 events</h2> <p> This is a list of PPC E300's performance counter event types. Please see PowerPC e300 Core Reference Manual. Downloadable from <a href="http://www.freescale.com">freescale.com</a> </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc-e500v2-events --- <tr><td>CPU_CLK</td><td> Cycles </td><td> all</td><td> </td> </tr> <tr><td>COMPLETED_INSNS</td><td> Completed Instructions (0, 1, or 2 per cycle) </td><td> all</td><td> </td> </tr> <tr><td>COMPLETED_OPS</td><td> Completed Micro-ops (counts 2 for load/store w/update) </td><td> all</td><td> </td> </tr> <tr><td>INSTRUCTION_FETCHES</td><td> Instruction fetches </td><td> all</td><td> </td> </tr> <tr><td>DECODED_OPS</td><td> Micro-ops decoded </td><td> all</td><td> </td> </tr> <tr><td>COMPLETED_BRANCHES</td><td> Branch Instructions completed </td><td> all</td><td> </td> </tr> <tr><td>COMPLETED_LOAD_OPS</td><td> Load micro-ops completed </td><td> all</td><td> </td> </tr> <tr><td>COMPLETED_STORE_OPS</td><td> Store micro-ops completed </td><td> all</td><td> </td> </tr> <tr><td>COMPLETION_REDIRECTS</td><td> Number of completion buffer redirects </td><td> all</td><td> </td> </tr> <tr><td>BRANCHES_FINISHED</td><td> Branches finished </td><td> all</td><td> </td> </tr> <tr><td>TAKEN_BRANCHES_FINISHED</td><td> Taken branches finished </td><td> all</td><td> </td> </tr> <tr><td>BIFFED_BRANCHES_FINISHED</td><td> Biffed branches finished </td><td> all</td><td> </td> </tr> <tr><td>BRANCHES_MISPREDICTED</td><td> Branch instructions mispredicted due to direction, target, or IAB prediction </td><td> all</td><td> </td> </tr> <tr><td>BRANCHES_MISPREDICTED_DIRECTION</td><td> Branches mispredicted due to direction prediction </td><td> all</td><td> </td> </tr> <tr><td>BTB_HITS</td><td> Branches that hit in the BTB, or missed but are not taken </td><td> all</td><td> </td> </tr> <tr><td>DECODE_STALLED</td><td> Cycles the instruction buffer was not empty, but 0 instructions decoded </td><td> all</td><td> </td> </tr> <tr><td>ISSUE_STALLED</td><td> Cycles the issue buffer is not empty but 0 instructions issued </td><td> all</td><td> </td> </tr> <tr><td>BRANCH_ISSUE_STALLED</td><td> Cycles the branch buffer is not empty but 0 instructions issued </td><td> all</td><td> </td> </tr> <tr><td>SRS0_SCHEDULE_STALLED</td><td> Cycles SRS0 is not empty but 0 instructions scheduled </td><td> all</td><td> </td> </tr> <tr><td>SRS1_SCHEDULE_STALLED</td><td> Cycles SRS1 is not empty but 0 instructions scheduled </td><td> all</td><td> </td> </tr> <tr><td>VRS_SCHEDULE_STALLED</td><td> Cycles VRS is not empty but 0 instructions scheduled </td><td> all</td><td> </td> </tr> <tr><td>LRS_SCHEDULE_STALLED</td><td> Cycles LRS is not empty but 0 instructions scheduled </td><td> all</td><td> </td> </tr> <tr><td>BRS_SCHEDULE_STALLED</td><td> Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events </td><td> all</td><td> </td> </tr> <tr><td>TOTAL_TRANSLATED</td><td> Total Ldst microops translated. </td><td> all</td><td> </td> </tr> <tr><td>LOADS_TRANSLATED</td><td> Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.) </td><td> all</td><td> </td> </tr> <tr><td>STORES_TRANSLATED</td><td> Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.) </td><td> all</td><td> </td> </tr> <tr><td>TOUCHES_TRANSLATED</td><td> Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.) </td><td> all</td><td> </td> </tr> <tr><td>CACHEOPS_TRANSLATED</td><td> Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi) </td><td> all</td><td> </td> </tr> <tr><td>CACHEINHIBITED_ACCESSES_TRANSLATED</td><td> Number of cache inhibited accesses translated </td><td> all</td><td> </td> </tr> <tr><td>GUARDED_LOADS_TRANSLATED</td><td> Number of guarded loads translated </td><td> all</td><td> </td> </tr> <tr><td>WRITETHROUGH_STORES_TRANSLATED</td><td> Number of write-through stores translated </td><td> all</td><td> </td> </tr> <tr><td>MISALIGNED_ACCESSES_TRANSLATED</td><td> Number of misaligned load or store accesses translated. </td><td> all</td><td> </td> </tr> <tr><td>TOTAL_ALLOCATED_DLFB</td><td> Total allocated to dLFB </td><td> all</td><td> </td> </tr> <tr><td>LOADS_TRANSLATED_ALLOCATED_DLFB</td><td> Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.) </td><td> all</td><td> </td> </tr> <tr><td>STORES_COMPLETED_ALLOCATED_DLFB</td><td> Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.) </td><td> all</td><td> </td> </tr> <tr><td>TOUCHES_TRANSLATED_ALLOCATED_DLFB</td><td> Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.) </td><td> all</td><td> </td> </tr> <tr><td>STORES_COMPLETED</td><td> Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.) </td><td> all</td><td> </td> </tr> <tr><td>DL1_LOCKS</td><td> Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.) </td><td> all</td><td> </td> </tr> <tr><td>DL1_RELOADS</td><td> This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason. </td><td> all</td><td> </td> </tr> <tr><td>DL1_CASTOUTS</td><td> dL1 castouts. Does not count castouts due to DCBF. </td><td> all</td><td> </td> </tr> <tr><td>DETECTED_REPLAYS</td><td> Times detected replay condition - Load miss with dLFB full. </td><td> all</td><td> </td> </tr> <tr><td>LOAD_MISS_QUEUE_FULL_REPLAYS</td><td> Load miss with load queue full. </td><td> all</td><td> </td> </tr> <tr><td>LOAD_GUARDED_MISS_NOT_LAST_REPLAYS</td><td> Load guarded miss when the load is not yet at the bottom of the completion buffer. </td><td> all</td><td> </td> </tr> <tr><td>STORE_TRANSLATED_QUEUE_FULL_REPLAYS</td><td> Translate a store when the StQ is full. </td><td> all</td><td> </td> </tr> <tr><td>ADDRESS_COLLISION_REPLAYS</td><td> Address collision. </td><td> all</td><td> </td> </tr> <tr><td>DMMU_MISS_REPLAYS</td><td> DMMU_MISS_REPLAYS : DMMU miss. </td><td> all</td><td> </td> </tr> <tr><td>DMMU_BUSY_REPLAYS</td><td> DMMU_BUSY_REPLAYS : DMMU busy. </td><td> all</td><td> </td> </tr> <tr><td>SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS</td><td> Second part of misaligned access when first part missed in cache. </td><td> all</td><td> </td> </tr> <tr><td>LOAD_MISS_DLFB_FULL_CYCLES</td><td> Cycles stalled on replay condition - Load miss with dLFB full. </td><td> all</td><td> </td> </tr> <tr><td>LOAD_MISS_QUEUE_FULL_CYCLES</td><td> Cycles stalled on replay condition - Load miss with load queue full. </td><td> all</td><td> </td> </tr> <tr><td>LOAD_GUARDED_MISS_NOT_LAST_CYCLES</td><td> Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer. </td><td> all</td><td> </td> </tr> <tr><td>STORE_TRANSLATED_QUEUE_FULL_CYCLES</td><td> Cycles stalled on replay condition - Translate a store when the StQ is full. </td><td> all</td><td> </td> </tr> <tr><td>ADDRESS_COLLISION_CYCLES</td><td> Cycles stalled on replay condition - Address collision. </td><td> all</td><td> </td> </tr> <tr><td>DMMU_MISS_CYCLES</td><td> Cycles stalled on replay condition - DMMU miss. </td><td> all</td><td> </td> </tr> <tr><td>DMMU_BUSY_CYCLES</td><td> Cycles stalled on replay condition - DMMU busy. </td><td> all</td><td> </td> </tr> <tr><td>SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES</td><td> Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache. </td><td> all</td><td> </td> </tr> <tr><td>IL1_LOCKS</td><td> Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.) </td><td> all</td><td> </td> </tr> <tr><td>IL1_FETCH_RELOADS</td><td> This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch. </td><td> all</td><td> </td> </tr> <tr><td>FETCHES</td><td> Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch) </td><td> all</td><td> </td> </tr> <tr><td>IMMU_TLB4K_RELOADS</td><td> iMMU TLB4K reloads </td><td> all</td><td> </td> </tr> <tr><td>IMMU_VSP_RELOADS</td><td> iMMU VSP reloads </td><td> all</td><td> </td> </tr> <tr><td>DMMU_TLB4K_RELOADS</td><td> dMMU TLB4K reloads </td><td> all</td><td> </td> </tr> <tr><td>DMMU_VSP_RELOADS</td><td> dMMU VSP reloads </td><td> all</td><td> </td> </tr> <tr><td>L2MMU_MISSES</td><td> Counts iTLB/dTLB error interrupt </td><td> all</td><td> </td> </tr> <tr><td>BIU_MASTER_REQUESTS</td><td> Number of master transactions. (Number of master TSs.) </td><td> all</td><td> </td> </tr> <tr><td>BIU_MASTER_I_REQUESTS</td><td> Number of master I-Side transactions. (Number of master I-Side TSs.) </td><td> all</td><td> </td> </tr> <tr><td>BIU_MASTER_D_REQUESTS</td><td> Number of master D-Side transactions. (Number of master D-Side TSs.) </td><td> all</td><td> </td> </tr> <tr><td>BIU_MASTER_D_CASTOUT_REQUESTS</td><td> Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.) </td><td> all</td><td> </td> </tr> <tr><td>BIU_MASTER_RETRIES</td><td> Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.) </td><td> all</td><td> </td> </tr> <tr><td>SNOOP_REQUESTS</td><td> Number of externally generated snoop requests. (Counts snoop TSs.) </td><td> all</td><td> </td> </tr> <tr><td>SNOOP_HITS</td><td> Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared) </td><td> all</td><td> </td> </tr> <tr><td>SNOOP_PUSHES</td><td> Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.) </td><td> all</td><td> </td> </tr> <tr><td>SNOOP_RETRIES</td><td> Number of snoop requests retried. (Counts snoop ARTRYs.) </td><td> all</td><td> </td> </tr> <tr><td>PMC0_OVERFLOW</td><td> Counts the number of times PMC0[32] transitioned from 1 to 0. </td><td> all</td><td> </td> </tr> <tr><td>PMC1_OVERFLOW</td><td> Counts the number of times PMC1[32] transitioned from 1 to 0. </td><td> all</td><td> </td> </tr> <tr><td>PMC2_OVERFLOW</td><td> Counts the number of times PMC2[32] transitioned from 1 to 0. </td><td> all</td><td> </td> </tr> <tr><td>PMC3_OVERFLOW</td><td> Counts the number of times PMC3[32] transitioned from 1 to 0. </td><td> all</td><td> </td> </tr> <tr><td>INTERRUPTS</td><td> Number of interrupts taken </td><td> all</td><td> </td> </tr> <tr><td>EXTERNAL_INTERRUPTS</td><td> Number of external input interrupts taken </td><td> all</td><td> </td> </tr> <tr><td>CRITICAL_INTERRUPTS</td><td> Number of critical input interrupts taken </td><td> all</td><td> </td> </tr> <tr><td>SC_TRAP_INTERRUPTS</td><td> Number of system call and trap interrupts </td><td> all</td><td> </td> </tr> --- NEW FILE: ppc-e500v2-events.php --- <?php require("../start_page.php"); start_page("docs/ppc-e500v2-events.php", "PPC E500 v2 performance counter events"); ?> <h2>PPC E500 v2 events</h2> <p> This is a list of PPC E500 v2's performance counter event types. Please see PowerPC e500 Core Complex Reference Manual Chapter 7: Performance Monitor. Downloadable from <a href="http://www.freescale.com">freescale.com</a> </p> <?php start_event_table(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-970MP-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-970MP-events.php", "ppc64 970MP processor events"); ?> <h2>ppc64 970MP events</h2> <p> This is a list of all ppc64 970MP's performance counter event types. </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-cellBE-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-cellBE-events.php", "ppc64 Cell BE processor events"); ?> <h2>ppc64 Cell BE events</h2> <p> This is a list of all ppc64 Cell Broadband Engine's performance counter event types. </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-compatv1-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-compatv1-events.php", "IBM PPC64 processor architected events, version 1"); ?> <h2>IBM PPC64 processor compat mode events, version 1</h2> <p> This is a list of architected performance counter events for newer IBM POWER processors (POWER6 and later). </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-pa6t-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-pa6t-events.php", "ppc64 PA6T processor events"); ?> <h2>ppc64 PA6T events</h2> <p> This is a list of all ppc64 PA6T's performance counter event types. </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-power5p-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-power5p-events.php", "ppc64 POWER5+ processor events"); ?> <h2>ppc64 POWER5+ events</h2> <p> This is a list of all ppc64 POWER5+'s performance counter event types. </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-power5pp-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-power5pp-events.php", "ppc64 POWER5++ processor events"); ?> <h2>ppc64 POWER5++ events</h2> <p> This is a list of all ppc64 POWER5++'s performance counter event types. </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-power6-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-power6-events.php", "ppc64 POWER6 processor events"); ?> <h2>ppc64 POWER6 events</h2> <p> This is a list of all ppc64 POWER6's performance counter event types. </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> --- NEW FILE: ppc64-power7-events.php --- <?php require("../start_page.php"); start_page("docs/ppc64-power7-events.php", "ppc64 POWER7 processor events"); ?> <h2>ppc64 POWER7 events</h2> <p> This is a list of all ppc64 POWER7's performance counter event types. </p> <?php start_event_table_ppc64(); ?> <?php readfile(basename(__FILE__, ".php")); ?> <?php end_table(); ?> <?php require("$top/end_page.php"); end_page("/docs/" . basename(__FILE__)); ?> Index: amd-hammer-events.php =================================================================== RCS file: /cvsroot/oprofile/oprofile-www/docs/amd-hammer-events.php,v retrieving revision 1.1 retrieving revision 1.2 diff -u -p -d -r1.1 -r1.2 --- amd-hammer-events.php 23 Sep 2008 21:41:18 -0000 1.1 +++ amd-hammer-events.php 5 Aug 2009 21:40:29 -0000 1.2 @@ -1,9 +1,9 @@ -<?php require("../start_page.php"); start_page("docs/amd-hammer-events.php", "AMD64 processors performance counter events"); ?> +<?php require("../start_page.php"); start_page("docs/amd-hammer-events.php", "AMD64 Hammer processor performance counter events"); ?> -<h2>AMD events</h2> +<h2>AMD Hammer events</h2> <p> -This is a list of AMD64 processors CPU's performance counter event types. Please see the AMD Optimization Manual +This is a list of AMD64 Hammer's CPU's performance counter event types. Please see the AMD Optimization Manual for more details. Note that any counter can be used for any event. </p> |