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[PATCH] ARM: add support for A8/A9/A9mpcore, L2 cache, SCU, SMP
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From: Jon C. <Jon...@ar...> - 2009-03-09 17:36:45
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Changes to Oprofile 0.9.4 to support
- ARM Cortex A8, A9, A9mpcore cpus
- up to 64 event counters
- SMP on ARM
- collection of events from L220/L230 L2 cache controller
- collection of events from 11mpcore Snoop Control Unit (SCU)
This compiles cleanly on arm-none-linux-gnueabi-gcc-4.1.1, and I've
tested them as far as I can.
There are some corresponding Linux kernel patches included in the
upcoming 2.6.28-arm1 patch.
There are also a few changes to the opcontrol script which I made so
that it worked on the shell
I was using - you may prefer to ignore these, and I'll maintain locally.
Or they may work
fine with your shell.
Signed-off-by: Jon Callan <jon...@ar...>
diff -NaurBb oprofile-0.9.4.dist/events/Makefile.am
oprofile-0.9.4.mod/events/Makefile.am
--- oprofile-0.9.4.dist/events/Makefile.am 2008-02-22
16:17:48.000000000 +0000
+++ oprofile-0.9.4.mod/events/Makefile.am 2009-03-09
12:37:17.000000000 +0000
@@ -30,8 +30,11 @@
x86-64/family10/events x86-64/family10/unit_masks \
arm/xscale1/events arm/xscale1/unit_masks \
arm/xscale2/events arm/xscale2/unit_masks \
- arm/armv6/events arm/armv6/unit_masks \
- arm/mpcore/events arm/mpcore/unit_masks \
+ arm/v6/events arm/v6/unit_masks \
+ arm/11mpcore/events arm/11mpcore/unit_masks \
+ arm/a8/events arm/a8/unit_masks \
+ arm/a9/events arm/a9/unit_masks \
+ arm/a9mpcore/events arm/a9mpcore/unit_masks \
avr32/events avr32/unit_masks \
mips/20K/events mips/20K/unit_masks \
mips/24K/events mips/24K/unit_masks \
diff -NaurBb oprofile-0.9.4.dist/events/Makefile.in
oprofile-0.9.4.mod/events/Makefile.in
--- oprofile-0.9.4.dist/events/Makefile.in 2008-07-18
00:14:45.000000000 +0100
+++ oprofile-0.9.4.mod/events/Makefile.in 2009-03-09
12:37:17.000000000 +0000
@@ -239,8 +239,11 @@
x86-64/family10/events x86-64/family10/unit_masks \
arm/xscale1/events arm/xscale1/unit_masks \
arm/xscale2/events arm/xscale2/unit_masks \
- arm/armv6/events arm/armv6/unit_masks \
- arm/mpcore/events arm/mpcore/unit_masks \
+ arm/v6/events arm/v6/unit_masks \
+ arm/11mpcore/events arm/11mpcore/unit_masks \
+ arm/a8/events arm/a8/unit_masks \
+ arm/a9/events arm/a9/unit_masks \
+ arm/a9mpcore/events arm/a9mpcore/unit_masks \
avr32/events avr32/unit_masks \
mips/20K/events mips/20K/unit_masks \
mips/24K/events mips/24K/unit_masks \
@@ -310,7 +313,7 @@
distdir: $(DISTFILES)
- $(mkdir_p) $(distdir)/alpha/ev4 $(distdir)/alpha/ev5
$(distdir)/alpha/ev6 $(distdir)/alpha/ev67 $(distdir)/alpha/pca56
$(distdir)/arm/armv6 $(distdir)/arm/mpcore $(distdir)/arm/xscale1
$(distdir)/arm/xscale2 $(distdir)/avr32 $(distdir)/i386/athlon
$(distdir)/i386/core $(distdir)/i386/core_2 $(distdir)/i386/p4
$(distdir)/i386/p4-ht $(distdir)/i386/p6_mobile $(distdir)/i386/pii
$(distdir)/i386/piii $(distdir)/i386/ppro $(distdir)/ia64/ia64
$(distdir)/ia64/itanium $(distdir)/ia64/itanium2 $(distdir)/mips/20K
$(distdir)/mips/24K $(distdir)/mips/25K $(distdir)/mips/34K
$(distdir)/mips/5K $(distdir)/mips/r10000 $(distdir)/mips/r12000
$(distdir)/mips/rm7000 $(distdir)/mips/rm9000 $(distdir)/mips/sb1
$(distdir)/mips/vr5432 $(distdir)/mips/vr5500 $(distdir)/ppc/7450
$(distdir)/ppc/e300 $(distdir)/ppc/e500 $(distdir)/ppc/e500v2
$(distdir)/ppc64/970 $(distdir)/ppc64/970MP $(distdir)/ppc64/cell-be
$(distdir)/ppc64/pa6t $(distdir)/ppc64/power4 $(distdir)/ppc64/power5
$(distdir)/ppc64/power5+ $(distdir)/ppc64/power5++
$(distdir)/ppc64/power6 $(distdir)/rtc $(distdir)/x86-64/family10
$(distdir)/x86-64/hammer
+ $(mkdir_p) $(distdir)/alpha/ev4 $(distdir)/alpha/ev5
$(distdir)/alpha/ev6 $(distdir)/alpha/ev67 $(distdir)/alpha/pca56
$(distdir)/arm/11mpcore $(distdir)/arm/a8 $(distdir)/arm/a9
$(distdir)/arm/a9mpcore $(distdir)/arm/v6 $(distdir)/arm/xscale1
$(distdir)/arm/xscale2 $(distdir)/avr32 $(distdir)/i386/athlon
$(distdir)/i386/core $(distdir)/i386/core_2 $(distdir)/i386/p4
$(distdir)/i386/p4-ht $(distdir)/i386/p6_mobile $(distdir)/i386/pii
$(distdir)/i386/piii $(distdir)/i386/ppro $(distdir)/ia64/ia64
$(distdir)/ia64/itanium $(distdir)/ia64/itanium2 $(distdir)/mips/20K
$(distdir)/mips/24K $(distdir)/mips/25K $(distdir)/mips/34K
$(distdir)/mips/5K $(distdir)/mips/r10000 $(distdir)/mips/r12000
$(distdir)/mips/rm7000 $(distdir)/mips/rm9000 $(distdir)/mips/sb1
$(distdir)/mips/vr5432 $(distdir)/mips/vr5500 $(distdir)/ppc/7450
$(distdir)/ppc/e300 $(distdir)/ppc/e500 $(distdir)/ppc/e500v2
$(distdir)/ppc64/970 $(distdir)/ppc64/970MP $(distdir)/ppc64/cell-be
$(distdir)/ppc64/pa6t $(distdir)/ppc64/power4 $(distdir)/ppc64/power5
$(distdir)/ppc64/power5+ $(distdir)/ppc64/power5++
$(distdir)/ppc64/power6 $(distdir)/rtc $(distdir)/x86-64/family10
$(distdir)/x86-64/hammer
@srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \
topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \
list='$(DISTFILES)'; for file in $$list; do \
diff -NaurBb oprofile-0.9.4.dist/events/arm/11mpcore/events
oprofile-0.9.4.mod/events/arm/11mpcore/events
--- oprofile-0.9.4.dist/events/arm/11mpcore/events 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/11mpcore/events 2008-04-15
14:07:29.000000000 +0100
@@ -0,0 +1,178 @@
+# ARM/MPCORE
+
+# Event numbers are structured:
+# bits 0-7 are the actual event number, which is written into the
hardware counters
+# bits 8-11 are which CPU the event relates to
+# bit 12-13 0=CPU counter (i.e. accessed through CP15)
+# 1=SCU counter (i.e. memory-mapped)
+
+# CPU events
+
+event:0x0001 counters:0,1 um:zero minimum:500 name:CPU0_ICACHE_MISS :
ICache miss to a cacheable location
+event:0x0002 counters:0,1 um:zero minimum:500 name:CPU0_STALL_INST :
Stall because prefetch unit cannot deliver an instruction
+event:0x0003 counters:0,1 um:zero minimum:500 name:CPU0_STALL_DATA :
Stall because data dependency
+event:0x0004 counters:0,1 um:zero minimum:100 name:CPU0_uTLB_MISS_I :
Instruction uTLB miss
+event:0x0005 counters:0,1 um:zero minimum:100 name:CPU0_uTLB_MISS_D :
Data uTLB miss
+event:0x0006 counters:0,1 um:zero minimum:500 name:CPU0_BRANCH_EXEC :
Branch instruction executed
+event:0x0007 counters:0,1 um:zero minimum:500 name:CPU0_BRANCH_NOT_PRED
: Branch not predicted
+event:0x0008 counters:0,1 um:zero minimum:500 name:CPU0_BRANCH_MIS_PRED
: Branch mispredicted
+event:0x0009 counters:0,1 um:zero minimum:50000 name:CPU0_INST_EXEC :
Instruction executed
+event:0x000a counters:0,1 um:zero minimum:500 name:CPU0_FOLD_INST_EXEC
: Folded instruction executed
+event:0x000b counters:0,1 um:zero minimum:1000 name:CPU0_DCACHE_READ :
Data cache read access
+event:0x000c counters:0,1 um:zero minimum:1000
name:CPU0_DCACHE_READ_MISS : Data cache read miss
+event:0x000d counters:0,1 um:zero minimum:1000 name:CPU0_DCACHE_WRITE :
Data cache write access
+event:0x000e counters:0,1 um:zero minimum:1000
name:CPU0_DCACHE_WRITE_MISS : Data cache write miss
+event:0x000f counters:0,1 um:zero minimum:500
name:CPU0_DCACHE_LEVICTION : Data cache line evictions
+event:0x0010 counters:0,1 um:zero minimum:500
name:CPU0_SW_PCCHANGE_NOMODE : SW changes PC with no mode changed
+event:0x0011 counters:0,1 um:zero minimum:500 name:CPU0_TLB_MISS : Main
TLB miss
+event:0x0012 counters:0,1 um:zero minimum:500 name:CPU0_EXT_MEM_REQ :
External memory request
+event:0x0013 counters:0,1 um:zero minimum:500 name:CPU0_STALL_LSU_FULL
: Stall because of LSU request queue full
+event:0x0014 counters:0,1 um:zero minimum:500 name:CPU0_STR_BUF_DRAIN :
The number of times the Store buffer was drained due to LSU ordering
constraints or CP15 operations
+event:0x0015 counters:0,1 um:zero minimum:500 name:CPU0_BUF_WRI_MERG :
Buffered write merged in a store buffer slot
+event:0x0016 counters:0,1 um:zero minimum:500 name:CPU0_LSU_SAFE : LSU
is in safe mode
+
+event:0x00ff counters:7 um:zero minimum:50000 name:CPU0_CYCLES : CPU0
Cycle Counter
+
+event:0x0101 counters:8,9 um:zero minimum:500 name:CPU1_ICACHE_MISS :
ICache miss to a cacheable location
+event:0x0102 counters:8,9 um:zero minimum:500 name:CPU1_STALL_INST :
Stall because prefetch unit cannot deliver an instruction
+event:0x0103 counters:8,9 um:zero minimum:500 name:CPU1_STALL_DATA :
Stall because data dependency
+event:0x0104 counters:8,9 um:zero minimum:100 name:CPU1_uTLB_MISS_I :
Instruction uTLB miss
+event:0x0105 counters:8,9 um:zero minimum:100 name:CPU1_uTLB_MISS_D :
Data uTLB miss
+event:0x0106 counters:8,9 um:zero minimum:500 name:CPU1_BRANCH_EXEC :
Branch instruction executed
+event:0x0107 counters:8,9 um:zero minimum:500 name:CPU1_BRANCH_NOT_PRED
: Branch not predicted
+event:0x0108 counters:8,9 um:zero minimum:500 name:CPU1_BRANCH_MIS_PRED
: Branch mispredicted
+event:0x0109 counters:8,9 um:zero minimum:50000 name:CPU1_INST_EXEC :
Instruction executed
+event:0x010a counters:8,9 um:zero minimum:500 name:CPU1_FOLD_INST_EXEC
: Folded instruction executed
+event:0x010b counters:8,9 um:zero minimum:1000 name:CPU1_DCACHE_READ :
Data cache read access
+event:0x010c counters:8,9 um:zero minimum:1000
name:CPU1_DCACHE_READ_MISS : Data cache read miss
+event:0x010d counters:8,9 um:zero minimum:1000 name:CPU1_DCACHE_WRITE :
Data cache write access
+event:0x010e counters:8,9 um:zero minimum:1000
name:CPU1_DCACHE_WRITE_MISS : Data cache write miss
+event:0x010f counters:8,9 um:zero minimum:500
name:CPU1_DCACHE_LEVICTION : Data cache line evictions
+event:0x0110 counters:8,9 um:zero minimum:500
name:CPU1_SW_PCCHANGE_NOMODE : SW changes PC with no mode changed
+event:0x0111 counters:8,9 um:zero minimum:500 name:CPU1_TLB_MISS : Main
TLB miss
+event:0x0112 counters:8,9 um:zero minimum:500 name:CPU1_EXT_MEM_REQ :
External memory request
+event:0x0113 counters:8,9 um:zero minimum:500 name:CPU1_STALL_LSU_FULL
: Stall because of LSU request queue full
+event:0x0114 counters:8,9 um:zero minimum:500 name:CPU1_STR_BUF_DRAIN :
The number of times the Store buffer was drained due to LSU ordering
constraints or CP15 operations
+event:0x0115 counters:8,9 um:zero minimum:500 name:CPU1_BUF_WRI_MERG :
Buffered write merged in a store buffer slot
+event:0x0116 counters:8,9 um:zero minimum:500 name:CPU1_LSU_SAFE : LSU
is in safe mode
+
+event:0x01ff counters:15 um:zero minimum:50000 name:CPU1_CYCLES : CPU1
Cycle Counter
+
+event:0x0201 counters:16,17 um:zero minimum:500 name:CPU2_ICACHE_MISS :
ICache miss to a cacheable location
+event:0x0202 counters:16,17 um:zero minimum:500 name:CPU2_STALL_INST :
Stall because prefetch unit cannot deliver an instruction
+event:0x0203 counters:16,17 um:zero minimum:500 name:CPU2_STALL_DATA :
Stall because data dependency
+event:0x0204 counters:16,17 um:zero minimum:100 name:CPU2_uTLB_MISS_I :
Instruction uTLB miss
+event:0x0205 counters:16,17 um:zero minimum:100 name:CPU2_uTLB_MISS_D :
Data uTLB miss
+event:0x0206 counters:16,17 um:zero minimum:500 name:CPU2_BRANCH_EXEC :
Branch instruction executed
+event:0x0207 counters:16,17 um:zero minimum:500
name:CPU2_BRANCH_NOT_PRED : Branch not predicted
+event:0x0208 counters:16,17 um:zero minimum:500
name:CPU2_BRANCH_MIS_PRED : Branch mispredicted
+event:0x0209 counters:16,17 um:zero minimum:50000 name:CPU2_INST_EXEC :
Instruction executed
+event:0x020a counters:16,17 um:zero minimum:500
name:CPU2_FOLD_INST_EXEC : Folded instruction executed
+event:0x020b counters:16,17 um:zero minimum:1000 name:CPU2_DCACHE_READ
: Data cache read access
+event:0x020c counters:16,17 um:zero minimum:1000
name:CPU2_DCACHE_READ_MISS : Data cache read miss
+event:0x020d counters:16,17 um:zero minimum:1000 name:CPU2_DCACHE_WRITE
: Data cache write access
+event:0x020e counters:16,17 um:zero minimum:1000
name:CPU2_DCACHE_WRITE_MISS : Data cache write miss
+event:0x020f counters:16,17 um:zero minimum:500
name:CPU2_DCACHE_LEVICTION : Data cache line evictions
+event:0x0210 counters:16,17 um:zero minimum:500
name:CPU2_SW_PCCHANGE_NOMODE : SW changes PC with no mode changed
+event:0x0211 counters:16,17 um:zero minimum:500 name:CPU2_TLB_MISS :
Main TLB miss
+event:0x0212 counters:16,17 um:zero minimum:500 name:CPU2_EXT_MEM_REQ :
External memory request
+event:0x0213 counters:16,17 um:zero minimum:500
name:CPU2_STALL_LSU_FULL : Stall because of LSU request queue full
+event:0x0214 counters:16,17 um:zero minimum:500 name:CPU2_STR_BUF_DRAIN
: The number of times the Store buffer was drained due to LSU ordering
constraints or CP15 operations
+event:0x0215 counters:16,17 um:zero minimum:500 name:CPU2_BUF_WRI_MERG
: Buffered write merged in a store buffer slot
+event:0x0216 counters:16,17 um:zero minimum:500 name:CPU2_LSU_SAFE :
LSU is in safe mode
+
+event:0x02ff counters:23 um:zero minimum:50000 name:CPU2_CYCLES : CPU2
Cycle Counter
+
+event:0x0301 counters:24,25 um:zero minimum:500 name:CPU3_ICACHE_MISS :
ICache miss to a cacheable location
+event:0x0302 counters:24,25 um:zero minimum:500 name:CPU3_STALL_INST :
Stall because prefetch unit cannot deliver an instruction
+event:0x0303 counters:24,25 um:zero minimum:500 name:CPU3_STALL_DATA :
Stall because data dependency
+event:0x0304 counters:24,25 um:zero minimum:100 name:CPU3_uTLB_MISS_I :
Instruction uTLB miss
+event:0x0305 counters:24,25 um:zero minimum:100 name:CPU3_uTLB_MISS_D :
Data uTLB miss
+event:0x0306 counters:24,25 um:zero minimum:500 name:CPU3_BRANCH_EXEC :
Branch instruction executed
+event:0x0307 counters:24,25 um:zero minimum:500
name:CPU3_BRANCH_NOT_PRED : Branch not predicted
+event:0x0308 counters:24,25 um:zero minimum:500
name:CPU3_BRANCH_MIS_PRED : Branch mispredicted
+event:0x0309 counters:24,25 um:zero minimum:50000 name:CPU3_INST_EXEC :
Instruction executed
+event:0x030a counters:24,25 um:zero minimum:500
name:CPU3_FOLD_INST_EXEC : Folded instruction executed
+event:0x030b counters:24,25 um:zero minimum:1000 name:CPU3_DCACHE_READ
: Data cache read access
+event:0x030c counters:24,25 um:zero minimum:1000
name:CPU3_DCACHE_READ_MISS : Data cache read miss
+event:0x030d counters:24,25 um:zero minimum:1000 name:CPU3_DCACHE_WRITE
: Data cache write access
+event:0x030e counters:24,25 um:zero minimum:1000
name:CPU3_DCACHE_WRITE_MISS : Data cache write miss
+event:0x030f counters:24,25 um:zero minimum:500
name:CPU3_DCACHE_LEVICTION : Data cache line evictions
+event:0x0310 counters:24,25 um:zero minimum:500
name:CPU3_SW_PCCHANGE_NOMODE : SW changes PC with no mode changed
+event:0x0311 counters:24,25 um:zero minimum:500 name:CPU3_TLB_MISS :
Main TLB miss
+event:0x0312 counters:24,25 um:zero minimum:500 name:CPU3_EXT_MEM_REQ :
External memory request
+event:0x0313 counters:24,25 um:zero minimum:500
name:CPU3_STALL_LSU_FULL : Stall because of LSU request queue full
+event:0x0314 counters:24,25 um:zero minimum:500 name:CPU3_STR_BUF_DRAIN
: The number of times the Store buffer was drained due to LSU ordering
constraints or CP15 operations
+event:0x0315 counters:24,25 um:zero minimum:500 name:CPU3_BUF_WRI_MERG
: Buffered write merged in a store buffer slot
+event:0x0316 counters:24,25 um:zero minimum:500 name:CPU3_LSU_SAFE :
LSU is in safe mode
+
+event:0x03ff counters:31 um:zero minimum:50000 name:CPU3_CYCLES : CPU3
Cycle Counter
+
+# SCU events
+
+# SCU events related to a particular CPU.
+event:0x1001 counters:32,33 um:zero minimum:100 name:CPU0_LF_MISS :
CPU0 requested LF which misses in all other CPUs
+event:0x1102 counters:34,35 um:zero minimum:100 name:CPU1_LF_MISS :
CPU1 requested LF which misses in all other CPUs
+event:0x1203 counters:36,37 um:zero minimum:100 name:CPU2_LF_MISS :
CPU2 requested LF which misses in all other CPUs
+event:0x1304 counters:38,39 um:zero minimum:100 name:CPU3_LF_MISS :
CPU3 requested LF which misses in all other CPUs
+event:0x1005 counters:32,33 um:zero minimum:100 name:CPU0_LF_HIT : CPU0
requested LF which hits in all other CPUs
+event:0x1106 counters:34,35 um:zero minimum:100 name:CPU1_LF_HIT : CPU1
requested LF which hits in all other CPUs
+event:0x1207 counters:36,37 um:zero minimum:100 name:CPU2_LF_HIT : CPU2
requested LF which hits in all other CPUs
+event:0x1308 counters:38,39 um:zero minimum:100 name:CPU3_LF_HIT : CPU3
requested LF which hits in all other CPUs
+event:0x1009 counters:32,33 um:zero minimum:100 name:CPU0_LINE_NOPRE :
CPU0 was expected to have a line in cache but answers not present
+event:0x110a counters:34,35 um:zero minimum:100 name:CPU1_LINE_NOPRE :
CPU1 was expected to have a line in cache but answers not present
+event:0x120b counters:36,37 um:zero minimum:100 name:CPU2_LINE_NOPRE :
CPU2 was expected to have a line in cache but answers not present
+event:0x130c counters:38,39 um:zero minimum:100 name:CPU3_LINE_NOPRE :
CPU3 was expected to have a line in cache but answers not present
+
+# These events are global, i.e. they are not related to a specific CPU.
We replicate them across the CPUs because
+# each counter's interrupt is mapped to a particular CPU, and that CPU
is where oprofile will sample the pc.
+# Normally you probably want to count a global event on all the CPUs at
the same time, since you don't
+# generally know which CPU caused the event anyway.
+
+event:0x100d counters:32,33 um:zero minimum:100 name:CPU0_SCU_LM : Line
migration
+event:0x100e counters:32,33 um:zero minimum:500 name:CPU0_READ_BUSY_0 :
Master 0 read busy
+event:0x100f counters:32,33 um:zero minimum:500 name:CPU0_READ_BUSY_1 :
Master 1 read busy
+event:0x1010 counters:32,33 um:zero minimum:500 name:CPU0_WRITE_BUSY_0
: Master 0 write busy
+event:0x1011 counters:32,33 um:zero minimum:500 name:CPU0_WRITE_BUSY_1
: Master 1 write busy
+event:0x1012 counters:32,33 um:zero minimum:500 name:CPU0_READ_TRANS :
A read transfer is sent to the external memory
+event:0x1013 counters:32,33 um:zero minimum:500 name:CPU0_WRITE_TRANS :
A write transfer is sent to the external memory
+event:0x101f counters:32,33 um:zero minimum:120000 name:CPU0_CLK_SCU :
CLK cycle (counter incremented on each CLK cycle)
+
+event:0x110d counters:34,35 um:zero minimum:100 name:CPU1_SCU_LM : Line
migration
+event:0x110e counters:34,35 um:zero minimum:500 name:CPU1_READ_BUSY_0 :
Master 0 read busy
+event:0x110f counters:34,35 um:zero minimum:500 name:CPU1_READ_BUSY_1 :
Master 1 read busy
+event:0x1110 counters:34,35 um:zero minimum:500 name:CPU1_WRITE_BUSY_0
: Master 0 write busy
+event:0x1111 counters:34,35 um:zero minimum:500 name:CPU1_WRITE_BUSY_1
: Master 1 write busy
+event:0x1112 counters:34,35 um:zero minimum:500 name:CPU1_READ_TRANS :
A read transfer is sent to the external memory
+event:0x1113 counters:34,35 um:zero minimum:500 name:CPU1_WRITE_TRANS :
A write transfer is sent to the external memory
+event:0x111f counters:34,35 um:zero minimum:120000 name:CPU1_CLK_SCU :
CLK cycle (counter incremented on each CLK cycle)
+
+event:0x120d counters:36,37 um:zero minimum:100 name:CPU2_SCU_LM : Line
migration
+event:0x120e counters:36,37 um:zero minimum:500 name:CPU2_READ_BUSY_0 :
Master 0 read busy
+event:0x120f counters:36,37 um:zero minimum:500 name:CPU2_READ_BUSY_1 :
Master 1 read busy
+event:0x1210 counters:36,37 um:zero minimum:500 name:CPU2_WRITE_BUSY_0
: Master 0 write busy
+event:0x1211 counters:36,37 um:zero minimum:500 name:CPU2_WRITE_BUSY_1
: Master 1 write busy
+event:0x1212 counters:36,37 um:zero minimum:500 name:CPU2_READ_TRANS :
A read transfer is sent to the external memory
+event:0x1213 counters:36,37 um:zero minimum:500 name:CPU2_WRITE_TRANS :
A write transfer is sent to the external memory
+event:0x121f counters:36,37 um:zero minimum:120000 name:CPU2_CLK_SCU :
CLK cycle (counter incremented on each CLK cycle)
+
+event:0x130d counters:38,39 um:zero minimum:100 name:CPU3_SCU_LM : Line
migration
+event:0x130e counters:38,39 um:zero minimum:500 name:CPU3_READ_BUSY_0 :
Master 0 read busy
+event:0x130f counters:38,39 um:zero minimum:500 name:CPU3_READ_BUSY_1 :
Master 1 read busy
+event:0x1310 counters:38,39 um:zero minimum:500 name:CPU3_WRITE_BUSY_0
: Master 0 write busy
+event:0x1311 counters:38,39 um:zero minimum:500 name:CPU3_WRITE_BUSY_1
: Master 1 write busy
+event:0x1312 counters:38,39 um:zero minimum:500 name:CPU3_READ_TRANS :
A read transfer is sent to the external memory
+event:0x1313 counters:38,39 um:zero minimum:500 name:CPU3_WRITE_TRANS :
A write transfer is sent to the external memory
+event:0x131f counters:38,39 um:zero minimum:120000 name:CPU3_CLK_SCU :
CLK cycle (counter incremented on each CLK cycle)
+
+# These are the L220 (level 2 cache controller) events
+event:0x2001 counters:40,41 um:zero minimum:100 name:L220_CO : Eviction
(CastOUT) of a line or a half line from the L2 cache
+event:0x2003 counters:40,41 um:zero minimum:100 name:L220_DRHIT : Data
read hit in the L2 cache
+event:0x2004 counters:40,41 um:zero minimum:100 name:L220_DRREQ : Data
read lookup to the L2 cache
+event:0x2002 counters:40,41 um:zero minimum:100 name:L220_DWHIT : Data
write hit in the L2 cache
+event:0x2005 counters:40,41 um:zero minimum:100 name:L220_DWREQ : Data
write lookup to the L2 cache
+event:0x2006 counters:40,41 um:zero minimum:100 name:L220_DWTREQ : Data
write lookup to the L2 cache with Write-Through attribute
+event:0x2007 counters:40,41 um:zero minimum:100 name:L220_IRHIT :
Instruction read hit in the L2 cache
+event:0x2008 counters:40,41 um:zero minimum:100 name:L220_IRREQ :
Instruction read lookup to the L2 cache
+event:0x2009 counters:40,41 um:zero minimum:100 name:L220_WA :
Allocation into the L2 cache caused by a write (with Write-Allocate
attribute) miss
+
diff -NaurBb oprofile-0.9.4.dist/events/arm/11mpcore/unit_masks
oprofile-0.9.4.mod/events/arm/11mpcore/unit_masks
--- oprofile-0.9.4.dist/events/arm/11mpcore/unit_masks 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/11mpcore/unit_masks 2008-12-01
19:00:58.000000000 +0000
@@ -0,0 +1,4 @@
+# ARM/MPCORE possible unit masks
+#
+name:zero type:mandatory default:0xff
+ 0xff No unit mask
diff -NaurBb oprofile-0.9.4.dist/events/arm/a8/events
oprofile-0.9.4.mod/events/arm/a8/events
--- oprofile-0.9.4.dist/events/arm/a8/events 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/a8/events 2009-03-09
12:37:17.000000000 +0000
@@ -0,0 +1,29 @@
+# arm/a8
+
+# Event numbers are structured:
+# bits 0-7 are the actual event number, which is written into the
hardware counters
+# bits 8-11 are which CPU the event relates to
+# bit 12-13 0=CPU counter (accessed through CP15)
+# 1=SCU counter (memory-mapped, events from Snoop
Control Unit)
+# 2=L2x0 counter (memory-mapped, events from L2 cache
controller)
+
+# CPU events
+
+event:0x0001 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_ICACHE_MISS : Instruction fetch that misses in L1 cache
+event:0x0002 counters:0,1,2,3,4,5 um:zero minimum:100
name:CPU0_ITLB_MISS : Instruction fetch that misses in L1 TLB
+event:0x0003 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_LINEFILL : Read/Write operation that causes an L1 cache
linefill
+event:0x0004 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_ACCESS : Read/Write operation that causes an L1 cache
access
+event:0x0005 counters:0,1,2,3,4,5 um:zero minimum:100
name:CPU0_DTLB_MISS : Read/Write operation that misses in L1 TLB
+event:0x0006 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_READ :
Read instruction executed
+event:0x0007 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_WRITE :
Write instruction executed
+event:0x0068 counters:0,1,2,3,4,5 um:zero minimum:5000
name:CPU0_INSTRUCTION : Instruction executed
+event:0x0009 counters:0,1,2,3,4,5 um:zero minimum:50
name:CPU0_EXCEPTION_TAKEN : Exception taken, except floating point
+event:0x000a counters:0,1,2,3,4,5 um:zero minimum:50
name:CPU0_EXCEPTION_RETURN : Exception return executed
+event:0x000b counters:0,1,2,3,4,5 um:zero minimum:1
name:CPU0_CIDR_WRITE : Context ID Register written to
+event:0x000c counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_SW_PC_CHANGE : Software change of PC, except by an exception
+event:0x000d counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_IMMEDIATE_BRANCH : Immediate branch executed
+event:0x000e counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_PROCEDURE_RETURN : Predictable function return
+event:0x000f counters:0,1,2,3,4,5 um:zero minimum:1 name:CPU0_UNALIGNED
: Instruction that caused an unaligned access executed
+event:0x0010 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_BRANCH_NOT_PRED : Branch mispredicted/not predicted
+event:0x0012 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_BRANCH
: Branch executed (that could be predicted)
+event:0x00ff counters:7 um:zero minimum:50000 name:CPU0_CYCLES : Cycle
Counter
diff -NaurBb oprofile-0.9.4.dist/events/arm/a8/unit_masks
oprofile-0.9.4.mod/events/arm/a8/unit_masks
--- oprofile-0.9.4.dist/events/arm/a8/unit_masks 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/a8/unit_masks 2008-12-08
10:37:53.000000000 +0000
@@ -0,0 +1,4 @@
+# MPCore possible unit masks
+#
+name:zero type:mandatory default:0x00
+ 0x00 No unit mask
diff -NaurBb oprofile-0.9.4.dist/events/arm/a9/events
oprofile-0.9.4.mod/events/arm/a9/events
--- oprofile-0.9.4.dist/events/arm/a9/events 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/a9/events 2008-04-21
09:14:47.000000000 +0100
@@ -0,0 +1,56 @@
+# arm/a9mpcore
+
+# Event numbers are structured:
+# bits 0-7 are the actual event number, which is written into the
hardware counters
+# bits 8-11 are which CPU the event relates to
+# bit 12-13 0=CPU counter (accessed through CP15)
+# 1=SCU counter (memory-mapped, events from Snoop
Control Unit)
+# 2=L2x0 counter (memory-mapped, events from L2 cache
controller)
+
+# CPU events
+
+event:0x0001 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_ICACHE_MISS : Instruction fetch that misses in L1 cache
+event:0x0002 counters:0,1,2,3,4,5 um:zero minimum:100
name:CPU0_ITLB_MISS : Instruction fetch that misses in L1 TLB
+event:0x0003 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_LINEFILL : Read/Write operation that causes an L1 cache
linefill
+event:0x0004 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_ACCESS : Read/Write operation that causes an L1 cache
access
+event:0x0005 counters:0,1,2,3,4,5 um:zero minimum:100
name:CPU0_DTLB_MISS : Read/Write operation that misses in L1 TLB
+event:0x0006 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_READ :
Read instruction executed
+event:0x0007 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_WRITE :
Write instruction executed
+event:0x0068 counters:0,1,2,3,4,5 um:zero minimum:5000
name:CPU0_INSTRUCTION : Instruction executed
+event:0x0009 counters:0,1,2,3,4,5 um:zero minimum:50
name:CPU0_EXCEPTION_TAKEN : Exception taken, except floating point
+event:0x000a counters:0,1,2,3,4,5 um:zero minimum:50
name:CPU0_EXCEPTION_RETURN : Exception return executed
+event:0x000b counters:0,1,2,3,4,5 um:zero minimum:1
name:CPU0_CIDR_WRITE : Context ID Register written to
+event:0x000c counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_SW_PC_CHANGE : Software change of PC, except by an exception
+event:0x000d counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_IMMEDIATE_BRANCH : Immediate branch executed
+event:0x006e counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_PROCEDURE_RETURN : Predictable function return
+event:0x000f counters:0,1,2,3,4,5 um:zero minimum:1 name:CPU0_UNALIGNED
: Instruction that caused an unaligned access executed
+event:0x0010 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_BRANCH_NOT_PRED : Branch mispredicted/not predicted
+event:0x0012 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_BRANCH
: Branch executed (that could be predicted)
+# Jazelle specific events
+event:0x0040 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_BYTECODE : Java bytecode executed
+event:0x0041 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_SW_BYTECODE : Java bytecode executed in software
+event:0x0042 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_JAZELLE_BB : Jazelle backward Branch executed
+# SCU specific events (on Cortex A9, SCU events are counted by the CPU
counters)
+event:0x0050 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_COHERENT_LF_MISS : coherent linefill missed in all other CPUs,
and was sent to external memory
+event:0x0051 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_COHERENT_LF_HIT : coherent linefill hit in another CPU's
cache, and was fetched from there
+# Additional events
+event:0x0060 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_ICACHE_STALL : Instruction cache dependent stalls
+event:0x0061 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_STALL : Data cache dependent stalls
+event:0x0062 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_TLB_STALL : TLB miss dependent stalls
+event:0x0063 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_STREX_SUCCESS : STREX succeeded
+event:0x0064 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_STREX_FAIL : STREX failed
+event:0x0065 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_EVICTION : Data cache eviction
+event:0x00ff counters:7 um:zero minimum:50000 name:CPU0_CYCLES : CPU0
Cycle Counter
+
+
+# These are the L220 (level 2 cache controller) events
+event:0x2001 counters:40,41 um:zero minimum:100 name:L220_CO : Eviction
(CastOUT) of a line or a half line from the L2 cache
+event:0x2003 counters:40,41 um:zero minimum:100 name:L220_DRHIT : Data
read hit in the L2 cache
+event:0x2004 counters:40,41 um:zero minimum:100 name:L220_DRREQ : Data
read lookup to the L2 cache
+event:0x2002 counters:40,41 um:zero minimum:100 name:L220_DWHIT : Data
write hit in the L2 cache
+event:0x2005 counters:40,41 um:zero minimum:100 name:L220_DWREQ : Data
write lookup to the L2 cache
+event:0x2006 counters:40,41 um:zero minimum:100 name:L220_DWTREQ : Data
write lookup to the L2 cache with Write-Through attribute
+event:0x2007 counters:40,41 um:zero minimum:100 name:L220_IRHIT :
Instruction read hit in the L2 cache
+event:0x2008 counters:40,41 um:zero minimum:100 name:L220_IRREQ :
Instruction read lookup to the L2 cache
+event:0x2009 counters:40,41 um:zero minimum:100 name:L220_WA :
Allocation into the L2 cache caused by a write (with Write-Allocate
attribute) miss
+
diff -NaurBb oprofile-0.9.4.dist/events/arm/a9/unit_masks
oprofile-0.9.4.mod/events/arm/a9/unit_masks
--- oprofile-0.9.4.dist/events/arm/a9/unit_masks 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/a9/unit_masks 2008-03-13
16:00:53.000000000 +0000
@@ -0,0 +1,4 @@
+# MPCore possible unit masks
+#
+name:zero type:mandatory default:0x00
+ 0x00 No unit mask
diff -NaurBb oprofile-0.9.4.dist/events/arm/a9mpcore/events
oprofile-0.9.4.mod/events/arm/a9mpcore/events
--- oprofile-0.9.4.dist/events/arm/a9mpcore/events 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/a9mpcore/events 2008-04-21
09:17:14.000000000 +0100
@@ -0,0 +1,155 @@
+# arm/a9mpcore
+
+# Event numbers are structured:
+# bits 0-7 are the actual event number, which is written into the
hardware counters
+# bits 8-11 are which CPU the event relates to
+# bit 12-13 0=CPU counter (accessed through CP15)
+# 1=SCU counter (memory-mapped, events from Snoop
Control Unit)
+# 2=L2x0 counter (memory-mapped, events from L2 cache
controller)
+
+# CPU events
+
+event:0x0001 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_ICACHE_MISS : Instruction fetch that misses in L1 cache
+event:0x0002 counters:0,1,2,3,4,5 um:zero minimum:100
name:CPU0_ITLB_MISS : Instruction fetch that misses in L1 TLB
+event:0x0003 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_LINEFILL : Read/Write operation that causes an L1 cache
linefill
+event:0x0004 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_ACCESS : Read/Write operation that causes an L1 cache
access
+event:0x0005 counters:0,1,2,3,4,5 um:zero minimum:100
name:CPU0_DTLB_MISS : Read/Write operation that misses in L1 TLB
+event:0x0006 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_READ :
Read instruction executed
+event:0x0007 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_WRITE :
Write instruction executed
+event:0x0068 counters:0,1,2,3,4,5 um:zero minimum:5000
name:CPU0_INSTRUCTION : Instruction executed
+event:0x0009 counters:0,1,2,3,4,5 um:zero minimum:50
name:CPU0_EXCEPTION_TAKEN : Exception taken, except floating point
+event:0x000a counters:0,1,2,3,4,5 um:zero minimum:50
name:CPU0_EXCEPTION_RETURN : Exception return executed
+event:0x000b counters:0,1,2,3,4,5 um:zero minimum:1
name:CPU0_CIDR_WRITE : Context ID Register written to
+event:0x000c counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_SW_PC_CHANGE : Software change of PC, except by an exception
+event:0x000d counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_IMMEDIATE_BRANCH : Immediate branch executed
+event:0x006e counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_PROCEDURE_RETURN : Predictable function return
+event:0x000f counters:0,1,2,3,4,5 um:zero minimum:1 name:CPU0_UNALIGNED
: Instruction that caused an unaligned access executed
+event:0x0010 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_BRANCH_NOT_PRED : Branch mispredicted/not predicted
+event:0x0012 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU0_BRANCH
: Branch executed (that could be predicted)
+# Jazelle specific events
+event:0x0040 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_BYTECODE : Java bytecode executed
+event:0x0041 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_SW_BYTECODE : Java bytecode executed in software
+event:0x0042 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_JAZELLE_BB : Jazelle backward Branch executed
+# SCU specific events (on Cortex A9, SCU events are counted by the CPU
counters)
+event:0x0050 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_COHERENT_LF_MISS : coherent linefill missed in all other CPUs,
and was sent to external memory
+event:0x0051 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_COHERENT_LF_HIT : coherent linefill hit in another CPU's
cache, and was fetched from there
+# Additional events
+event:0x0060 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_ICACHE_STALL : Instruction cache dependent stalls
+event:0x0061 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_STALL : Data cache dependent stalls
+event:0x0062 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_TLB_STALL : TLB miss dependent stalls
+event:0x0063 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_STREX_SUCCESS : STREX succeeded
+event:0x0064 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_STREX_FAIL : STREX failed
+event:0x0065 counters:0,1,2,3,4,5 um:zero minimum:500
name:CPU0_DCACHE_EVICTION : Data cache eviction
+event:0x00ff counters:7 um:zero minimum:50000 name:CPU0_CYCLES : CPU0
Cycle Counter
+
+event:0x0101 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_ICACHE_MISS : Instruction fetch that misses in L1 cache
+event:0x0102 counters:8,9,10,11,12,13 um:zero minimum:100
name:CPU1_ITLB_MISS : Instruction fetch that misses in L1 TLB
+event:0x0103 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_DCACHE_LINEFILL : Read/Write operation that causes an L1 cache
linefill
+event:0x0104 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_DCACHE_ACCESS : Read/Write operation that causes an L1 cache
access
+event:0x0105 counters:8,9,10,11,12,13 um:zero minimum:100
name:CPU1_DTLB_MISS : Read/Write operation that misses in L1 TLB
+event:0x0106 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_READ : Read instruction executed
+event:0x0107 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_WRITE : Write instruction executed
+event:0x0168 counters:8,9,10,11,12,13 um:zero minimum:5000
name:CPU1_INSTRUCTION : Instruction executed
+event:0x0109 counters:8,9,10,11,12,13 um:zero minimum:50
name:CPU1_EXCEPTION_TAKEN : Exception taken, except floating point
+event:0x010a counters:8,9,10,11,12,13 um:zero minimum:50
name:CPU1_EXCEPTION_RETURN : Exception return executed
+event:0x010b counters:8,9,10,11,12,13 um:zero minimum:1
name:CPU1_CIDR_WRITE : Context ID Register written to
+event:0x010c counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_SW_PC_CHANGE : Software change of PC, except by an exception
+event:0x010d counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_IMMEDIATE_BRANCH : Immediate branch executed
+event:0x016e counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_PROCEDURE_RETURN : Predictable function return
+event:0x010f counters:8,9,10,11,12,13 um:zero minimum:1
name:CPU1_UNALIGNED : Instruction that caused an unaligned access
executed
+event:0x0110 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_BRANCH_NOT_PRED : Branch mispredicted/not predicted
+event:0x0112 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_BRANCH : Branch executed (that could be predicted)
+# Jazelle specific events
+event:0x0140 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_BYTECODE : Java bytecode executed
+event:0x0141 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_SW_BYTECODE : Java bytecode executed in software
+event:0x0142 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_JAZELLE_BB : Jazelle backward Branch executed
+# SCU specific events (on Cortex A9, SCU events are counted by the CPU
counters)
+event:0x0150 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_COHERENT_LF_MISS : coherent linefill missed in all other CPUs,
and was sent to external memory
+event:0x0151 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_COHERENT_LF_HIT : coherent linefill hit in another CPU's
cache, and was fetched from there
+# Additional events
+event:0x0160 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_ICACHE_STALL : Instruction cache dependent stalls
+event:0x0161 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_DCACHE_STALL : Data cache dependent stalls
+event:0x0162 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_TLB_STALL : TLB miss dependent stalls
+event:0x0163 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_STREX_SUCCESS : STREX succeeded
+event:0x0164 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_STREX_FAIL : STREX failed
+event:0x0165 counters:8,9,10,11,12,13 um:zero minimum:500
name:CPU1_DCACHE_EVICTION : Data cache eviction
+event:0x01ff counters:15 um:zero minimum:50000 name:CPU1_CYCLES : CPU1
Cycle Counter
+
+event:0x0201 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_ICACHE_MISS : Instruction fetch that misses in L1 cache
+event:0x0202 counters:16,17,18,19,20,21 um:zero minimum:100
name:CPU2_ITLB_MISS : Instruction fetch that misses in L1 TLB
+event:0x0203 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_DCACHE_LINEFILL : Read/Write operation that causes an L1 cache
linefill
+event:0x0204 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_DCACHE_ACCESS : Read/Write operation that causes an L1 cache
access
+event:0x0205 counters:16,17,18,19,20,21 um:zero minimum:100
name:CPU2_DTLB_MISS : Read/Write operation that misses in L1 TLB
+event:0x0206 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_READ : Read instruction executed
+event:0x0207 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_WRITE : Write instruction executed
+event:0x0268 counters:16,17,18,19,20,21 um:zero minimum:5000
name:CPU2_INSTRUCTION : Instruction executed
+event:0x0209 counters:16,17,18,19,20,21 um:zero minimum:50
name:CPU2_EXCEPTION_TAKEN : Exception taken, except floating point
+event:0x020a counters:16,17,18,19,20,21 um:zero minimum:50
name:CPU2_EXCEPTION_RETURN : Exception return executed
+event:0x020b counters:16,17,18,19,20,21 um:zero minimum:1
name:CPU2_CIDR_WRITE : Context ID Register written to
+event:0x020c counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_SW_PC_CHANGE : Software change of PC, except by an exception
+event:0x020d counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_IMMEDIATE_BRANCH : Immediate branch executed
+event:0x026e counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_PROCEDURE_RETURN : Predictable function return
+event:0x020f counters:16,17,18,19,20,21 um:zero minimum:1
name:CPU2_UNALIGNED : Instruction that caused an unaligned access
executed
+event:0x0210 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_BRANCH_NOT_PRED : Branch mispredicted/not predicted
+event:0x0212 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_BRANCH : Branch executed (that could be predicted)
+# Jazelle specific events
+event:0x0240 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_BYTECODE : Java bytecode executed
+event:0x0241 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_SW_BYTECODE : Java bytecode executed in software
+event:0x0242 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_JAZELLE_BB : Jazelle backward Branch executed
+# SCU specific events (on Cortex A9, SCU events are counted by the CPU
counters)
+event:0x0250 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_COHERENT_LF_MISS : coherent linefill missed in all other CPUs,
and was sent to external memory
+event:0x0251 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_COHERENT_LF_HIT : coherent linefill hit in another CPU's
cache, and was fetched from there
+# Additional events
+event:0x0260 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_ICACHE_STALL : Instruction cache dependent stalls
+event:0x0261 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_DCACHE_STALL : Data cache dependent stalls
+event:0x0262 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_TLB_STALL : TLB miss dependent stalls
+event:0x0263 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_STREX_SUCCESS : STREX succeeded
+event:0x0264 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_STREX_FAIL : STREX failed
+event:0x0265 counters:16,17,18,19,20,21 um:zero minimum:500
name:CPU2_DCACHE_EVICTION : Data cache eviction
+event:0x02ff counters:23 um:zero minimum:50000 name:CPU2_CYCLES : CPU2
Cycle Counter
+
+event:0x0301 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_ICACHE_MISS : Instruction fetch that misses in L1 cache
+event:0x0302 counters:24,25,26,27,28,29 um:zero minimum:100
name:CPU3_ITLB_MISS : Instruction fetch that misses in L1 TLB
+event:0x0303 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_DCACHE_LINEFILL : Read/Write operation that causes an L1 cache
linefill
+event:0x0304 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_DCACHE_ACCESS : Read/Write operation that causes an L1 cache
access
+event:0x0305 counters:24,25,26,27,28,29 um:zero minimum:100
name:CPU3_DTLB_MISS : Read/Write operation that misses in L1 TLB
+event:0x0306 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_READ : Read instruction executed
+event:0x0307 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_WRITE : Write instruction executed
+event:0x0368 counters:24,25,26,27,28,29 um:zero minimum:5000
name:CPU3_INSTRUCTION : Instruction executed
+event:0x0309 counters:24,25,26,27,28,29 um:zero minimum:50
name:CPU3_EXCEPTION_TAKEN : Exception taken, except floating point
+event:0x030a counters:24,25,26,27,28,29 um:zero minimum:50
name:CPU3_EXCEPTION_RETURN : Exception return executed
+event:0x030b counters:24,25,26,27,28,29 um:zero minimum:1
name:CPU3_CIDR_WRITE : Context ID Register written to
+event:0x030c counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_SW_PC_CHANGE : Software change of PC, except by an exception
+event:0x030d counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_IMMEDIATE_BRANCH : Immediate branch executed
+event:0x036e counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_PROCEDURE_RETURN : Predictable function return
+event:0x030f counters:24,25,26,27,28,29 um:zero minimum:1
name:CPU3_UNALIGNED : Instruction that caused an unaligned access
executed
+event:0x0310 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_BRANCH_NOT_PRED : Branch mispredicted/not predicted
+event:0x0312 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_BRANCH : Branch executed (that could be predicted)
+# Jazelle specific events
+event:0x0340 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_BYTECODE : Java bytecode executed
+event:0x0341 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_SW_BYTECODE : Java bytecode executed in software
+event:0x0342 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_JAZELLE_BB : Jazelle backward Branch executed
+# SCU specific events (on Cortex A9, SCU events are counted by the CPU
counters)
+event:0x0350 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_COHERENT_LF_MISS : coherent linefill missed in all other CPUs,
and was sent to external memory
+event:0x0351 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_COHERENT_LF_HIT : coherent linefill hit in another CPU's
cache, and was fetched from there
+# Additional events
+event:0x0360 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_ICACHE_STALL : Instruction cache dependent stalls
+event:0x0361 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_DCACHE_STALL : Data cache dependent stalls
+event:0x0362 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_TLB_STALL : TLB miss dependent stalls
+event:0x0363 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_STREX_SUCCESS : STREX succeeded
+event:0x0364 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_STREX_FAIL : STREX failed
+event:0x0365 counters:24,25,26,27,28,29 um:zero minimum:500
name:CPU3_DCACHE_EVICTION : Data cache eviction
+event:0x03ff counters:31 um:zero minimum:50000 name:CPU3_CYCLES : CPU3
cycle Counter
+
+
+# These are the L220 (level 2 cache controller) events
+event:0x2001 counters:40,41 um:zero minimum:100 name:L220_CO : Eviction
(CastOUT) of a line or a half line from the L2 cache
+event:0x2003 counters:40,41 um:zero minimum:100 name:L220_DRHIT : Data
read hit in the L2 cache
+event:0x2004 counters:40,41 um:zero minimum:100 name:L220_DRREQ : Data
read lookup to the L2 cache
+event:0x2002 counters:40,41 um:zero minimum:100 name:L220_DWHIT : Data
write hit in the L2 cache
+event:0x2005 counters:40,41 um:zero minimum:100 name:L220_DWREQ : Data
write lookup to the L2 cache
+event:0x2006 counters:40,41 um:zero minimum:100 name:L220_DWTREQ : Data
write lookup to the L2 cache with Write-Through attribute
+event:0x2007 counters:40,41 um:zero minimum:100 name:L220_IRHIT :
Instruction read hit in the L2 cache
+event:0x2008 counters:40,41 um:zero minimum:100 name:L220_IRREQ :
Instruction read lookup to the L2 cache
+event:0x2009 counters:40,41 um:zero minimum:100 name:L220_WA :
Allocation into the L2 cache caused by a write (with Write-Allocate
attribute) miss
+
diff -NaurBb oprofile-0.9.4.dist/events/arm/a9mpcore/unit_masks
oprofile-0.9.4.mod/events/arm/a9mpcore/unit_masks
--- oprofile-0.9.4.dist/events/arm/a9mpcore/unit_masks 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/a9mpcore/unit_masks 2008-01-17
17:52:35.000000000 +0000
@@ -0,0 +1,4 @@
+# MPCore possible unit masks
+#
+name:zero type:mandatory default:0x00
+ 0x00 No unit mask
diff -NaurBb oprofile-0.9.4.dist/events/arm/armv6/events
oprofile-0.9.4.mod/events/arm/armv6/events
--- oprofile-0.9.4.dist/events/arm/armv6/events 2007-11-05
16:37:29.000000000 +0000
+++ oprofile-0.9.4.mod/events/arm/armv6/events 1970-01-01
01:00:00.000000000 +0100
@@ -1,23 +0,0 @@
-# ARM V6 events
-#
-event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS :
number of instruction fetch misses
-event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL :
cycles instruction fetch pipe is stalled
-event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL :
cycles stall occurs for due to data dependency
-event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of
Instruction MicroTLB misses
-event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of
Data MicroTLB misses
-event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED :
branch instruction executed w/ or w/o program flow change
-event:0x06 counters:0,1 um:zero minimum:500 name:BR_INST_MISS_PRED :
branch mispredicted
-event:0x07 counters:0,1 um:zero minimum:500 name:INSN_EXECUTED :
instructions executed
-event:0x09 counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS : data
cache access, cacheable locations
-event:0x0a counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS_ALL :
data cache access, all locations
-event:0x0b counters:0,1 um:zero minimum:500 name:DCACHE_MISS : data
cache miss
-event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache
writeback, 1 event for every half cacheline
-event:0x0d counters:0,1 um:zero minimum:500 name:PC_CHANGE : number of
times the program counter was changed without a mode switch
-event:0x0f counters:0,1 um:zero minimum:500 name:TLB_MISS : Main TLB
miss
-event:0x10 counters:0,1 um:zero minimum:500 name:EXP_EXTERNAL : Explict
external data access
-event:0x11 counters:0,1 um:zero minimum:500 name:LSU_STALL : cycles
stalled because Load Store request queque is full
-event:0x12 counters:0,1 um:zero minimum:500 name:WRITE_DRAIN : Times
write buffer was drained
-event:0x20 counters:0,1 um:zero minimum:500 name:ETMEXTOUT0 : nuber of
cycles ETMEXTOUT[0] signal was asserted
-event:0x21 counters:0,1 um:zero minimum:500 name:ETMEXTOUT1 : nuber of
cycles ETMEXTOUT[1] signal was asserted
-event:0x22 counters:0,1 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber
of cycles both ETMEXTOUT [0] and [1] were asserted * 2
-event:0xff counters:0,1,2 um:zero minimum:500 name:CPU_CYCLES : clock
cycles counter
diff -NaurBb oprofile-0.9.4.dist/events/arm/armv6/unit_masks
oprofile-0.9.4.mod/events/arm/armv6/unit_masks
--- oprofile-0.9.4.dist/events/arm/armv6/unit_masks 2007-05-24
18:08:35.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/armv6/unit_masks 1970-01-01
01:00:00.000000000 +0100
@@ -1,4 +0,0 @@
-# ARM V6 PMU possible unit masks
-#
-name:zero type:mandatory default:0x00
- 0x00 No unit mask
diff -NaurBb oprofile-0.9.4.dist/events/arm/mpcore/events
oprofile-0.9.4.mod/events/arm/mpcore/events
--- oprofile-0.9.4.dist/events/arm/mpcore/events 2007-05-23
15:02:34.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/mpcore/events 1970-01-01
01:00:00.000000000 +0100
@@ -1,28 +0,0 @@
-# MPCore events
-#
-event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS :
number of instruction fetch misses
-event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL :
cycles instruction fetch pipe is stalled
-event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL :
cycles stall occurs for due to data dependency
-event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of
ITLB misses
-event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of
DTLB misses
-event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED :
branch instruction executed w/ or w/o program flow change
-event:0x06 counters:0,1 um:zero minimum:500 name:BR_INST_NOT_PRED :
branch not predicted
-event:0x07 counters:0,1 um:zero minimum:500 name:BR_INST_MISPRED :
branch mispredicted
-event:0x08 counters:0,1 um:zero minimum:500 name:INSN_EXECUTED :
instruction executed
-event:0x09 counters:0,1 um:zero minimum:500 name:INSN_FOLD_EXECUTED :
folded instruction executed
-event:0x0a counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS : data
cache read access
-event:0x0b counters:0,1 um:zero minimum:500 name:DCACHE_MISS : data
cache miss
-event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WA : data cache
write access
-event:0x0d counters:0,1 um:zero minimum:500 name:DCACHE_WM : data cache
write miss
-event:0x0e counters:0,1 um:zero minimum:500 name:DCACHE_LINE_EV : data
cache line eviction
-event:0x0f counters:0,1 um:zero minimum:500 name:SOFT_PC_CHANGE :
software changed PC without mode change
-event:0x10 counters:0,1 um:zero minimum:500 name:TLB_MISS : main TLB
miss
-event:0x11 counters:0,1 um:zero minimum:500 name:MEM_REQUEST : external
memory request (Cache request, write back)
-event:0x12 counters:0,1 um:zero minimum:500 name:LS_QUEUE_FULL : stall
because load store unit queue being full
-event:0x13 counters:0,1 um:zero minimum:500 name:LS_QUEUE_DRAINED :
number of times store buffer drained
-event:0x14 counters:0,1 um:zero minimum:500 name:LS_QUEUE_WMERGE :
buffered write merged into a store buffer slot
-event:0x15 counters:0,1 um:zero minimum:500 name:LS_SAFE_MODE : LSU in
safe mode
-event:0xff counters:0,1 um:zero minimum:500 name:CPU_CYCLES : clock
cycles counter
-
-#see ARM11 MPCore Techical Reference Manual rev. r1p0, page 3-70
-
diff -NaurBb oprofile-0.9.4.dist/events/arm/mpcore/unit_masks
oprofile-0.9.4.mod/events/arm/mpcore/unit_masks
--- oprofile-0.9.4.dist/events/arm/mpcore/unit_masks 2007-05-23
15:02:34.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/mpcore/unit_masks 1970-01-01
01:00:00.000000000 +0100
@@ -1,4 +0,0 @@
-# MPCore possible unit masks
-#
-name:zero type:mandatory default:0x00
- 0x00 No unit mask
diff -NaurBb oprofile-0.9.4.dist/events/arm/v6/events
oprofile-0.9.4.mod/events/arm/v6/events
--- oprofile-0.9.4.dist/events/arm/v6/events 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/v6/events 2007-11-05
16:37:29.000000000 +0000
@@ -0,0 +1,23 @@
+# ARM V6 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS :
number of instruction fetch misses
+event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL :
cycles instruction fetch pipe is stalled
+event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL :
cycles stall occurs for due to data dependency
+event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of
Instruction MicroTLB misses
+event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of
Data MicroTLB misses
+event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED :
branch instruction executed w/ or w/o program flow change
+event:0x06 counters:0,1 um:zero minimum:500 name:BR_INST_MISS_PRED :
branch mispredicted
+event:0x07 counters:0,1 um:zero minimum:500 name:INSN_EXECUTED :
instructions executed
+event:0x09 counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS : data
cache access, cacheable locations
+event:0x0a counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS_ALL :
data cache access, all locations
+event:0x0b counters:0,1 um:zero minimum:500 name:DCACHE_MISS : data
cache miss
+event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache
writeback, 1 event for every half cacheline
+event:0x0d counters:0,1 um:zero minimum:500 name:PC_CHANGE : number of
times the program counter was changed without a mode switch
+event:0x0f counters:0,1 um:zero minimum:500 name:TLB_MISS : Main TLB
miss
+event:0x10 counters:0,1 um:zero minimum:500 name:EXP_EXTERNAL : Explict
external data access
+event:0x11 counters:0,1 um:zero minimum:500 name:LSU_STALL : cycles
stalled because Load Store request queque is full
+event:0x12 counters:0,1 um:zero minimum:500 name:WRITE_DRAIN : Times
write buffer was drained
+event:0x20 counters:0,1 um:zero minimum:500 name:ETMEXTOUT0 : nuber of
cycles ETMEXTOUT[0] signal was asserted
+event:0x21 counters:0,1 um:zero minimum:500 name:ETMEXTOUT1 : nuber of
cycles ETMEXTOUT[1] signal was asserted
+event:0x22 counters:0,1 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber
of cycles both ETMEXTOUT [0] and [1] were asserted * 2
+event:0xff counters:0,1,2 um:zero minimum:500 name:CPU_CYCLES : clock
cycles counter
diff -NaurBb oprofile-0.9.4.dist/events/arm/v6/unit_masks
oprofile-0.9.4.mod/events/arm/v6/unit_masks
--- oprofile-0.9.4.dist/events/arm/v6/unit_masks 1970-01-01
01:00:00.000000000 +0100
+++ oprofile-0.9.4.mod/events/arm/v6/unit_masks 2007-05-24
18:08:35.000000000 +0100
@@ -0,0 +1,4 @@
+# ARM V6 PMU possible unit masks
+#
+name:zero type:mandatory default:0x00
+ 0x00 No unit mask
diff -NaurBb oprofile-0.9.4.dist/gui/oprof_start.h
oprofile-0.9.4.mod/gui/oprof_start.h
--- oprofile-0.9.4.dist/gui/oprof_start.h 2005-08-14
12:17:35.000000000 +0100
+++ oprofile-0.9.4.mod/gui/oprof_start.h 2009-01-08
12:04:17.000000000 +0000
@@ -30,7 +30,7 @@
op_event_descr();
/// bit mask of allowed counters
- uint counter_mask;
+ u64 counter_mask;
/// hardware event number
u32 val;
/// unit mask values if applicable
diff -NaurBb oprofile-0.9.4.dist/libop/op_alloc_counter.c
oprofile-0.9.4.mod/libop/op_alloc_counter.c
--- oprofile-0.9.4.dist/libop/op_alloc_counter.c 2008-07-18
00:00:52.000000000 +0100
+++ oprofile-0.9.4.mod/libop/op_alloc_counter.c 2009-01-29
17:06:47.000000000 +0000
@@ -51,11 +51,10 @@
for (i = 0; i < nr_events; ++i) {
int j;
- u32 mask = pev[i]->counter_mask;
-
+ u64 mask = pev[i]->counter_mask;
list_init(&ctr_arc[i].next);
for (j = 0; mask; ++j) {
- if (mask & (1 << j)) {
+ if (mask & (1ULL << j)) {
counter_arc * arc =
xmalloc(sizeof(counter_arc));
arc->counter = j;
@@ -67,7 +66,7 @@
* debugging code
*/
list_add_tail(&arc->next,
&ctr_arc[i].next);
- mask &= ~(1 << j);
+ mask &= ~(1ULL << j);
}
}
}
@@ -119,12 +118,12 @@
* counter rather on counter (this is not an improvment if each counter
goes
* in it's own class)
*/
+#include <stdio.h>
static int
allocate_counter(counter_arc_head const * ctr_arc, int max_depth, int
depth,
- u32 allocated_mask, size_t * counter_map)
+ u64 allocated_mask, size_t * counter_map)
{
struct list_head * pos;
-
if (depth == max_depth)
return 1;
@@ -130,14 +129,13 @@
list_for_each(pos, &ctr_arc[depth].next) {
counter_arc const * arc = list_entry(pos, counter_arc,
next);
-
- if (allocated_mask & (1 << arc->counter))
+ if (allocated_mask & (1ULL << arc->counter))
continue;
counter_map[depth] = arc->counter;
if (allocate_counter(ctr_arc, max_depth, depth + 1,
- allocated_mask | (1 <<
arc->counter),
+ allocated_mask | (1ULL <<
arc->counter),
counter_map))
return 1;
}
@@ -160,12 +158,12 @@
* < 0 could not determine number of counters
*
*/
-static int op_get_counter_mask(u32 * mask)
+static int op_get_counter_mask(u64 * mask)
{
struct dirent **counterlist;
int count, i;
/* assume nothing is available */
- u32 available=0;
+ u64 available=0ULL;
count = scandir("/dev/oprofile", &counterlist, perfcounterdir,
alphasort);
@@ -174,7 +172,7 @@
return -1;
/* convert to bit map (0 where counter exists) */
for (i=0; i<count; ++i) {
- available |= 1 << atoi(counterlist[i]->d_name);
+ available |= 1ULL << atoi(counterlist[i]->d_name);
free(counterlist[i]);
}
*mask=~available;
@@ -188,13 +186,13 @@
counter_arc_head * ctr_arc;
size_t * counter_map;
int nr_counters;
- u32 unavailable_counters = 0;
+ u64 unavailable_counters = 0ULL;
nr_counters = op_get_counter_mask(&unavailable_counters);
/* no counters then probably perfmon managing perfmon hw */
if (nr_counters <= 0) {
nr_counters = op_get_nr_counters(cpu_type);
- unavailable_counters = (~0) << nr_counters;
+ unavailable_counters = (~0ULL) << nr_counters;
}
if (nr_counters < nr_events)
return 0;
diff -NaurBb oprofile-0.9.4.dist/libop/op_cpu_type.c
oprofile-0.9.4.mod/libop/op_cpu_type.c
--- oprofile-0.9.4.dist/libop/op_cpu_type.c 2008-02-22
16:17:48.000000000 +0000
+++ oprofile-0.9.4.mod/libop/op_cpu_type.c 2009-03-09
12:37:17.000000000 +0000
@@ -69,11 +69,14 @@
{ "ppc64 Cell Broadband Engine", "ppc64/cell-be",
CPU_PPC64_CELL, 8 },
{ "AMD64 family10", "x86-64/family10", CPU_FAMILY10, 4 },
{ "ppc64 PA6T", "ppc64/pa6t", CPU_PPC64_PA6T, 6 },
- { "ARM MPCore", "arm/mpcore", CPU_ARM_MPCORE, 2 },
+ { "ARM 11MPCore", "arm/11mpcore", CPU_ARM_11MPCORE, 42 },
{ "ARM V6 PMU", "arm/armv6", CPU_ARM_V6, 3 },
{ "ppc64 POWER5++", "ppc64/power5++", CPU_PPC64_POWER5pp, 6 },
{ "e300", "ppc/e300", CPU_PPC_E300, 4 },
{ "AVR32", "avr32", CPU_AVR32, 3 },
+ { "ARM Cortex A9", "arm/a9", CPU_ARM_A9, 42 },
+ { "ARM Cortex A9MPCore", "arm/a9mpcore", CPU_ARM_A9MPCORE, 42 },
+ { "ARM Cortex A8", "arm/a8", CPU_ARM_A8, 8 },
};
static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct
cpu_descr);
diff -NaurBb oprofile-0.9.4.dist/libop/op_cpu_type.h
oprofile-0.9.4.mod/libop/op_cpu_type.h
--- oprofile-0.9.4.dist/libop/op_cpu_type.h 2008-02-22
16:17:48.000000000 +0000
+++ oprofile-0.9.4.mod/libop/op_cpu_type.h 2009-01-08
11:41:32.000000000 +0000
@@ -67,11 +67,14 @@
CPU_PPC64_CELL, /**< ppc64 Cell Broadband Engine*/
CPU_FAMILY10, /**< AMD family 10 */
CPU_PPC64_PA6T, /**< ppc64 PA6T */
- CPU_ARM_MPCORE, /**< ARM MPCore */
+ CPU_ARM_11MPCORE, /**< ARM 11MPCore */
CPU_ARM_V6, /**< ARM V6 */
CPU_PPC64_POWER5pp, /**< ppc64 Power5++ family */
CPU_PPC_E300, /**< e300 */
CPU_AVR32, /**< AVR32 */
+ CPU_ARM_A9, /**< ARM Cortex A9 */
+ CPU_ARM_A9MPCORE, /**< ARM Cortex A9MPCore */
+ CPU_ARM_A8, /**< ARM Cortex A8 */
MAX_CPU_TYPE
} op_cpu;
diff -NaurBb oprofile-0.9.4.dist/libop/op_events.c
oprofile-0.9.4.mo...
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