[oprof-cvs] CVS: oprofile/events/x86-64/family10 events,1.3,1.4

[Maynard J. <may...@us...>]

Update of /cvsroot/oprofile/oprofile/events/x86-64/family10
In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv801/events/x86-64/family10

Modified Files:
	events 
Log Message:
whitespace cleanup

Index: events
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/x86-64/family10/events,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -p -d -r1.3 -r1.4
--- events	21 May 2008 00:31:07 -0000	1.3
+++ events	24 Nov 2008 16:39:31 -0000	1.4
@@ -48,7 +48,7 @@ event:0x47 counters:0,1,2,3 um:zero mini
 event:0x48 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_LATE_CANCEL_ACCESS : Microarchitectural late cancel of an access
 event:0x49 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_EARLY_CANCEL_ACCESS : Microarchitectural early cancel of an access
 event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:1_BIT_ECC_ERRORS : Single-bit ECC errors recorded by scrubber
-event:0x4b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : The number of prefetch instructions dispatched by the decoder 
+event:0x4b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : The number of prefetch instructions dispatched by the decoder
 event:0x4c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISSES : The number of dta cache misses by locked instructions.
 event:0x4d counters:0,1,2,3 um:l1_dtlb_hit minimum:500 name:L1_DTLB_HIT : L1 DTLB hit
 event:0x52 counters:0,1,2,3 um:soft_prefetch minimum:500 name:INEFFECTIVE_SW_PREFETCHES : Number of software prefetches that did not fetch data outside of processor core