[oprof-cvs] CVS: oprofile-www/docs amd-hammer-events,1.1,1.2

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Update of /cvsroot/oprofile/oprofile-www/docs
In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv19643/docs

Modified Files:
	amd-hammer-events 
Log Message:
updates for new release

Index: amd-hammer-events
===================================================================
RCS file: /cvsroot/oprofile/oprofile-www/docs/amd-hammer-events,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -p -d -r1.1 -r1.2

--- amd-hammer-events	19 Oct 2007 11:47:09 -0000	1.1
+++ amd-hammer-events	18 Jul 2008 00:33:48 -0000	1.2
@@ -1,24 +1,81 @@
-<tr><td>CPU_CLK_UNHALTED</td><td>	Cycles outside of halt state </td><td> all</td><td>
+<tr><td>DISPATCHED_FPU_OPS</td><td>	Dispatched FPU ops </td><td> all</td><td>
+	0x01: Add pipe ops
+ <br />
+	0x02: Multiply pipe
+ <br />
+	0x04: Store pipe ops
+ <br />
+	0x08: Add pipe load ops
+ <br />
+	0x10: Multiply pipe load ops
+ <br />
+	0x20: Store pipe load ops
+ <br />
 </td>
 
 </tr>
 
-<tr><td>RETIRED_INSTRUCTIONS</td><td>	Retired instructions (includes exceptions, interrupts, re-syncs) </td><td> all</td><td>
+<tr><td>CYCLES_NO_FPU_OPS_RETIRED</td><td>	Cycles with no FPU ops retired </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>RETIRED_UOPS</td><td>	Retired micro-ops </td><td> all</td><td>
+<tr><td>DISPATCHED_FPU_OPS_FAST_FLAG</td><td>	Dispatched FPU ops that use the fast flag interface </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>INSTRUCTION_CACHE_FETCHES</td><td>	Instruction cache fetches (RevE) </td><td> all</td><td>
+<tr><td>SEGMENT_REGISTER_LOADS</td><td>	Segment register loads </td><td> all</td><td>
+	0x01: ES register
+ <br />
+	0x02: CS register
+ <br />
+	0x04: SS register
+ <br />
+	0x08: DS register
+ <br />
+	0x10: FS register
+ <br />
+	0x20: GS register
+ <br />
+	0x40: HS register
+ <br />
 </td>
 
 </tr>
 
-<tr><td>INSTRUCTION_CACHE_MISSES</td><td>	Instruction cache misses </td><td> all</td><td>
+<tr><td>PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE</td><td>	Micro-architectural re-sync caused by self modifying code </td><td> all</td><td>
+</td>
+
+</tr>
+
+<tr><td>PIPELINE_RESTART_DUE_TO_PROBE_HIT</td><td>	Micro-architectural re-sync caused by snoop </td><td> all</td><td>
+</td>
+
+</tr>
+
+<tr><td>LS_BUFFER_2_FULL_CYCLES</td><td>	Cycles LS Buffer 2 full </td><td> all</td><td>
+</td>
+
+</tr>
+
+<tr><td>LOCKED_OPS</td><td>	Locked operations </td><td> all</td><td>
+	0x01: The number of locked instructions executed
+ <br />
+	0x02: The number of cycles spent in speculative phase
+ <br />
+	0x04: The number of cycles spent in non-speculative phase (including cache miss penalty)
+ <br />
+</td>
+
+</tr>
+
+<tr><td>RETIRED_CLFLUSH_INSTRUCTIONS</td><td>	Retired CLFLUSH instructions </td><td> all</td><td>
+</td>
+
+</tr>
+
+<tr><td>RETIRED_CPUID_INSTRUCTIONS</td><td>	Retired CPUID instructions </td><td> all</td><td>
 </td>
 
 </tr>
@@ -34,15 +91,15 @@
 </tr>
 
 <tr><td>DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM</td><td>	Data cache refills from L2 or system </td><td> all</td><td>
-	0x10: (M)odified cache state
+	0x01: refill from system
  <br />
-	0x08: (O)wner cache state
+	0x02: (S)hared cache state from L2
  <br />
-	0x04: (E)xclusive cache state
+	0x04: (E)xclusive cache state from L2
  <br />
-	0x02: (S)hared cache state
+	0x08: (O)wned cache state from L2
  <br />
-	0x01: refill from system
+	0x10: (M)odified cache state from L2
  <br />
 	0x1e: All cache states except Invalid
  <br />
@@ -51,15 +108,15 @@
 </tr>
 
 <tr><td>DATA_CACHE_REFILLS_FROM_SYSTEM</td><td>	Data cache refills from system </td><td> all</td><td>
-	0x10: (M)odified cache state
+	0x01: (I)nvalid cache state
  <br />
-	0x08: (O)wner cache state
+	0x02: (S)hared cache state
  <br />
 	0x04: (E)xclusive cache state
  <br />
-	0x02: (S)hared cache state
+	0x08: (O)wned cache state
  <br />
-	0x01: (I)nvalid cache state
+	0x10: (M)odified cache state
  <br />
 	0x1f: All cache states
  <br />
@@ -68,15 +125,15 @@
 </tr>
 
 <tr><td>DATA_CACHE_LINES_EVICTED</td><td>	Data cache lines evicted </td><td> all</td><td>
-	0x10: (M)odified cache state
+	0x01: (I)nvalid cache state
  <br />
-	0x08: (O)wner cache state
+	0x02: (S)hared cache state
  <br />
 	0x04: (E)xclusive cache state
  <br />
-	0x02: (S)hared cache state
+	0x08: (O)wned cache state
  <br />
-	0x01: (I)nvalid cache state
+	0x10: (M)odified cache state
  <br />
 	0x1f: All cache states
  <br />
@@ -84,26 +141,6 @@
 
 </tr>
 
-<tr><td>RETIRED_BRANCH_INSTRUCTIONS</td><td>	Retired branches (conditional, unconditional, exceptions, interrupts) </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS</td><td>	Retired Mispredicted Branch Instructions </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS</td><td>	Retired taken branch instructions </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED</td><td>	Retired taken branches mispredicted </td><td> all</td><td>
-</td>
-
-</tr>
-
 <tr><td>L1_DTLB_MISS_AND_L2_DTLB_HIT</td><td>	L1 DTLB misses and L2 DTLB hits </td><td> all</td><td>
 </td>
 
@@ -119,262 +156,207 @@
 
 </tr>
 
-<tr><td>L1_ITLB_MISS_AND_L2_ITLB_HIT</td><td>	L1 ITLB misses (and L2 ITLB hits) </td><td> all</td><td>
+<tr><td>MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS</td><td>	Micro-architectural late cancel of an access </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>L1_ITLB_MISS_AND_L2_ITLB_MISS</td><td>	L1 ITLB Miss, L2 ITLB Miss </td><td> all</td><td>
+<tr><td>MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS</td><td>	Micro-architectural early cancel of an access </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>RETIRED_FAR_CONTROL_TRANSFERS</td><td>	Retired far control transfers </td><td> all</td><td>
+<tr><td>SCRUBBER_SINGLE_BIT_ECC_ERRORS</td><td>	One bit ECC error recorded by scrubber </td><td> all</td><td>
+	0x01: Scrubber error
+ <br />
+	0x02: Piggyback scrubber errors
+ <br />
 </td>
 
 </tr>
 
-<tr><td>RETIRED_BRANCH_RESYNCS</td><td>	Retired branches resyncs (only non-control transfer branches) </td><td> all</td><td>
+<tr><td>PREFETCH_INSTRUCTIONS_DISPATCHED</td><td>	Prefetch instructions dispatched </td><td> all</td><td>
+	0x01: Load
+ <br />
+	0x02: Store
+ <br />
+	0x04: NTA
+ <br />
 </td>
 
 </tr>
 
-<tr><td>INTERRUPTS_MASKED_CYCLES</td><td>	Cycles with interrupts masked (IF=0) </td><td> all</td><td>
+<tr><td>DCACHE_MISS_LOCKED_INSTRUCTIONS</td><td>	DCACHE misses by locked instructions </td><td> all</td><td>
+	0x02: Data cache misses by locked instructions
+ <br />
 </td>
 
 </tr>
 
-<tr><td>INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING</td><td>	Cycles with interrupts masked while interrupt pending </td><td> all</td><td>
+<tr><td>MEMORY_REQUESTS</td><td>	Memory requests by type </td><td> all</td><td>
+	0x01: Requests to non-cacheable (UC) memory
+ <br />
+	0x02: Requests to write-combining (WC) memory or WC buffer flushes to WB memory
+ <br />
+	0x80: Streaming store (SS) requests
+ <br />
 </td>
 
 </tr>
 
-<tr><td>INTERRUPTS_TAKEN</td><td>	Number of taken hardware interrupts </td><td> all</td><td>
+<tr><td>DATA_PREFETCHES</td><td>	Data prefetcher </td><td> all</td><td>
+	0x01: Cancelled prefetches
+ <br />
+	0x02: Prefetch attempts
+ <br />
 </td>
 
 </tr>
 
-<tr><td>DISPATCHED_FPU_OPS</td><td>	Dispatched FPU ops </td><td> all</td><td>
-	0x01: Add pipe ops
- <br />
-	0x02: Multiply pipe
- <br />
-	0x04: Store pipe ops
- <br />
-	0x08: Add pipe load ops
+<tr><td>SYSTEM_READ_RESPONSES</td><td>	System read responses by coherency state </td><td> all</td><td>
+	0x01: Exclusive
  <br />
-	0x10: Multiply pipe load ops
+	0x02: Modified
  <br />
-	0x20: Store pipe load ops
+	0x04: Shared
  <br />
 </td>
 
 </tr>
 
-<tr><td>CYCLES_NO_FPU_OPS_RETIRED</td><td>	Cycles with no FPU ops retired </td><td> all</td><td>
+<tr><td>QUADWORD_WRITE_TRANSFERS</td><td>	Quadwords written to system </td><td> all</td><td>
+	0x01: Quadword write transfer
+ <br />
 </td>
 
 </tr>
 
-<tr><td>DISPATCHED_FPU_OPS_FAST_FLAG</td><td>	Dispatched FPU ops that use the fast flag interface </td><td> all</td><td>
+<tr><td>CPU_CLK_UNHALTED</td><td>	Cycles outside of halt state </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>SEGMENT_REGISTER_LOADS</td><td>	Segment register loads </td><td> all</td><td>
-	0x01: ES register
- <br />
-	0x02: CS register
- <br />
-	0x04: SS register
+<tr><td>REQUESTS_TO_L2</td><td>	Requests to L2 cache </td><td> all</td><td>
+	0x01: IC fill
  <br />
-	0x08: DS register
+	0x02: DC fill
  <br />
-	0x10: FS register
+	0x04: TLB fill (page table walk)
  <br />
-	0x20: GS register
+	0x08: Tag snoop request
  <br />
-	0x40: HS register
+	0x10: Cancelled request
  <br />
 </td>
 
 </tr>
 
-<tr><td>PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE</td><td>	Micro-architectural re-sync caused by self modifying code </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>PIPELINE_RESTART_DUE_TO_PROBE_HIT</td><td>	Micro-architectural re-sync caused by snoop </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>LS_BUFFER_2_FULL_CYCLES</td><td>	Cycles LS Buffer 2 Full </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>LOCKED_OPS</td><td>	Locked operations </td><td> all</td><td>
-	0x01: The number of locked instructions executed
+<tr><td>L2_CACHE_MISS</td><td>	L2 cache misses </td><td> all</td><td>
+	0x01: IC fill
  <br />
-	0x02: The number of cycles spent in speculative phase
+	0x02: DC fill
  <br />
-	0x04: The number of cycles spent in non-speculative phase (including cache miss penalty)
+	0x04: TLB page table walk
  <br />
 </td>
 
 </tr>
 
-<tr><td>OP_LATE_CANCEL</td><td>	Micro-architectural late cancel of an operation </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>RETIRED_CLFLUSH_INSTRUCTIONS</td><td>	Retired CLFLUSH instructions </td><td> all</td><td>
-</td>
-
-</tr>
-
-<tr><td>RETIRED_CPUID_INSTRUCTIONS</td><td>	Retired CPUID instructions </td><td> all</td><td>
+<tr><td>L2_CACHE_FILL_WRITEBACK</td><td>	L2 fill/writeback </td><td> all</td><td>
+	0x01: L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
+ <br />
+	0x02: L2 writebacks to system
+ <br />
 </td>
 
 </tr>
 
-<tr><td>MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS</td><td>	Micro-architectural late cancel of an access </td><td> all</td><td>
+<tr><td>INSTRUCTION_CACHE_FETCHES</td><td>	Instruction cache fetches </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS</td><td>	Micro-architectural early cancel of an access </td><td> all</td><td>
+<tr><td>INSTRUCTION_CACHE_MISSES</td><td>	Instruction cache misses </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>SCRUBBER_SINGLE_BIT_ECC_ERRORS</td><td>	One bit ECC error recorded by scrubber </td><td> all</td><td>
-	0x01: Scrubber error
- <br />
-	0x02: Piggyback scrubber errors
- <br />
+<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_L2</td><td>	Instruction cache refills from L2 </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>PREFETCH_INSTRUCTIONS_DISPATCHED</td><td>	Prefetch Instructions Dispatched </td><td> all</td><td>
-	0x01: Load
- <br />
-	0x02: Store
- <br />
-	0x04: NTA
- <br />
+<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM</td><td>	Instruction cache refills from system </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>DCACHE_MISS_LOCKED_INSTRUCTIONS</td><td>	DCACHE Misses by Locked Instructions </td><td> all</td><td>
-	0x02: Data Cache Misses by Locked Instructions
- <br />
+<tr><td>L1_ITLB_MISS_AND_L2_ITLB_HIT</td><td>	L1 ITLB miss and L2 ITLB hit </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>MEMORY_REQUESTS</td><td>	Memory Requests by Type </td><td> all</td><td>
-	0x01: Requests to non-cacheable (UC) memory
- <br />
-	0x02: Requests to write-combining (WC) memory or WC buffer flushes to WB memory
- <br />
-	0x80: Streaming store (SS) requests
- <br />
+<tr><td>L1_ITLB_MISS_AND_L2_ITLB_MISS</td><td>	L1 ITLB miss and L2 ITLB miss </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>DATA_PREFETCHES</td><td>	Data Prefetcher </td><td> all</td><td>
-	0x01: Cancelled prefetches
- <br />
-	0x02: Prefetch attempts
- <br />
+<tr><td>PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE</td><td>	Pipeline restart due to instruction stream probe </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>SYSTEM_READ_RESPONSES</td><td>	System Read Responses by Coherency State </td><td> all</td><td>
-	0x01: Exclusive
- <br />
-	0x02: Modified
- <br />
-	0x04: Shared
- <br />
+<tr><td>INSTRUCTION_FETCH_STALL</td><td>	Instruction fetch stall </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>QUADWORD_WRITE_TRANSFERS</td><td>	Quadwords Written to System </td><td> all</td><td>
+<tr><td>RETURN_STACK_HITS</td><td>	Return stack hits </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>REQUESTS_TO_L2</td><td>	Requests to L2 Cache </td><td> all</td><td>
-	0x01: IC fill
- <br />
-	0x02: DC fill
- <br />
-	0x04: TLB reload
- <br />
-	0x08: Tag snoop request
- <br />
-	0x10: Canceled request
- <br />
+<tr><td>RETURN_STACK_OVERFLOWS</td><td>	Return stack overflows </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>L2_CACHE_MISS</td><td>	L2 Cache Misses </td><td> all</td><td>
-	0x01: IC fill
- <br />
-	0x02: DC fill
- <br />
-	0x04: TLB reload
- <br />
+<tr><td>RETIRED_INSTRUCTIONS</td><td>	Retired instructions (includes exceptions, interrupts, re-syncs) </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>L2_CACHE_FILL_WRITEBACK</td><td>	L2 Fill/Writeback </td><td> all</td><td>
-	0x01: L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
- <br />
-	0x02: L2 Writebacks to system
- <br />
+<tr><td>RETIRED_UOPS</td><td>	Retired micro-ops </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_L2</td><td>	Instruction Cache Refills from L2 </td><td> all</td><td>
+<tr><td>RETIRED_BRANCH_INSTRUCTIONS</td><td>	Retired branches (conditional, unconditional, exceptions, interrupts) </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM</td><td>	Instruction Cache Refills from System </td><td> all</td><td>
+<tr><td>RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS</td><td>	Retired mispredicted branch instructions </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE</td><td>	Pipeline Restart Due to Instruction Stream Probe </td><td> all</td><td>
+<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS</td><td>	Retired taken branch instructions </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>INSTRUCTION_FETCH_STALL</td><td>	Instruction fetch stall </td><td> all</td><td>
+<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED</td><td>	Retired taken branches mispredicted </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>RETURN_STACK_HITS</td><td>	Return stack hit </td><td> all</td><td>
+<tr><td>RETIRED_FAR_CONTROL_TRANSFERS</td><td>	Retired far control transfers </td><td> all</td><td>
 </td>
 
 </tr>
 
-<tr><td>RETURN_STACK_OVERFLOWS</td><td>	Return stack overflow </td><td> all</td><td>
+<tr><td>RETIRED_BRANCH_RESYNCS</td><td>	Retired branches resyncs (only non-control transfer branches) </td><td> all</td><td>
 </td>
 
 </tr>
@@ -389,7 +371,7 @@
 
 </tr>
 
-<tr><td>RETIRED_INDIRECT_BRANCHES_MISPREDICTED</td><td>	Retired Indirect Branches Mispredicted </td><td> all</td><td>
+<tr><td>RETIRED_INDIRECT_BRANCHES_MISPREDICTED</td><td>	Retired indirect branches mispredicted </td><td> all</td><td>
 </td>
 
 </tr>
@@ -418,6 +400,21 @@
 
 </tr>
 
+<tr><td>INTERRUPTS_MASKED_CYCLES</td><td>	Cycles with interrupts masked (IF=0) </td><td> all</td><td>
+</td>
+
+</tr>
+
+<tr><td>INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING</td><td>	Cycles with interrupts masked while interrupt pending </td><td> all</td><td>
+</td>
+
+</tr>
+
+<tr><td>INTERRUPTS_TAKEN</td><td>	Number of taken hardware interrupts </td><td> all</td><td>
+</td>
+
+</tr>
+
 <tr><td>DECODER_EMPTY</td><td>	Nothing to dispatch (decoder empty) </td><td> all</td><td>
 </td>
 
@@ -468,7 +465,7 @@
 
 </tr>
 
-<tr><td>DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC</td><td>	Dispatch Stall for Far Transfer or Resync to Retire </td><td> all</td><td>
+<tr><td>DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC</td><td>	Dispatch stall for far transfer or resync to retire </td><td> all</td><td>
 </td>
 
 </tr>
@@ -506,7 +503,7 @@
 
 </tr>
 
-<tr><td>DRAM_ACCESSES</td><td>	DRAM Accesses </td><td> all</td><td>
+<tr><td>DRAM_ACCESSES</td><td>	DRAM accesses </td><td> all</td><td>
 	0x01: Page hit
  <br />
 	0x02: Page miss
@@ -546,105 +543,100 @@
 
 </tr>
 
-<tr><td>THERMAL_STATUS_AND_DRAM_ECC_ERRORS</td><td>	Thermal status and ECC errors </td><td> all</td><td>
-	0x01: Number of clocks CPU is active when HTC is active
- <br />
-	0x02: Number of clocks CPU clock is inactive when HTC is active
+<tr><td>SIZED_BLOCKS</td><td>	Sized blocks </td><td> all</td><td>
+	0x04: 32-byte Sized Writes (RevD and later)
  <br />
-	0x04: Number of clocks when die temperature is higher than the software high temperature threshold
+	0x08: 64-byte Sized Writes (RevD and later)
  <br />
-	0x08: Number of clocks when high temperature threshold was exceeded
+	0x10: 32-byte Sized Reads (RevD and later)
  <br />
-	0x80: Number of correctable and uncorrectable DRAM ECC errors
+	0x20: 64-byte Sized Reads (RevD and later)
  <br />
 </td>
 
 </tr>
 
-<tr><td>GART_EVENTS</td><td>	GART Events </td><td> all</td><td>
-	0x01: GART aperture hit on access from CPU
- <br />
-	0x02: GART aperture hit on access from I/O
- <br />
-	0x04: GART miss
+<tr><td>THERMAL_STATUS_AND_DRAM_ECC_ERRORS</td><td>	Thermal status and ECC errors </td><td> all</td><td>
+	0x01: Number of clocks CPU is active when HTC is active (RevF)
  <br />
-</td>
-
-</tr>
-
-<tr><td>SIZED_BLOCKS</td><td>	Sized Blocks </td><td> all</td><td>
-	0x04: 32-byte Sized Writes (RevD)
+	0x02: Number of clocks CPU clock is inactive when HTC is active (RevF)
  <br />
-	0x08: 64-byte Sized Writes (RevD)
+	0x04: Number of clocks when die temperature is higher than the software high temperature threshold (RevF)
  <br />
-	0x10: 32-byte Sized Reads (RevD)
+	0x08: Number of clocks when high temperature threshold was exceeded (RevF)
  <br />
-	0x20: 64-byte Sized Reads (RevD)
+	0x80: Number of correctable and uncorrectable DRAM ECC errors (RevE)
  <br />
 </td>
 
 </tr>
 
-<tr><td>CPU_IO_REQUESTS_TO_MEMORY_IO</td><td>	CPU/IO Requests to Memory/IO (RevE) </td><td> all</td><td>
+<tr><td>CPU_IO_REQUESTS_TO_MEMORY_IO</td><td>	CPU/IO requests to memory/IO (RevE) </td><td> all</td><td>
+	0xa1: Requests Local I/O to Local I/O
+ <br />
 	0xa2: Requests Local I/O to Local Memory
  <br />
-	0xa1: Requests Local I/O to Local I/O
+	0xa3: Requests Local I/O to Local (I/O or Mem) 
  <br />
-	0xa3: Requests Local I/O to Local Any
+	0xa4: Requests Local CPU to Local I/O
  <br />
-	0xaa: Requests Local Any to Local Memory
+	0xa5: Requests Local (CPU or I/O) to Local I/O
  <br />
-	0xa5: Requests Local Any to Local I/O
+	0xa8: Requests Local CPU to Local Memory
  <br />
-	0xaf: Requests Local Any to Local Any
+	0xaa: Requests Local (CPU or I/O) to Local Memory
  <br />
-	0x98: Requests Local CPU to Remote Memory
+	0xac: Requests Local CPU to Local (I/O or Mem)
  <br />
-	0x94: Requests Local CPU to Remote I/O
+	0xaf: Requests Local (CPU or I/O) to Local (I/O or Mem)
  <br />
-	0x9c: Requests Local CPU to Remote Any
+	0x91: Requests Local I/O to Remote I/O
  <br />
 	0x92: Requests Local I/O to Remote Memory
  <br />
-	0x91: Requests Local I/O to Remote I/O
+	0x93: Requests Local I/O to Remote (I/O or Mem)
  <br />
-	0x93: Requests Local I/O to Remote Any
+	0x94: Requests Local CPU to Remote I/O
  <br />
-	0x9a: Requests Local Any to Remote Memory
+	0x95: Requests Local (CPU or I/O) to Remote I/O
  <br />
-	0x95: Requests Local Any to Remote I/O
+	0x98: Requests Local CPU to Remote Memory
  <br />
-	0x9f: Requests Local Any to Remote Any
+	0x9a: Requests Local (CPU or I/O) to Remote Memory
  <br />
-	0xb8: Requests Local CPU to Any Memory
+	0x9c: Requests Local CPU to Remote (I/O or Mem)
  <br />
-	0xb4: Requests Local CPU to Any I/O
+	0x9f: Requests Local (CPU or I/O) to Remote (I/O or Mem)
  <br />
-	0xbc: Requests Local CPU to Any Any
+	0xb1: Requests Local I/O to Any I/O
  <br />
 	0xb2: Requests Local I/O to Any Memory
  <br />
-	0xb1: Requests Local I/O to Any I/O
+	0xb3: Requests Local I/O to Any (I/O or Mem)
  <br />
-	0xb3: Requests Local I/O to Any Any
+	0xb4: Requests Local CPU to Any I/O
  <br />
-	0xba: Requests Local Any to Any Memory
+	0xb5: Requests Local (CPU or I/O) to Any I/O
  <br />
-	0xb5: Requests Local Any to Any I/O
+	0xb8: Requests Local CPU to Any Memory
  <br />
-	0xbf: Requests Local Any to Any Any
+	0xba: Requests Local (CPU or I/O) to Any Memory
  <br />
-	0x64: Requests Remote CPU to Local I/O
+	0xbc: Requests Local CPU to Any (I/O or Mem)
+ <br />
+	0xbf: Requests Local (CPU or I/O) to Any (I/O or Mem)
  <br />
 	0x61: Requests Remote I/O to Local I/O
  <br />
-	0x65: Requests Remote Any to Local I/O
+	0x64: Requests Remote CPU to Local I/O
+ <br />
+	0x65: Requests Remote (CPU or I/O) to Local I/O
  <br />
 </td>
 
 </tr>
 
-<tr><td>CACHE_BLOCK_COMMANDS</td><td>	Cache Block Commands (RevE) </td><td> all</td><td>
+<tr><td>CACHE_BLOCK_COMMANDS</td><td>	Cache block commands (RevE) </td><td> all</td><td>
 	0x01: Victim Block (Writeback)
  <br />
 	0x04: Read Block (Dcache load miss refill)
@@ -659,26 +651,26 @@
 
 </tr>
 
-<tr><td>SIZED_COMMANDS</td><td>	Sized Commands </td><td> all</td><td>
-	0x01: non-posted write byte
+<tr><td>SIZED_COMMANDS</td><td>	Sized commands </td><td> all</td><td>
+	0x01: Non-posted write byte
  <br />
-	0x02: non-posted write dword
+	0x02: Non-posted write dword
  <br />
-	0x04: posted write byte
+	0x04: Posted write byte
  <br />
-	0x08: posted write dword
+	0x08: Posted write dword
  <br />
-	0x10: read byte (4 bytes)
+	0x10: Read byte (4 bytes)
  <br />
-	0x20: read dword (1-16 dwords)
+	0x20: Read dword (1-16 dwords)
  <br />
-	0x40: read-modify-write
+	0x40: Read-modify-write
  <br />
 </td>
 
 </tr>
 
-<tr><td>PROBE_RESPONSES_AND_UPSTREAM_REQUESTS</td><td>	Probe Responses and Upstream Requests </td><td> all</td><td>
+<tr><td>PROBE_RESPONSES_AND_UPSTREAM_REQUESTS</td><td>	Probe responses and upstream requests </td><td> all</td><td>
 	0x01: Probe miss
  <br />
 	0x02: Probe hit clean
@@ -691,13 +683,24 @@
  <br />
 	0x20: Upstream non-display refresh reads
  <br />
-	0x40: Upstream writes
+	0x40: Upstream writes (RevD and later)
  <br />
 </td>
 
 </tr>
 
-<tr><td>HYPERTRANSPORT_LINK0_BANDWIDTH</td><td>	HyperTransport(tm) link 0 bandwidth </td><td> all</td><td>
+<tr><td>GART_EVENTS</td><td>	GART events </td><td> all</td><td>
+	0x01: GART aperture hit on access from CPU
+ <br />
+	0x02: GART aperture hit on access from I/O
+ <br />
+	0x04: GART miss
+ <br />
+</td>
+
+</tr>
+
+<tr><td>HYPERTRANSPORT_LINK0_BANDWIDTH</td><td>	HyperTransport(tm) link 0 transmit bandwidth </td><td> all</td><td>
 	0x01: Command sent
  <br />
 	0x02: Data sent
@@ -710,7 +713,7 @@
 
 </tr>
 
-<tr><td>HYPERTRANSPORT_LINK1_BANDWIDTH</td><td>	HyperTransport(tm) link 1 bandwidth </td><td> all</td><td>
+<tr><td>HYPERTRANSPORT_LINK1_BANDWIDTH</td><td>	HyperTransport(tm) link 1 transmit bandwidth </td><td> all</td><td>
 	0x01: Command sent
  <br />
 	0x02: Data sent
@@ -723,7 +726,7 @@
 
 </tr>
 
-<tr><td>HYPERTRANSPORT_LINK2_BANDWIDTH</td><td>	HyperTransport(tm) link 2 bandwidth </td><td> all</td><td>
+<tr><td>HYPERTRANSPORT_LINK2_BANDWIDTH</td><td>	HyperTransport(tm) link 2 transmit bandwidth </td><td> all</td><td>
 	0x01: Command sent
  <br />
 	0x02: Data sent



