Re: update core_2 events

[dean g. <de...@ar...>]

On Wed, 13 Jun 2007, John Levon wrote:

> On Tue, Jun 12, 2007 at 06:00:35PM -0700, dean gaudet wrote:
> 
> > - L2_M_LINES_IN supports only the "core" unit mask
> 
> It'd be great if you could do a ChangeLog entry.
> 
> > - add a RS_UOPS_DISPATCHED_NONE event which sets the INV bit and CMASK to 
> >   1 -- so that it counts cycles which issue less than 1 uop.  this is a
> >   rough estimation of total stall cycles.  it's a bit of an abuse to do
> >   this but it passes through the oprofile machinery just fine.
> 
> I think we can live with the abuse, but please document what's happening
> in the events file above the 'weird' event number.

cool, how's this?

-dean

Index: ChangeLog
===================================================================
RCS file: /cvsroot/oprofile/oprofile/ChangeLog,v
retrieving revision 1.1735
diff -u -r1.1735 ChangeLog
--- ChangeLog	8 Jun 2007 12:17:20 -0000	1.1735
+++ ChangeLog	13 Jun 2007 04:23:35 -0000
@@ -1,4 +1,11 @@
-2007-06-08  Dean Gaudet  <dg...@us...>
+2007-06-12  dean gaudet  <de...@ar...>
+
+	* events/i386/core_2/events:
+	* events/i386/core_2/unit_masks:  updates to match
+	  253669-022US ISA vol 3B from Intel.  (Including fix
+	  for #1580064 from Arun Sharma.)
+
+2007-06-08  dean gaudet  <de...@ar...>
 
 	* events/x86-64/hammer/events:
 	* events/x86-64/hammer/unit_masks: updates from December 2006
Index: events/i386/core_2/events
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/i386/core_2/events,v
retrieving revision 1.5
diff -u -r1.5 events
--- events/i386/core_2/events	20 May 2007 21:32:04 -0000	1.5
+++ events/i386/core_2/events	13 Jun 2007 04:23:35 -0000
@@ -28,7 +28,7 @@
 event:0x21 counters:0,1 um:core minimum:500 name:L2_ADS : Cycles the L2 address bus is in use.
 event:0x23 counters:0,1 um:core minimum:500 name:L2_DBUS_BUSY_RD : Cycles the L2 transfers data to the core.
 event:0x24 counters:0,1 um:core_prefetch minimum:500 name:L2_LINES_IN : number of allocated lines in L2
-event:0x25 counters:0,1 um:core_prefetch minimum:500 name:L2_M_LINES_IN : number of modified lines allocated in L2
+event:0x25 counters:0,1 um:core minimum:500 name:L2_M_LINES_IN : number of modified lines allocated in L2
 event:0x26 counters:0,1 um:core_prefetch minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
 event:0x27 counters:0,1 um:core_prefetch minimum:500 name:L2_M_LINES_OUT : number of modified lines removed from L2
 event:0x28 counters:0,1 um:core_mesi minimum:500 name:L2_IFETCH : number of L2 cacheable instruction fetches
@@ -48,7 +48,7 @@
 event:0x45 counters:0,1 um:x0f minimum:500 name:L1D_REPL : Cache lines allocated in the L1 data cache
 event:0x46 counters:0,1 um:zero minimum:500 name:L1D_M_REPL : Modified cache lines allocated in the L1 data cache
 event:0x47 counters:0,1 um:zero minimum:500 name:L1D_M_EVICT : Modified cache lines evicted from the L1 data cache
-event:0x48 counters:0,1 um:dc_pend_miss minimum:500 name:L1D_PEND_MISS : Weighted cycles of L1 miss outstanding
+event:0x48 counters:0,1 um:zero minimum:500 name:L1D_PEND_MISS : Total number of outstanding L1 data cache misses at any cycle
 event:0x49 counters:0,1 um:l1d_split minimum:500 name:L1D_SPLIT : Cache line split load/stores
 event:0x4b counters:0,1 um:sse_miss minimum:500 name:SSE_PREF_MISS : SSE instructions that missed all caches
 event:0x4c counters:0,1 um:zero minimum:500 name:LOAD_HIT_PRE : Load operations conflicting with a software prefetch to the same address
@@ -100,6 +100,11 @@
 event:0x97 counters:0,1 um:zero minimum:3000 name:BR_TKN_BUBBLE_1 : Branch predicted taken with bubble 1
 event:0x98 counters:0,1 um:zero minimum:3000 name:BR_TKN_BUBBLE_2 : Branch predicted taken with bubble 2
 event:0xa0 counters:0,1 um:zero minimum:1000 name:RS_UOPS_DISPATCHED : Micro-ops dispatched for execution
+# Set both the CMASK and INV fields to 1 -- which causes the counter to
+# increment on cycles in which fewer than 1 uop dispatches.  i.e. stall cycles.
+# It's a bit of a hack, but passes through the oprofile infrastructure just
+# fine.
+event:0x18000a0 counters:0,1 um:zero minimum:1000 name:RS_UOPS_DISPATCHED_NONE : No Micro-ops dispatched for execution
 event:0xaa counters:0,1 um:macro_insts minimum:500 name:MACRO_INSTS : instructions decoded
 event:0xab counters:0,1 um:esp minimum:500 name:ESP : ESP register events
 event:0xb0 counters:0,1 um:zero minimum:500 name:SIMD_UOPS_EXEC : SIMD micro-ops executed (excluding stores)
Index: events/i386/core_2/unit_masks
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/i386/core_2/unit_masks,v
retrieving revision 1.3
diff -u -r1.3 unit_masks
--- events/i386/core_2/unit_masks	21 Sep 2006 16:09:37 -0000	1.3
+++ events/i386/core_2/unit_masks	13 Jun 2007 04:23:35 -0000
@@ -42,12 +42,9 @@
 	0x10 SIMD packed logical
 	0x20 SIMD packed arithmetic
 	0x3f all of the above
-name:mmx_trans type:exclusive default:0x0
-	0x00 MMX->float operations
-	0x01 float->MMX operations
-name:dc_pend_miss type:exclusive default:0x0
-	0x00 Weighted cycles
-	0x01 Duration of cycles
+name:mmx_trans type:bitmask default:0x3
+	0x01 float->MMX transitions
+	0x02 MMX->float transitions
 name:sse_miss type:exclusive default:0x0
 	0x00 PREFETCHNTA
 	0x01 PREFETCHT0
@@ -108,17 +105,18 @@
 	0x2	split stores
 name:bus_agents type:exclusive default:0x00
 	0x00	this agent
-	0x10	include all agents
+	0x20	include all agents
 name:core_and_bus_agents type:bitmask default:0x40
 	0xc0	core: all cores
 	0x40	core: this core
 	0x00	bus: this agent
-	0x10	bus: include all agents
-name:bus_agents_and_snoop type:bitmask default:0x03
+	0x20	bus: include all agents
+name:bus_agents_and_snoop type:bitmask default:0x0b
 	0x00	bus: this agent
-	0x10	bus: include all agents
-	0x01	snoop: CMP2I snoops
-	0x02	snoop: CMP2S snoops
+	0x20	bus: include all agents
+	0x08	snoop: HITM snoops
+	0x02	snoop: HIT snoops
+	0x01	snoop: CLEAN snoops
 name:core_and_snoop type:bitmask default:0x40
 	0xc0	core: all cores
 	0x40	core: this core