variable clock frequency

[Rob F. <rj...@ri...>]

> Date: Mon, 21 Feb 2005 17:05:00 -0500
> From: William Cohen <wc...@re...>
> To: oprofile-list <opr...@li...>
> Subject: variable clock frequency vs. oprofile
> 
> A number of different processors have power management systems that 
> adjust the processor clock frequency for power management.  OProfile 
> assumes that the clock period is aways the same. This variation in clock 
> frequency may make the analysis of the collected te data more 
> "interesting" because the time-based sampling in most performance 
> monitoring hardware is based on the number of processor clock cycles 
> elapsed.
> 
> For the case where the processor is slowed for power conservation each 
> sample for a number of clock cycles would represent a larger interval of 
> time.
> 
> Would it be worthwhile to have a time-based mechanism that would adjust 
> the processor cycle sample count when the clock rate changes?
> 
> -Will

At HPCA I spoke with several chip designers about this.  Today, these
features exist, but are not generally invoked on servers and other
systems designed with adequate power and heat dissipation.  (Whether
they get invoked on clusters with high density packaging is a question
worth examining.)

With the advent of multi-core chips later this year, however, throttling
will become more common --  For example, low-performance "pointer chasing"
applications might be allowed to run at full clock rate on multiple
cores because they are really spending a lot of time waiting for memory.
OTOH, multiple copies of highly optimized numeric codes, e.g. the Linpack
benchmark, might easily exceed the chip's heat/power budget if run at full clock
rate.  In those cases, voltages, clock rates, and clock duty cycle
will be used to control heat and power, even on top-end systems.

In order for time-like performance measures to make sense, some mechanism
is going to be needed to record the "performance state" of the machine
in the profiles.   Note that there are multiple mechanisms on each
processor to control this stuff.  Example -- Pentiums have Speedstep to
control voltage and frequency.  In addition, the IA32_CLOCK_MODULATION MSR
is available to operating systems to implement a power management strategy
by controling the duty cycle of the clock in steps of 12.5%.  The presence
of this feature is why cycles are measured in nonhalted_clockticks.

Regardless of the ultimate scheme for reporting time, transitions
in performance state will be valuable performance metrics in themselves
and should be profileable.


-- 
Rob Fowler