[openwince-cvs-commit] brux/src/arm cpu.c,1.3,1.4

[Marcel T. <te...@us...>]

Update of /cvsroot/openwince/brux/src/arm
In directory usw-pr-cvs1:/tmp/cvs-serv436

Modified Files:
	cpu.c 
Log Message:
Added support for C0 stepping of the PXA2x0 processors.


Index: cpu.c
===================================================================
RCS file: /cvsroot/openwince/brux/src/arm/cpu.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- cpu.c	4 Jul 2002 19:34:47 -0000	1.3
+++ cpu.c	18 Jul 2002 22:02:49 -0000	1.4
@@ -32,6 +32,8 @@
  *     Specification Update", December 2001, Order Number: 278259-023
  * [5] Intel Corporation, "SA-110 Microprocessor Technical Reference
  *     Manual", December 2000, Order Number: 278058-002
+ * [6] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
+ *     Specification Update", May 2002, Order Number: 278534-005
  *
  */
 
@@ -100,22 +102,24 @@
 	}
 
 	/* PXA250 and PXA210 */
-	if ((main_id & 0xFFFFF7D0) == 0x69052100) {
+	if ((main_id & 0xFFFFF3D0) == 0x69052100) {
 		if (main_id & bit(5))
 			puts( "(intel) Intel PXA210 Application Processor detected.\n" );
 		else
 			puts( "(intel) Intel PXA250 Application Processor detected.\n" );
 
-		/* test valid ARM ID - see tables 2-3 and 2-4 in [2] */
+		/* test valid ARM ID - see tables 2-3 and 2-4 in [2] and D55. in [6] */
 		switch (main_id) {
 			/* PXA250 */
 			case 0x69052100:
 			case 0x69052101:
 			case 0x69052902:
 			case 0x69052903:
+			case 0x69052D05:
 			/* PXA210 */
 			case 0x69052922:
 			case 0x69052923:
+			case 0x69052D25:
 				break;
 			default:
 				puts( "(pxa2x0) unknown/invalid ARM ID (Warning!).\n" );
@@ -126,11 +130,18 @@
 		puts( "(pxa2x0) Core Generation: Intel XScale Core.\n" );
 
 		puts( "(pxa2x0) Core Revision: " );
-		if (main_id & bit(11))
-			puts( "Third" );
-		else
-			puts( "First" );
-		puts( " version of the core.\n" );
+		switch ((main_id >> 10) & 0x7) {
+			case 0x0:
+				puts( "First version of the core.\n" );
+				break;
+			case 0x2:
+				puts( "Third version of the core.\n" );
+				break;
+			default:
+				puts( "unknown (Warning!).\n" );
+				halt();
+				break;
+		}
 
 		puts( "(pxa2x0) Stepping: " );
 		switch (main_id & 0xF) {
@@ -145,6 +156,9 @@
 				break;
 			case 0x3:
 				puts( "B1.\n" );
+				break;
+			case 0x5:		/* see D54. in [6] */
+				puts( "C0.\n" );
 				break;
 			default:
 				puts( "unknown (Warning!).\n" );