I implement Zynq HyBrid Design on my zynq board, but use "Axi Ethernet + Axi Dma" to instead of "openMAC", so i do not know how to trigger the #61 interruption (from openMAC to zynq ),can you help me sir?
Last edit: liu zhi qiang 2018-08-20
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The "interrupt" pin in the Axi Ethernet IP core can be used instead of the "timer_pulse_irq" pin in the Axi Openmac IP core. Kindly replace the same and try building the hardware.
If you face any issue during the hardware build, please provide us with the console log so that we can assist you better.
Thanks,
Powerlink-Team-Kalycito
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Hello Powerlink-team Kalycito ,
thanks for your kindly reply.
I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 interruption in "ARM0 (PS7)" occurs so frequently that all other programs are blocked seemingly.
so i wonder when does the #61 interruption in the ARM0 core ought to occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks
liu zhi qiang 8/25/2018
Last edit: liu zhi qiang 2018-08-25
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Hello Powerlink-team Kalycito ,
I implement Zynq HyBrid Design on my zynq board, but use "Axi Ethernet + Axi Dma" to instead of "openMAC", so i do not know how to trigger the #61 interruption (from openMAC to zynq ),can you help me sir?
Last edit: liu zhi qiang 2018-08-20
system.bd
the wire was linked as this diagram in system.bd
Last edit: liu zhi qiang 2018-08-20
make corrections:
not #61 but #91 (XPAR_FABRIC_AXI_OPENMAC_0_TIMER_PULSE_IRQ_INTR)
Last edit: liu zhi qiang 2018-08-21
Hi Liu zhi qiang,
The "interrupt" pin in the Axi Ethernet IP core can be used instead of the "timer_pulse_irq" pin in the Axi Openmac IP core. Kindly replace the same and try building the hardware.
If you face any issue during the hardware build, please provide us with the console log so that we can assist you better.
Thanks,
Powerlink-Team-Kalycito
Hello Powerlink-team Kalycito ,
thanks for your kindly reply.
I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 interruption in "ARM0 (PS7)" occurs so frequently that all other programs are blocked seemingly.
so i wonder when does the #61 interruption in the ARM0 core ought to occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks
liu zhi qiang 8/25/2018
Last edit: liu zhi qiang 2018-08-25