liu zhi qiang - 2018-07-12

hi Powerlink-Team-Kalycito,

In Zynq Hybrid design, demo_mn_console (USER SPACE of STACK) run on arm cpu,and PCP (KERNEL of STACK) run on Microblaze, and exchange the DATA (.i.e network package,NMT command) through the SHARED MEMORY.

I notice that they exchange the data via the F2P interrupt from PL to PS(the codes are below),could you please a little amply tell me what timestamp the interruption occurs in the per POWERLINK CYCLE (see the attachment picture )? SoC?PReq?PRes?SoA?ASnd?

thanks
liu zhi qiang

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E:\oplk-v2.6.2\contrib\dualprocshm\src\dualprocshm-intr.c

//------------------------------------------------------------------------------
/**
\brief Master Interrupt Handler

This is the master interrupt handler which is called by the system
if the IRQ signal is asserted by the PCP.
It is used to handle multiple interrupt sources with a single interrupt line.
This handler acknowledges the processed interrupt and calls the corresponding
callbacks registered with dualprocshm_registerHandler().

\param[in] pArg_p Driver instance passed during initialization.
/
//------------------------------------------------------------------------------
static void targetInterruptHandler(void
pArg_p)
{
UINT16 pendings;
UINT16 mask;
INT i;

UNUSED_PARAMETER(pArg_p);

if (intrInst_l.pIntrReg == NULL)
    return;

DUALPROCSHM_INVALIDATE_DCACHE_RANGE(&intrInst_l.pIntrReg->irq.irqPending,
                                    sizeof(intrInst_l.pIntrReg->irq.irqPending));
pendings = DPSHM_READ16(&intrInst_l.pIntrReg->irq.irqPending);

for (i = 0; i < TARGET_MAX_INTERRUPTS; i++)
{
    mask = 1 << i;

    // ack IRQ source first
    if (pendings & mask)
    {
        pendings &= ~mask;
        DPSHM_WRITE16(&intrInst_l.pIntrReg->irq.irqAck, pendings);
        DUALPROCSHM_FLUSH_DCACHE_RANGE(&intrInst_l.pIntrReg->irq.irqAck,
                                       sizeof(intrInst_l.pIntrReg->irq.irqAck));
    }

    // then try to execute the callback
    if (intrInst_l.apfnIrqCb[i] != NULL)
        intrInst_l.apfnIrqCb[i]();
}

}

 

Last edit: liu zhi qiang 2018-07-12