Thread: [OpenOCD-user] flash write error : timed out while waiting for target halted

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Hi
I'm using the jlink of segger with my stm32f103.Host is ubuntu 12.04.
Here is what I have done.So long....

   1. I download the JLink_Linux from segger web site.
   setup the jlink.

   feng@feng:~/fun/JLink_Linux_V441g$ JLinkExe
>    SEGGER J-Link Commander V4.41g ('?' for help)
>    Compiled Jan 27 2012 19:11:22
>    Updating firmware:  J-Link ARM V8 compiled Jan 12 2012 20:43:19
>    Replacing firmware: J-Link ARM V8 compiled JAN 12 2012 20:43:19
>    Waiting for new firmware to boot
>    New firmware booted successfully
>    DLL version V4.41g, compiled Jan 27 2012 19:11:21
>    Firmware: J-Link ARM V8 compiled Jan 12 2012 20:43:19
>    Hardware: V8.00
>    S/N: 20100214
>    Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull
>    VTarget = 3.293V
>    Info: TotalIRLen = 9, IRPrint = 0x0011
>    Info: Found Cortex-M3 r1p1, Little endian.
>    Info: TPIU fitted.
>    Info:   FPUnit: 6 code (BP) slots and 2 literal slots
>    Found 2 JTAG devices, Total IRLen = 9:
>     #0 Id: 0x3BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
>     #1 Id: 0x16410041, IRLen: 05, IRPrint: 0x1, STM32 Boundary Scan
>    Cortex-M3 identified.
>    JTAG speed: 100 kHz
>    J-Link>exec invalidateFw
>    Info: Updating firmware:  J-Link ARM V8 compiled JAN 12 2012 20:43:19
>    Info: Replacing firmware: J-Link ARM V8 compiled Jan 12 2012 20:43:19
>    Info: Waiting for new firmware to boot
>    Info: New firmware booted successfully
>
   2.  get the openocd-0.5.0

>    feng@feng:~/fun/openocd-0.5.0$ export LDFLAGS=lusb
>    feng@feng:~/fun/openocd-0.5.0$ ./configure --enable-ft2232_libftdi
>    --enable-maintainer-mode --enable-arm-jtag-ew
>
   3. openocd.cfg file

>    feng@feng:~$ cat openocd.cfg
>    #daemon configuration
>    telnet_port 4444
>    gdb_port 3333
>
>    #
>    ## Segger J-Link
>    #
>    ## http://www.segger.com/jlink.html
>    #
>    #
>    #
>    interface jlink
>
>    # script for stm32
>
>    if { [info exists CHIPNAME] } {
>       set  _CHIPNAME $CHIPNAME
>    } else {
>       set  _CHIPNAME stm32
>    }
>
>    if { [info exists ENDIAN] } {
>       set  _ENDIAN $ENDIAN
>    } else {
>       set  _ENDIAN little
>    }
>
>    # Work-area is a space in RAM used for flash programming
>    # By default use 16kB
>    if { [info exists WORKAREASIZE] } {
>       set  _WORKAREASIZE $WORKAREASIZE
>    } else {
>       set  _WORKAREASIZE 0x4000
>    }
>
>    # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use
>    F_JTAG = 1MHz
>    adapter_khz 1000
>
>    adapter_nsrst_delay 100
>    jtag_ntrst_delay 100
>
>    #jtag scan chain
>    if { [info exists CPUTAPID ] } {
>       set _CPUTAPID $CPUTAPID
>    } else {
>      # See STM Document RM0008
>      # Section 26.6.3
>       set _CPUTAPID 0x3ba00477
>    }
>    jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
>    -expected-id $_CPUTAPID
>
>    if { [info exists BSTAPID ] } {
>       # FIXME this never gets used to override defaults...
>       set _BSTAPID $BSTAPID
>    } else {
>      # See STM Document RM0008
>      # Section 29.6.2
>      # Low density devices, Rev A
>      set _BSTAPID1 0x06412041
>      # Medium density devices, Rev A
>      set _BSTAPID2 0x06410041
>      # Medium density devices, Rev B and Rev Z
>      set _BSTAPID3 0x16410041
>      set _BSTAPID4 0x06420041
>      # High density devices, Rev A
>      set _BSTAPID5 0x06414041
>      # Connectivity line devices, Rev A and Rev Z
>      set _BSTAPID6 0x06418041
>      # XL line devices, Rev A
>      set _BSTAPID7 0x06430041
>    }
>    jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
>        -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
>        -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
>        -expected-id $_BSTAPID6 -expected-id $_BSTAPID7
>
>    set _TARGETNAME $_CHIPNAME.cpu
>    target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
>    $_TARGETNAME
>
>    $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
>    $_WORKAREASIZE -work-area-backup 0
>
>    # flash size will be probed
>    set _FLASHNAME $_CHIPNAME.flash
>    flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
>
>    # if srst is not fitted use SYSRESETREQ to
>    # perform a soft reset
>    cortex_m3 reset_config sysresetreq
>
   4.  start the openocd

>    feng@feng:~$ sudo openocd -f openocd.cfg
>    [sudo] password for feng:
>    Open On-Chip Debugger 0.5.0 (2012-06-16-17:34)
>    Licensed under GNU GPL v2
>    For bug reports, read
>        http://openocd.berlios.de/doc/doxygen/bugs.html
>    Warn : Adapter driver 'jlink' did not declare which transports it
>    allows; assuming legacy JTAG-only
>    Info : only one transport option; autoselect 'jtag'
>    1000 kHz
>    adapter_nsrst_delay: 100
>    jtag_ntrst_delay: 100
>    cortex_m3 reset_config sysresetreq
>    Info : J-Link initialization started / target CPU reset initiated
>    Info : J-Link ARM V8 compiled JAN 12 2012 20:43:19
>    Info : J-Link caps 0xb9ff7bbf
>    Info : J-Link hw version 80000
>    Info : J-Link hw type J-Link
>    Info : J-Link max mem block 9440
>    Info : J-Link configuration
>    Info : USB-Address: 0x0
>    Info : Kickstart power on JTAG-pin 19: 0xffffffff
>    Info : Vref = 3.293 TCK = 1 TDI = 0 TDO = 1 TMS = 0 SRST = 0 TRST = 0
>    Info : J-Link JTAG Interface ready
>    Info : clock speed 1000 kHz
>    Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b,
>    part: 0xba00, ver: 0x3)
>    Info : JTAG tap: stm32.bs tap/device found: 0x16410041 (mfg: 0x020,
>    part: 0x6410, ver: 0x1)
>    Info : stm32.cpu: hardware has 6 breakpoints, 4 watchpoints
>
   5.  using ocd with telnet

>    feng@feng:~/fun/afrodevices-read-only/baseflight/obj$ telnet localhost
>    4444Trying 127.0.0.1...
>    Connected to localhost.
>    Escape character is '^]'.
>    Open On-Chip Debugger
>    > reset halt
>    JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part:
>    0xba00, ver: 0x3)
>    JTAG tap: stm32.bs tap/device found: 0x16410041 (mfg: 0x020, part:
>    0x6410, ver: 0x1)
>    target state: halted
>    target halted due to debug-request, current mode: Thread
>    xPSR: 0x01000000 pc: 0x1ffff020 msp: 0x200001fc
>    > flash probe 0
>    device id = 0x20036410
>    flash size = 64kbytes
>    device id = 0x20036410
>    flash size = 64kbytes
>    flash 'stm32f1x' found at 0x08000000
>    > stm32f1x unlock 0
>    stm32x unlocked.
>    INFO: a reset or power cycle is required for the new settings to take
>    effect.
>    > reset
>    halt
>
>    JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part:
>    0xba00, ver: 0x3)
>    JTAG tap: stm32.bs tap/device found: 0x16410041 (mfg: 0x020, part:
>    0x6410, ver: 0x1)
>    target state: halted
>    target halted due to debug-request, current mode: Thread
>    xPSR: 0x01000000 pc: 0x1ffff020 msp: 0x200001fc
>
   > stm32f1x mass_erase 0
>    stm32x mass erase complete
>    > flash erase_check 0
>    successfully checked erase state
>        #  0: 0x00000000 (0x400 1kB) erased
>        #  1: 0x00000400 (0x400 1kB) erased
>        #  2: 0x00000800 (0x400 1kB) erased
>              ............
>        # 62: 0x0000f800 (0x400 1kB) erased
>        # 63: 0x0000fc00 (0x400 1kB) erased
>    > flash write_bank 0
>    /home/feng/fun/afrodevices-read-only/baseflight/obj/baseflight.hex  0
>    *timed out* while waiting for target halted
>    error executing stm32x flash write algorithm
>    error writing to flash at address 0x08000000 at offset 0x00000000
>    in procedure 'flash'
>

At least ,I get the TIMED OUT error.
The text is so long...Thank you for reading.

-- 

DY.Feng(叶毅锋)
yyfeng88625@twitter
Department of Applied Mathematics
Guangzhou University,China
dy...@st...

Thread: [OpenOCD-user] flash write error : timed out while waiting for target halted

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