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From: Tommy M. <tom...@ho...> - 2024-08-09 12:20:29
|
Any use? https://community.nxp.com/t5/MCX-Microcontrollers/MCF54418CMJ250/td-p/1924429 |
|
From: Arun K. <aru...@gm...> - 2024-08-09 10:34:49
|
I have a Netburner device NANO54415 which uses MCF54418CMJ250 Coldfire microcontroller. I need to recover the firmware from the device as I don't have the source code for flashing to other devices https://www.netburner.com/products/system-on-modules/nano54415-ethernet-system-on-module/ Is there a way to recover the firmware for flashing to other devices. Can we use OpenOCD or some other utility tool to recover the firmware from the Netburner? Regards, Arun Kannan |
|
From: Liviu I. <il...@li...> - 2024-08-02 22:48:20
|
https://xpack-dev-tools.github.io/openocd-xpack/blog/2024/08/02/openocd-v0-12-0-4-released/ |
|
From: Liviu I. <il...@li...> - 2024-07-22 20:52:44
|
Hi! I recently reworked the web site for the xPack OpenOCD project: - https://xpack-dev-tools.github.io/openocd-xpack/ I would appreciate any feedback on the site. Is the content in the Install pages usable for regular developers? Is the content of the Getting Started of any use? Do you have any suggestions/critics/etc? Did reading these pages raise any questions for you? If so, please share these questions in order to improve the pages to answer/avoid these questions. Thank you in advance, Liviu |
|
From: Josef W. <jw...@ra...> - 2024-07-18 16:42:37
|
Hello all,
First hit on breakpoint gives:
Breakpoint 4, my_printf (format=Error: JTAG-DP STICKY ERROR
Error: Failed to read memory at 0xa5a5a5a6
0xa5a5a5a5 "") at app/my-stdlib.c:249
second hit on breakpoint works as expected. (Please see below for a more
verbose transcript)
I am using
- stm32f429bit6
- Amontec key
- binutils-2.42
- gcc-14.1.0
- gdb-15.1
- current HEAD of master of openocd (7f2d3e2925833c952ee73fb178c8fdee637c844e)
- this openocd-config:
source [find interface/ftdi/jtagkey.cfg]
telnet_port 4444
gdb_port pipe
gdb_memory_map enable
gdb_flash_program enable
source [find target/stm32f4x.cfg]
init
reset halt
(gdb) mon reset halt
Info : JTAG tap: stm32f4x.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
Info : JTAG tap: stm32f4x.bs tap/device found: 0x06419041 (mfg: 0x020 (STMicroelectronics), part: 0x6419, ver: 0x0)
JTAG tap: stm32f4x.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4)
JTAG tap: stm32f4x.bs tap/device found: 0x06419041 (mfg: 0x020 (STMicroelectronics), part: 0x6419, ver: 0x0)
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08039f5c msp: 0x20030000
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08039f5c msp: 0x20030000
(gdb) cont
Continuing.
Breakpoint 4, my_printf (format=Error: JTAG-DP STICKY ERROR
Error: Failed to read memory at 0xa5a5a5a6
0xa5a5a5a5 "") at app/my-stdlib.c:249
249 {
(gdb) i r
r0 0x805dac8 134601416
r1 0x805ca18 134597144
r2 0x10000000 268435456
r3 0xa5a5a5a5 -1515870811
r4 0xa5a5a5a5 -1515870811
r5 0xa5a5a5a5 -1515870811
r6 0xa5a5a5a5 -1515870811
r7 0xa5a5a5a5 -1515870811
r8 0xa5a5a5a5 -1515870811
r9 0xa5a5a5a5 -1515870811
r10 0xa5a5a5a5 -1515870811
r11 0xa5a5a5a5 -1515870811
r12 0xa5a5a5a5 -1515870811
sp 0x20016ee0 0x20016ee0 <ucHeap+10412>
lr 0x8005f19 134242073
pc 0x800c2e8 0x800c2e8 <my_printf>
xPSR 0x61000000 1627389952
fpscr 0x0 0
msp 0x2002ffe0 0x2002ffe0
psp 0x20016ee0 0x20016ee0 <ucHeap+10412>
primask 0x0 0
basepri 0x0 0
faultmask 0x0 0
control 0x2 2
(gdb) disass
Dump of assembler code for function my_printf:
=> 0x0800c2e8 <+0>: push {r0, r1, r2, r3}
0x0800c2ea <+2>: push {r4, r5, lr}
0x0800c2ec <+4>: sub sp, #268 @ 0x10c
0x0800c2ee <+6>: bl 0x8006238 <is_tamper>
0x0800c2f2 <+10>: cbz r0, 0x800c320 <my_printf+56>
0x0800c2f4 <+12>: bl 0x80086b4 <get_irq_mask>
0x0800c2f8 <+16>: cbnz r0, 0x800c32a <my_printf+66>
0x0800c2fa <+18>: add r2, sp, #284 @ 0x11c
0x0800c2fc <+20>: str r2, [sp, #4]
0x0800c2fe <+22>: add r5, sp, #8
0x0800c300 <+24>: ldr r1, [sp, #280] @ 0x118
0x0800c302 <+26>: mov r0, r5
0x0800c304 <+28>: bl 0x800bfa0 <simple_vsprintf>
0x0800c308 <+32>: mov r4, r0
0x0800c30a <+34>: movs r2, #1
0x0800c30c <+36>: mov r1, r0
0x0800c30e <+38>: mov r0, r5
0x0800c310 <+40>: bl 0x8000928 <ser_write>
0x0800c314 <+44>: mov r0, r4
0x0800c316 <+46>: add sp, #268 @ 0x10c
0x0800c318 <+48>: ldmia.w sp!, {r4, r5, lr}
0x0800c31c <+52>: add sp, #16
0x0800c31e <+54>: bx lr
0x0800c320 <+56>: mov r4, r0
0x0800c322 <+58>: movs r0, #1
0x0800c324 <+60>: bl 0x80009f4 <ser_flush>
0x0800c328 <+64>: b.n 0x800c314 <my_printf+44>
0x0800c32a <+66>: ldr r0, [pc, #4] @ (0x800c330 <my_printf+72>)
0x0800c32c <+68>: bl 0x800c25c <haltme>
0x0800c330 <+72>: eor.w r8, r8, #8716288 @ 0x850000
End of assembler dump.
(gdb) cont
Continuing.
Breakpoint 4, my_printf (format=0x805dac8 "\r\n\r\nit1010 %s command interpreter started\r\n") at app/my-stdlib.c:249
249 {
(gdb)
Any ideas?
--
Josef Wolf
jw...@ra...
|
|
From: Bob M <bo...@el...> - 2024-07-10 07:30:43
|
On 03/07/2024 12:44, Tommy Murphy wrote: > First thing to do in such situations is to capture and upload/post a > verbose `openocd -d3` log for the problem scenario and that may shed > some light on what's happening and why single stepping results in simply > resuming execution. Sorry for the delay in response; I only get a chance once a week to play with this stuff. Output of `-d3` below. The `halt` is issued on line 411 and `step` issued on line 521. Open On-Chip Debugger 0.12.0+dev-01638-g23c33e1d3 (2024-07-03-08:34) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html User : 3 1 options.c:52 configuration_output_handler(): debug_level: 3User : 4 1 options.c:52 configuration_output_handler(): Debug: 5 1 options.c:346 parse_cmdline_args(): ARGV[0] = "openocd/build/src/openocd" Debug: 6 1 options.c:346 parse_cmdline_args(): ARGV[1] = "-f" Debug: 7 1 options.c:346 parse_cmdline_args(): ARGV[2] = "config/interface/ft2232h.cfg" Debug: 8 1 options.c:346 parse_cmdline_args(): ARGV[3] = "-f" Debug: 9 1 options.c:346 parse_cmdline_args(): ARGV[4] = "config/board/rpi2.cfg" Debug: 10 1 options.c:346 parse_cmdline_args(): ARGV[5] = "-d3" Debug: 11 1 options.c:233 add_default_dirs(): bindir=/usr/local/bin Debug: 12 1 options.c:234 add_default_dirs(): pkgdatadir=/usr/local/share/openocd Debug: 13 1 options.c:235 add_default_dirs(): exepath=/home/bob/projects/openocd-raspberry-pi-2b/openocd/build/src Debug: 14 1 options.c:236 add_default_dirs(): bin2data=../share/openocd Debug: 15 1 configuration.c:33 add_script_search_dir(): adding /home/bob/.config/openocd Debug: 16 1 configuration.c:33 add_script_search_dir(): adding /home/bob/.openocd Debug: 17 1 configuration.c:33 add_script_search_dir(): adding /home/bob/projects/openocd-raspberry-pi-2b/openocd/build/src/../share/openocd/site Debug: 18 1 configuration.c:33 add_script_search_dir(): adding /home/bob/projects/openocd-raspberry-pi-2b/openocd/build/src/../share/openocd/scripts Debug: 19 1 command.c:153 script_debug(): command - ocd_find config/interface/ft2232h.cfg Debug: 20 1 configuration.c:88 find_file(): found config/interface/ft2232h.cfg Debug: 21 1 command.c:153 script_debug(): command - adapter driver ftdi Debug: 22 1 command.c:153 script_debug(): command - ftdi vid_pid 0x0403 0x6010 Debug: 23 1 command.c:153 script_debug(): command - echo DEPRECATED! use 'ftdi channel' not 'ftdi_channel' User : 24 1 command.c:678 handle_echo(): DEPRECATED! use 'ftdi channel' not 'ftdi_channel' Debug: 25 1 command.c:153 script_debug(): command - ftdi channel 0 Debug: 26 1 command.c:153 script_debug(): command - ftdi layout_init 0x0008 0x000b Debug: 27 1 command.c:153 script_debug(): command - ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 Debug: 28 1 command.c:153 script_debug(): command - ocd_find config/board/rpi2.cfg Debug: 29 1 configuration.c:88 find_file(): found config/board/rpi2.cfg Debug: 30 1 command.c:153 script_debug(): command - ocd_find config/target/bcm2836.cfg Debug: 31 1 configuration.c:88 find_file(): found config/target/bcm2836.cfg Debug: 32 1 command.c:153 script_debug(): command - transport select Info : 33 1 transport.c:267 handle_transport_select(): auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. Debug: 34 1 command.c:153 script_debug(): command - transport select Debug: 35 1 command.c:153 script_debug(): command - jtag newtap bcm2836 cpu -expected-id 0x4ba00477 -irlen 4 Debug: 36 1 tcl.c:401 handle_jtag_newtap_args(): Creating New Tap, Chip: bcm2836, Tap: cpu, Dotted: bcm2836.cpu, 4 params Debug: 37 1 core.c:1474 jtag_tap_init(): Created Tap: bcm2836.cpu @ abs position 0, irlen 4, capture: 0x1 mask: 0x3 Debug: 38 1 command.c:153 script_debug(): command - adapter speed 4000 Debug: 39 1 adapter.c:250 adapter_config_khz(): handle adapter khz Debug: 40 1 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 41 1 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 42 1 command.c:153 script_debug(): command - dap create bcm2836.dap -chain-position bcm2836.cpu Debug: 43 1 command.c:153 script_debug(): command - target create bcm2836.ap mem_ap -dap bcm2836.dap -ap-num 0 Debug: 44 1 command.c:153 script_debug(): command - target create bcm2836.cpu0 cortex_a -dap bcm2836.dap -coreid 0 -dbgbase 0x80010000 Debug: 45 1 command.c:153 script_debug(): command - bcm2836.cpu0 configure -event reset-assert-post cortex_a dbginit Debug: 46 1 command.c:153 script_debug(): command - target create bcm2836.cpu1 cortex_a -dap bcm2836.dap -coreid 1 -dbgbase 0x80012000 Debug: 47 1 command.c:259 register_command(): command 'arm' is already registered Debug: 48 1 command.c:259 register_command(): command 'arm reg' is already registered Debug: 49 1 command.c:259 register_command(): command 'arm mcr' is already registered Debug: 50 1 command.c:259 register_command(): command 'arm mrc' is already registered Debug: 51 1 command.c:259 register_command(): command 'arm mcrr' is already registered Debug: 52 1 command.c:259 register_command(): command 'arm mrrc' is already registered Debug: 53 1 command.c:259 register_command(): command 'arm core_state' is already registered Debug: 54 1 command.c:259 register_command(): command 'arm disassemble' is already registered Debug: 55 1 command.c:259 register_command(): command 'arm semihosting' is already registered Debug: 56 1 command.c:259 register_command(): command 'arm semihosting_redirect' is already registered Debug: 57 1 command.c:259 register_command(): command 'arm semihosting_cmdline' is already registered Debug: 58 1 command.c:259 register_command(): command 'arm semihosting_fileio' is already registered Debug: 59 1 command.c:259 register_command(): command 'arm semihosting_resexit' is already registered Debug: 60 1 command.c:259 register_command(): command 'arm semihosting_read_user_param' is already registered Debug: 61 1 command.c:259 register_command(): command 'arm semihosting_basedir' is already registered Debug: 62 1 command.c:259 register_command(): command 'cache_config' is already registered Debug: 63 1 command.c:259 register_command(): command 'cache_config l2x' is already registered Debug: 64 1 command.c:259 register_command(): command 'cache' is already registered Debug: 65 1 command.c:259 register_command(): command 'cache l1' is already registered Debug: 66 1 command.c:259 register_command(): command 'cache l1 info' is already registered Debug: 67 1 command.c:259 register_command(): command 'cache l1 d' is already registered Debug: 68 1 command.c:259 register_command(): command 'cache l1 d flush_all' is already registered Debug: 69 1 command.c:259 register_command(): command 'cache l1 d inval' is already registered Debug: 70 1 command.c:259 register_command(): command 'cache l1 d clean' is already registered Debug: 71 1 command.c:259 register_command(): command 'cache l1 i' is already registered Debug: 72 1 command.c:259 register_command(): command 'cache l1 i inval_all' is already registered Debug: 73 1 command.c:259 register_command(): command 'cache l1 i inval' is already registered Debug: 74 1 command.c:259 register_command(): command 'cache l2x' is already registered Debug: 75 1 command.c:259 register_command(): command 'cache l2x conf' is already registered Debug: 76 1 command.c:259 register_command(): command 'cache l2x info' is already registered Debug: 77 1 command.c:259 register_command(): command 'cache l2x flush_all' is already registered Debug: 78 1 command.c:259 register_command(): command 'cache l2x flush' is already registered Debug: 79 1 command.c:259 register_command(): command 'cache l2x inval' is already registered Debug: 80 1 command.c:259 register_command(): command 'cache l2x clean' is already registered Debug: 81 1 command.c:259 register_command(): command 'cortex_a' is already registered Debug: 82 1 command.c:259 register_command(): command 'cortex_a cache_info' is already registered Debug: 83 1 command.c:259 register_command(): command 'cortex_a dbginit' is already registered Debug: 84 1 command.c:259 register_command(): command 'cortex_a maskisr' is already registered Debug: 85 1 command.c:259 register_command(): command 'cortex_a dacrfixup' is already registered Debug: 86 1 command.c:259 register_command(): command 'cortex_a mmu' is already registered Debug: 87 1 command.c:259 register_command(): command 'cortex_a mmu dump' is already registered Debug: 88 1 command.c:259 register_command(): command 'cortex_a smp' is already registered Debug: 89 1 command.c:259 register_command(): command 'cortex_a smp_gdb' is already registered Debug: 90 1 command.c:153 script_debug(): command - bcm2836.cpu1 configure -event reset-assert-post cortex_a dbginit Debug: 91 1 command.c:153 script_debug(): command - target create bcm2836.cpu2 cortex_a -dap bcm2836.dap -coreid 2 -dbgbase 0x80014000 Debug: 92 1 command.c:259 register_command(): command 'arm' is already registered Debug: 93 1 command.c:259 register_command(): command 'arm reg' is already registered Debug: 94 1 command.c:259 register_command(): command 'arm mcr' is already registered Debug: 95 1 command.c:259 register_command(): command 'arm mrc' is already registered Debug: 96 1 command.c:259 register_command(): command 'arm mcrr' is already registered Debug: 97 1 command.c:259 register_command(): command 'arm mrrc' is already registered Debug: 98 1 command.c:259 register_command(): command 'arm core_state' is already registered Debug: 99 1 command.c:259 register_command(): command 'arm disassemble' is already registered Debug: 100 1 command.c:259 register_command(): command 'arm semihosting' is already registered Debug: 101 1 command.c:259 register_command(): command 'arm semihosting_redirect' is already registered Debug: 102 1 command.c:259 register_command(): command 'arm semihosting_cmdline' is already registered Debug: 103 1 command.c:259 register_command(): command 'arm semihosting_fileio' is already registered Debug: 104 1 command.c:259 register_command(): command 'arm semihosting_resexit' is already registered Debug: 105 1 command.c:259 register_command(): command 'arm semihosting_read_user_param' is already registered Debug: 106 1 command.c:259 register_command(): command 'arm semihosting_basedir' is already registered Debug: 107 1 command.c:259 register_command(): command 'cache_config' is already registered Debug: 108 1 command.c:259 register_command(): command 'cache_config l2x' is already registered Debug: 109 1 command.c:259 register_command(): command 'cache' is already registered Debug: 110 1 command.c:259 register_command(): command 'cache l1' is already registered Debug: 111 1 command.c:259 register_command(): command 'cache l1 info' is already registered Debug: 112 1 command.c:259 register_command(): command 'cache l1 d' is already registered Debug: 113 1 command.c:259 register_command(): command 'cache l1 d flush_all' is already registered Debug: 114 1 command.c:259 register_command(): command 'cache l1 d inval' is already registered Debug: 115 1 command.c:259 register_command(): command 'cache l1 d clean' is already registered Debug: 116 1 command.c:259 register_command(): command 'cache l1 i' is already registered Debug: 117 1 command.c:259 register_command(): command 'cache l1 i inval_all' is already registered Debug: 118 1 command.c:259 register_command(): command 'cache l1 i inval' is already registered Debug: 119 1 command.c:259 register_command(): command 'cache l2x' is already registered Debug: 120 1 command.c:259 register_command(): command 'cache l2x conf' is already registered Debug: 121 1 command.c:259 register_command(): command 'cache l2x info' is already registered Debug: 122 1 command.c:259 register_command(): command 'cache l2x flush_all' is already registered Debug: 123 1 command.c:259 register_command(): command 'cache l2x flush' is already registered Debug: 124 1 command.c:259 register_command(): command 'cache l2x inval' is already registered Debug: 125 1 command.c:259 register_command(): command 'cache l2x clean' is already registered Debug: 126 1 command.c:259 register_command(): command 'cortex_a' is already registered Debug: 127 1 command.c:259 register_command(): command 'cortex_a cache_info' is already registered Debug: 128 1 command.c:259 register_command(): command 'cortex_a dbginit' is already registered Debug: 129 1 command.c:259 register_command(): command 'cortex_a maskisr' is already registered Debug: 130 1 command.c:259 register_command(): command 'cortex_a dacrfixup' is already registered Debug: 131 1 command.c:259 register_command(): command 'cortex_a mmu' is already registered Debug: 132 1 command.c:259 register_command(): command 'cortex_a mmu dump' is already registered Debug: 133 1 command.c:259 register_command(): command 'cortex_a smp' is already registered Debug: 134 1 command.c:259 register_command(): command 'cortex_a smp_gdb' is already registered Debug: 135 1 command.c:153 script_debug(): command - bcm2836.cpu2 configure -event reset-assert-post cortex_a dbginit Debug: 136 1 command.c:153 script_debug(): command - target create bcm2836.cpu3 cortex_a -dap bcm2836.dap -coreid 3 -dbgbase 0x80016000 Debug: 137 1 command.c:259 register_command(): command 'arm' is already registered Debug: 138 1 command.c:259 register_command(): command 'arm reg' is already registered Debug: 139 1 command.c:259 register_command(): command 'arm mcr' is already registered Debug: 140 1 command.c:259 register_command(): command 'arm mrc' is already registered Debug: 141 1 command.c:259 register_command(): command 'arm mcrr' is already registered Debug: 142 1 command.c:259 register_command(): command 'arm mrrc' is already registered Debug: 143 1 command.c:259 register_command(): command 'arm core_state' is already registered Debug: 144 1 command.c:259 register_command(): command 'arm disassemble' is already registered Debug: 145 1 command.c:259 register_command(): command 'arm semihosting' is already registered Debug: 146 1 command.c:259 register_command(): command 'arm semihosting_redirect' is already registered Debug: 147 1 command.c:259 register_command(): command 'arm semihosting_cmdline' is already registered Debug: 148 1 command.c:259 register_command(): command 'arm semihosting_fileio' is already registered Debug: 149 1 command.c:259 register_command(): command 'arm semihosting_resexit' is already registered Debug: 150 1 command.c:259 register_command(): command 'arm semihosting_read_user_param' is already registered Debug: 151 1 command.c:259 register_command(): command 'arm semihosting_basedir' is already registered Debug: 152 1 command.c:259 register_command(): command 'cache_config' is already registered Debug: 153 1 command.c:259 register_command(): command 'cache_config l2x' is already registered Debug: 154 1 command.c:259 register_command(): command 'cache' is already registered Debug: 155 1 command.c:259 register_command(): command 'cache l1' is already registered Debug: 156 1 command.c:259 register_command(): command 'cache l1 info' is already registered Debug: 157 1 command.c:259 register_command(): command 'cache l1 d' is already registered Debug: 158 1 command.c:259 register_command(): command 'cache l1 d flush_all' is already registered Debug: 159 1 command.c:259 register_command(): command 'cache l1 d inval' is already registered Debug: 160 1 command.c:259 register_command(): command 'cache l1 d clean' is already registered Debug: 161 1 command.c:259 register_command(): command 'cache l1 i' is already registered Debug: 162 1 command.c:259 register_command(): command 'cache l1 i inval_all' is already registered Debug: 163 1 command.c:259 register_command(): command 'cache l1 i inval' is already registered Debug: 164 1 command.c:259 register_command(): command 'cache l2x' is already registered Debug: 165 1 command.c:259 register_command(): command 'cache l2x conf' is already registered Debug: 166 1 command.c:259 register_command(): command 'cache l2x info' is already registered Debug: 167 1 command.c:259 register_command(): command 'cache l2x flush_all' is already registered Debug: 168 1 command.c:259 register_command(): command 'cache l2x flush' is already registered Debug: 169 1 command.c:259 register_command(): command 'cache l2x inval' is already registered Debug: 170 1 command.c:259 register_command(): command 'cache l2x clean' is already registered Debug: 171 1 command.c:259 register_command(): command 'cortex_a' is already registered Debug: 172 1 command.c:259 register_command(): command 'cortex_a cache_info' is already registered Debug: 173 1 command.c:259 register_command(): command 'cortex_a dbginit' is already registered Debug: 174 1 command.c:259 register_command(): command 'cortex_a maskisr' is already registered Debug: 175 1 command.c:259 register_command(): command 'cortex_a dacrfixup' is already registered Debug: 176 1 command.c:259 register_command(): command 'cortex_a mmu' is already registered Debug: 177 1 command.c:259 register_command(): command 'cortex_a mmu dump' is already registered Debug: 178 1 command.c:259 register_command(): command 'cortex_a smp' is already registered Debug: 179 1 command.c:259 register_command(): command 'cortex_a smp_gdb' is already registered Debug: 180 1 command.c:153 script_debug(): command - bcm2836.cpu3 configure -event reset-assert-post cortex_a dbginit Debug: 181 1 command.c:153 script_debug(): command - targets bcm2836.cpu0 Debug: 182 1 command.c:153 script_debug(): command - transport select jtag Warn : 183 1 transport.c:280 handle_transport_select(): Transport "jtag" was already selected Debug: 184 1 command.c:153 script_debug(): command - reset_config trst_only User : 185 1 options.c:52 configuration_output_handler(): trst_only separate trst_push_pullUser : 186 1 options.c:52 configuration_output_handler(): Info : 187 1 server.c:298 add_service(): Listening on port 6666 for tcl connections Info : 188 1 server.c:298 add_service(): Listening on port 4444 for telnet connections Debug: 189 1 command.c:153 script_debug(): command - init Debug: 190 1 command.c:153 script_debug(): command - target init Debug: 191 1 command.c:153 script_debug(): command - target names Debug: 192 2 command.c:153 script_debug(): command - bcm2836.ap cget -event gdb-flash-erase-start Debug: 193 2 command.c:153 script_debug(): command - bcm2836.ap configure -event gdb-flash-erase-start reset init Debug: 194 2 command.c:153 script_debug(): command - bcm2836.ap cget -event gdb-flash-write-end Debug: 195 2 command.c:153 script_debug(): command - bcm2836.ap configure -event gdb-flash-write-end reset halt Debug: 196 2 command.c:153 script_debug(): command - bcm2836.ap cget -event gdb-attach Debug: 197 2 command.c:153 script_debug(): command - bcm2836.ap configure -event gdb-attach halt 1000 Debug: 198 2 command.c:153 script_debug(): command - bcm2836.cpu0 cget -event gdb-flash-erase-start Debug: 199 2 command.c:153 script_debug(): command - bcm2836.cpu0 configure -event gdb-flash-erase-start reset init Debug: 200 2 command.c:153 script_debug(): command - bcm2836.cpu0 cget -event gdb-flash-write-end Debug: 201 2 command.c:153 script_debug(): command - bcm2836.cpu0 configure -event gdb-flash-write-end reset halt Debug: 202 2 command.c:153 script_debug(): command - bcm2836.cpu0 cget -event gdb-attach Debug: 203 2 command.c:153 script_debug(): command - bcm2836.cpu0 configure -event gdb-attach halt 1000 Debug: 204 2 command.c:153 script_debug(): command - bcm2836.cpu1 cget -event gdb-flash-erase-start Debug: 205 2 command.c:153 script_debug(): command - bcm2836.cpu1 configure -event gdb-flash-erase-start reset init Debug: 206 2 command.c:153 script_debug(): command - bcm2836.cpu1 cget -event gdb-flash-write-end Debug: 207 2 command.c:153 script_debug(): command - bcm2836.cpu1 configure -event gdb-flash-write-end reset halt Debug: 208 2 command.c:153 script_debug(): command - bcm2836.cpu1 cget -event gdb-attach Debug: 209 2 command.c:153 script_debug(): command - bcm2836.cpu1 configure -event gdb-attach halt 1000 Debug: 210 2 command.c:153 script_debug(): command - bcm2836.cpu2 cget -event gdb-flash-erase-start Debug: 211 2 command.c:153 script_debug(): command - bcm2836.cpu2 configure -event gdb-flash-erase-start reset init Debug: 212 2 command.c:153 script_debug(): command - bcm2836.cpu2 cget -event gdb-flash-write-end Debug: 213 2 command.c:153 script_debug(): command - bcm2836.cpu2 configure -event gdb-flash-write-end reset halt Debug: 214 2 command.c:153 script_debug(): command - bcm2836.cpu2 cget -event gdb-attach Debug: 215 2 command.c:153 script_debug(): command - bcm2836.cpu2 configure -event gdb-attach halt 1000 Debug: 216 2 command.c:153 script_debug(): command - bcm2836.cpu3 cget -event gdb-flash-erase-start Debug: 217 2 command.c:153 script_debug(): command - bcm2836.cpu3 configure -event gdb-flash-erase-start reset init Debug: 218 2 command.c:153 script_debug(): command - bcm2836.cpu3 cget -event gdb-flash-write-end Debug: 219 2 command.c:153 script_debug(): command - bcm2836.cpu3 configure -event gdb-flash-write-end reset halt Debug: 220 2 command.c:153 script_debug(): command - bcm2836.cpu3 cget -event gdb-attach Debug: 221 2 command.c:153 script_debug(): command - bcm2836.cpu3 configure -event gdb-attach halt 1000 Debug: 222 2 target.c:1588 handle_target_init_command(): Initializing targets... Debug: 223 2 mem_ap.c:61 mem_ap_init_target(): mem_ap_init_target Debug: 224 2 semihosting_common.c:107 semihosting_common_init(): Debug: 225 2 semihosting_common.c:107 semihosting_common_init(): Debug: 226 2 semihosting_common.c:107 semihosting_common_init(): Debug: 227 2 semihosting_common.c:107 semihosting_common_init(): Debug: 228 2 ftdi.c:655 ftdi_initialize(): ftdi interface using shortest path jtag state transitions Debug: 229 12 mpsse.c:424 mpsse_purge(): - Debug: 230 16 mpsse.c:705 mpsse_loopback_config(): off Debug: 231 16 mpsse.c:750 mpsse_set_frequency(): target 4000000 Hz Debug: 232 16 mpsse.c:742 mpsse_rtck_config(): off Debug: 233 16 mpsse.c:731 mpsse_divide_by_5_config(): off Debug: 234 16 mpsse.c:711 mpsse_set_divisor(): 7 Debug: 235 16 mpsse.c:774 mpsse_set_frequency(): actually 3750000 Hz Debug: 236 16 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 237 16 adapter.c:218 adapter_khz_to_speed(): have adapter set up Debug: 238 16 mpsse.c:750 mpsse_set_frequency(): target 4000000 Hz Debug: 239 16 mpsse.c:742 mpsse_rtck_config(): off Debug: 240 16 mpsse.c:731 mpsse_divide_by_5_config(): off Debug: 241 16 mpsse.c:711 mpsse_set_divisor(): 7 Debug: 242 16 mpsse.c:774 mpsse_set_frequency(): actually 3750000 Hz Debug: 243 16 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value Debug: 244 16 adapter.c:218 adapter_khz_to_speed(): have adapter set up Info : 245 16 adapter.c:178 adapter_init(): clock speed 4000 kHz Debug: 246 16 openocd.c:133 handle_init_command(): Debug Adapter init complete Debug: 247 16 command.c:153 script_debug(): command - transport init Debug: 248 16 transport.c:219 handle_transport_init(): handle_transport_init Debug: 249 16 core.c:830 jtag_add_reset(): SRST line released Debug: 250 16 core.c:855 jtag_add_reset(): TRST line released Debug: 251 16 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 252 16 command.c:153 script_debug(): command - jtag arp_init Debug: 253 16 core.c:1509 jtag_init_inner(): Init JTAG chain Debug: 254 16 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 255 16 core.c:1234 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS Debug: 256 16 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset Info : 257 17 core.c:1133 jtag_examine_chain_display(): JTAG tap: bcm2836.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) Debug: 258 17 core.c:1364 jtag_validate_ircapture(): IR capture validation scan Debug: 259 17 core.c:1421 jtag_validate_ircapture(): bcm2836.cpu: IR capture 0x01 Debug: 260 17 command.c:153 script_debug(): command - dap init Debug: 261 17 arm_dap.c:96 dap_init_all(): Initializing all DAPs ... Debug: 262 17 arm_dap.c:120 dap_init_all(): DAP bcm2836.cpu configured by default to use ADIv5 protocol Debug: 263 17 arm_adi_v5.c:783 dap_dp_init(): bcm2836.dap Debug: 264 17 arm_adi_v5.c:815 dap_dp_init(): DAP: wait CDBGPWRUPACK Debug: 265 17 arm_adi_v5.h:682 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000 Debug: 266 17 arm_adi_v5.c:823 dap_dp_init(): DAP: wait CSYSPWRUPACK Debug: 267 17 arm_adi_v5.h:682 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000 Debug: 268 17 openocd.c:150 handle_init_command(): Examining targets... Debug: 269 17 target.c:674 target_examine_one(): [bcm2836.ap] Examination started Debug: 270 17 target.c:1774 target_call_event_callbacks(): target event 19 (examine-start) for core bcm2836.ap Debug: 271 17 arm_adi_v5.c:1192 dap_get_ap(): refcount AP#0x0 get 1 Debug: 272 17 arm_adi_v5.c:933 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0 Debug: 273 17 target.c:1774 target_call_event_callbacks(): target event 21 (examine-end) for core bcm2836.ap Info : 274 17 target.c:690 target_examine_one(): [bcm2836.ap] Examination succeed Debug: 275 17 target.c:674 target_examine_one(): [bcm2836.cpu0] Examination started Debug: 276 17 target.c:1774 target_call_event_callbacks(): target event 19 (examine-start) for core bcm2836.cpu0 Debug: 277 17 arm_adi_v5.c:1192 dap_get_ap(): refcount AP#0x0 get 2 Debug: 278 18 arm_adi_v5.c:1135 dap_find_get_ap(): Found MEM-AP APB2 or APB3 at AP index: 0 (IDR=0x24770002) Debug: 279 18 arm_adi_v5.c:933 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0 Debug: 280 18 cortex_a.c:2962 cortex_a_examine_first(): didr = 0x3515f005 Debug: 281 18 cortex_a.c:2963 cortex_a_examine_first(): cpuid = 0x410fc075 Debug: 282 19 cortex_a.c:2972 cortex_a_examine_first(): [bcm2836.cpu0] DBGPRSR 0x2b Debug: 283 19 cortex_a.c:2981 cortex_a_examine_first(): [bcm2836.cpu0] was reset! Debug: 284 19 cortex_a.c:2988 cortex_a_examine_first(): [bcm2836.cpu0] DBGOSLSR 0xa Debug: 285 19 cortex_a.c:2994 cortex_a_examine_first(): [bcm2836.cpu0] OSLock set! Trying to unlock Debug: 286 19 cortex_a.c:3018 cortex_a_examine_first(): [bcm2836.cpu0] has security extensions Debug: 287 19 cortex_a.c:3022 cortex_a_examine_first(): [bcm2836.cpu0] has virtualization extensions Info : 288 19 arm_dpm.c:1148 arm_dpm_setup(): bcm2836.cpu0: hardware has 6 breakpoints, 4 watchpoints Debug: 289 19 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80010140 Debug: 290 19 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80010144 Debug: 291 20 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80010148 Debug: 292 20 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 8001014c Debug: 293 20 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80010150 Debug: 294 20 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80010154 Debug: 295 20 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800101c0 Debug: 296 21 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800101c4 Debug: 297 21 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800101c8 Debug: 298 21 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800101cc Debug: 299 21 cortex_a.c:3055 cortex_a_examine_first(): Configured 6 hw breakpoints Debug: 300 21 cortex_a.c:3069 cortex_a_examine_first(): Configured 4 hw watchpoints Debug: 301 22 target.c:1774 target_call_event_callbacks(): target event 21 (examine-end) for core bcm2836.cpu0 Info : 302 22 target.c:690 target_examine_one(): [bcm2836.cpu0] Examination succeed Debug: 303 22 target.c:674 target_examine_one(): [bcm2836.cpu1] Examination started Debug: 304 22 target.c:1774 target_call_event_callbacks(): target event 19 (examine-start) for core bcm2836.cpu1 Debug: 305 22 arm_adi_v5.c:1192 dap_get_ap(): refcount AP#0x0 get 3 Debug: 306 22 arm_adi_v5.c:1135 dap_find_get_ap(): Found MEM-AP APB2 or APB3 at AP index: 0 (IDR=0x24770002) Debug: 307 22 arm_adi_v5.c:933 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0 Debug: 308 23 cortex_a.c:2962 cortex_a_examine_first(): didr = 0x3515f005 Debug: 309 23 cortex_a.c:2963 cortex_a_examine_first(): cpuid = 0x410fc075 Debug: 310 23 cortex_a.c:2972 cortex_a_examine_first(): [bcm2836.cpu1] DBGPRSR 0x2b Debug: 311 23 cortex_a.c:2981 cortex_a_examine_first(): [bcm2836.cpu1] was reset! Debug: 312 23 cortex_a.c:2988 cortex_a_examine_first(): [bcm2836.cpu1] DBGOSLSR 0xa Debug: 313 23 cortex_a.c:2994 cortex_a_examine_first(): [bcm2836.cpu1] OSLock set! Trying to unlock Debug: 314 24 cortex_a.c:3018 cortex_a_examine_first(): [bcm2836.cpu1] has security extensions Debug: 315 24 cortex_a.c:3022 cortex_a_examine_first(): [bcm2836.cpu1] has virtualization extensions Info : 316 24 arm_dpm.c:1148 arm_dpm_setup(): bcm2836.cpu1: hardware has 6 breakpoints, 4 watchpoints Debug: 317 24 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80012140 Debug: 318 24 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80012144 Debug: 319 24 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80012148 Debug: 320 24 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 8001214c Debug: 321 25 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80012150 Debug: 322 25 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80012154 Debug: 323 25 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800121c0 Debug: 324 25 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800121c4 Debug: 325 25 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800121c8 Debug: 326 25 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800121cc Debug: 327 26 cortex_a.c:3055 cortex_a_examine_first(): Configured 6 hw breakpoints Debug: 328 26 cortex_a.c:3069 cortex_a_examine_first(): Configured 4 hw watchpoints Debug: 329 27 target.c:1774 target_call_event_callbacks(): target event 21 (examine-end) for core bcm2836.cpu1 Info : 330 27 target.c:690 target_examine_one(): [bcm2836.cpu1] Examination succeed Debug: 331 27 target.c:674 target_examine_one(): [bcm2836.cpu2] Examination started Debug: 332 27 target.c:1774 target_call_event_callbacks(): target event 19 (examine-start) for core bcm2836.cpu2 Debug: 333 27 arm_adi_v5.c:1192 dap_get_ap(): refcount AP#0x0 get 4 Debug: 334 27 arm_adi_v5.c:1135 dap_find_get_ap(): Found MEM-AP APB2 or APB3 at AP index: 0 (IDR=0x24770002) Debug: 335 27 arm_adi_v5.c:933 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0 Debug: 336 27 cortex_a.c:2962 cortex_a_examine_first(): didr = 0x3515f005 Debug: 337 27 cortex_a.c:2963 cortex_a_examine_first(): cpuid = 0x410fc075 Debug: 338 28 cortex_a.c:2972 cortex_a_examine_first(): [bcm2836.cpu2] DBGPRSR 0x2b Debug: 339 28 cortex_a.c:2981 cortex_a_examine_first(): [bcm2836.cpu2] was reset! Debug: 340 28 cortex_a.c:2988 cortex_a_examine_first(): [bcm2836.cpu2] DBGOSLSR 0xa Debug: 341 28 cortex_a.c:2994 cortex_a_examine_first(): [bcm2836.cpu2] OSLock set! Trying to unlock Debug: 342 28 cortex_a.c:3018 cortex_a_examine_first(): [bcm2836.cpu2] has security extensions Debug: 343 28 cortex_a.c:3022 cortex_a_examine_first(): [bcm2836.cpu2] has virtualization extensions Info : 344 28 arm_dpm.c:1148 arm_dpm_setup(): bcm2836.cpu2: hardware has 6 breakpoints, 4 watchpoints Debug: 345 28 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80014140 Debug: 346 29 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80014144 Debug: 347 29 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80014148 Debug: 348 29 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 8001414c Debug: 349 29 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80014150 Debug: 350 29 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80014154 Debug: 351 30 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800141c0 Debug: 352 30 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800141c4 Debug: 353 30 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800141c8 Debug: 354 30 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800141cc Debug: 355 30 cortex_a.c:3055 cortex_a_examine_first(): Configured 6 hw breakpoints Debug: 356 30 cortex_a.c:3069 cortex_a_examine_first(): Configured 4 hw watchpoints Debug: 357 31 target.c:1774 target_call_event_callbacks(): target event 21 (examine-end) for core bcm2836.cpu2 Info : 358 31 target.c:690 target_examine_one(): [bcm2836.cpu2] Examination succeed Debug: 359 31 target.c:674 target_examine_one(): [bcm2836.cpu3] Examination started Debug: 360 31 target.c:1774 target_call_event_callbacks(): target event 19 (examine-start) for core bcm2836.cpu3 Debug: 361 31 arm_adi_v5.c:1192 dap_get_ap(): refcount AP#0x0 get 5 Debug: 362 31 arm_adi_v5.c:1135 dap_find_get_ap(): Found MEM-AP APB2 or APB3 at AP index: 0 (IDR=0x24770002) Debug: 363 32 arm_adi_v5.c:933 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0 Debug: 364 32 cortex_a.c:2962 cortex_a_examine_first(): didr = 0x3515f005 Debug: 365 32 cortex_a.c:2963 cortex_a_examine_first(): cpuid = 0x410fc075 Debug: 366 32 cortex_a.c:2972 cortex_a_examine_first(): [bcm2836.cpu3] DBGPRSR 0x2b Debug: 367 32 cortex_a.c:2981 cortex_a_examine_first(): [bcm2836.cpu3] was reset! Debug: 368 33 cortex_a.c:2988 cortex_a_examine_first(): [bcm2836.cpu3] DBGOSLSR 0xa Debug: 369 33 cortex_a.c:2994 cortex_a_examine_first(): [bcm2836.cpu3] OSLock set! Trying to unlock Debug: 370 33 cortex_a.c:3018 cortex_a_examine_first(): [bcm2836.cpu3] has security extensions Debug: 371 33 cortex_a.c:3022 cortex_a_examine_first(): [bcm2836.cpu3] has virtualization extensions Info : 372 33 arm_dpm.c:1148 arm_dpm_setup(): bcm2836.cpu3: hardware has 6 breakpoints, 4 watchpoints Debug: 373 33 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80016140 Debug: 374 33 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80016144 Debug: 375 33 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80016148 Debug: 376 34 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 8001614c Debug: 377 34 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80016150 Debug: 378 34 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 80016154 Debug: 379 34 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800161c0 Debug: 380 34 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800161c4 Debug: 381 35 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800161c8 Debug: 382 35 cortex_a.c:628 cortex_a_bpwp_disable(): A: bpwp disable, cr 800161cc Debug: 383 35 cortex_a.c:3055 cortex_a_examine_first(): Configured 6 hw breakpoints Debug: 384 35 cortex_a.c:3069 cortex_a_examine_first(): Configured 4 hw watchpoints Debug: 385 36 target.c:1774 target_call_event_callbacks(): target event 21 (examine-end) for core bcm2836.cpu3 Info : 386 36 target.c:690 target_examine_one(): [bcm2836.cpu3] Examination succeed Debug: 387 36 command.c:153 script_debug(): command - flash init Debug: 388 36 tcl.c:1364 handle_flash_init_command(): Initializing flash devices... Debug: 389 36 command.c:153 script_debug(): command - nand init Debug: 390 36 tcl.c:484 handle_nand_init_command(): Initializing NAND devices... Debug: 391 36 command.c:153 script_debug(): command - pld init Debug: 392 36 pld.c:337 handle_pld_init_command(): Initializing PLDs... Debug: 393 36 command.c:153 script_debug(): command - tpiu init Info : 394 36 gdb_server.c:3874 gdb_target_add_one(): [bcm2836.ap] gdb port disabled Info : 395 36 gdb_server.c:3840 gdb_target_start(): [bcm2836.cpu0] starting gdb server on 3333 Info : 396 36 server.c:298 add_service(): Listening on port 3333 for gdb connections Info : 397 36 gdb_server.c:3840 gdb_target_start(): [bcm2836.cpu1] starting gdb server on 3334 Info : 398 36 server.c:298 add_service(): Listening on port 3334 for gdb connections Info : 399 36 gdb_server.c:3840 gdb_target_start(): [bcm2836.cpu2] starting gdb server on 3335 Info : 400 36 server.c:298 add_service(): Listening on port 3335 for gdb connections Info : 401 36 gdb_server.c:3840 gdb_target_start(): [bcm2836.cpu3] starting gdb server on 3336 Info : 402 36 server.c:298 add_service(): Listening on port 3336 for gdb connections Debug: 403 36 command.c:153 script_debug(): command - target names Debug: 404 36 command.c:153 script_debug(): command - target names Debug: 405 36 command.c:153 script_debug(): command - bcm2836.ap cget -type Debug: 406 36 command.c:153 script_debug(): command - bcm2836.cpu0 cget -type Debug: 407 36 command.c:153 script_debug(): command - bcm2836.cpu1 cget -type Debug: 408 36 command.c:153 script_debug(): command - bcm2836.cpu2 cget -type Debug: 409 36 command.c:153 script_debug(): command - bcm2836.cpu3 cget -type Info : 410 51435 server.c:91 add_connection(): accepting 'telnet' connection on tcp/4444 Debug: 411 58818 command.c:153 script_debug(): command - halt Debug: 412 58818 target.c:3245 handle_halt_command(): - Debug: 413 58819 cortex_a.c:764 cortex_a_poll(): Target halted Debug: 414 58819 cortex_a.c:1031 cortex_a_debug_entry(): dscr = 0x030c4003 Debug: 415 58819 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 416 58820 arm_dpm.c:269 arm_dpm_read_reg(): READ: r0, 00000000 Debug: 417 58820 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee001e15 Debug: 418 58820 arm_dpm.c:269 arm_dpm_read_reg(): READ: r1, 00000c42 Debug: 419 58820 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe10f0000 Debug: 420 58820 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 421 58821 armv4_5.c:485 arm_set_cpsr(): set CPSR 0x000001da: Hypervisor mode, ARM state Debug: 422 58821 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee002e15 Debug: 423 58821 arm_dpm.c:269 arm_dpm_read_reg(): READ: r2, 2e0d4d00 Debug: 424 58821 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee003e15 Debug: 425 58821 arm_dpm.c:269 arm_dpm_read_reg(): READ: r3, 00008000 Debug: 426 58821 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee004e15 Debug: 427 58822 arm_dpm.c:269 arm_dpm_read_reg(): READ: r4, 1fb7daf4 Debug: 428 58822 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee005e15 Debug: 429 58822 arm_dpm.c:269 arm_dpm_read_reg(): READ: r5, 00000000 Debug: 430 58822 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee006e15 Debug: 431 58823 arm_dpm.c:269 arm_dpm_read_reg(): READ: r6, 00000000 Debug: 432 58823 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee007e15 Debug: 433 58823 arm_dpm.c:269 arm_dpm_read_reg(): READ: r7, 40000000 Debug: 434 58823 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee008e15 Debug: 435 58823 arm_dpm.c:269 arm_dpm_read_reg(): READ: r8, 7ef73ebd Debug: 436 58823 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee009e15 Debug: 437 58824 arm_dpm.c:269 arm_dpm_read_reg(): READ: r9, 4b4b3e54 Debug: 438 58824 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee00ae15 Debug: 439 58824 arm_dpm.c:269 arm_dpm_read_reg(): READ: r10, 3a6a637c Debug: 440 58824 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee00be15 Debug: 441 58824 arm_dpm.c:269 arm_dpm_read_reg(): READ: r11, ebe33d74 Debug: 442 58824 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee00ce15 Debug: 443 58825 arm_dpm.c:269 arm_dpm_read_reg(): READ: r12, 000001fa Debug: 444 58825 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee00de15 Debug: 445 58825 arm_dpm.c:269 arm_dpm_read_reg(): READ: sp_hyp, eb9a39df Debug: 446 58825 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee00ee15 Debug: 447 58826 arm_dpm.c:269 arm_dpm_read_reg(): READ: lr_usr, e241f8e7 Debug: 448 58826 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe1a0000f Debug: 449 58826 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 450 58826 arm_dpm.c:269 arm_dpm_read_reg(): READ: pc, 00008004 Debug: 451 58826 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe14f0000 Debug: 452 58826 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 453 58827 arm_dpm.c:269 arm_dpm_read_reg(): READ: spsr_hyp, 7a0efe5d Debug: 454 58827 arm_dpm.c:53 dpm_mrc(): MRC p15, 0, r0, c1, c0, 0 Debug: 455 58827 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee110f10 Debug: 456 58827 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 457 58827 cortex_a.c:1115 cortex_a_post_debug_entry(): cp15_control_reg: 00c50878 Debug: 458 58828 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee120f50 Debug: 459 58828 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 460 58828 armv7a.c:137 armv7a_read_ttbcr(): ttbcr 0 Debug: 461 58828 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee120f10 Debug: 462 58828 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 463 58829 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee120f30 Debug: 464 58829 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 465 58829 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100f10 Debug: 466 58830 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 467 58830 armv7a.c:104 armv7a_read_midr(): bcm2836.cpu0 rev 5, partnum c07, arch f, variant 0, implementor 41 Debug: 468 58830 armv7a.c:172 armv7a_read_ttbcr(): ttbr1 not used, ttbr0_mask ffffc000 ttbr1_mask ffffc000 Debug: 469 58830 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100f30 Debug: 470 58830 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 471 58831 armv7a.c:390 armv7a_identify_cache(): ctr 84448003 ctr.iminline 32 ctr.dminline 64 Debug: 472 58831 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee300f30 Debug: 473 58831 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 474 58831 armv7a.c:402 armv7a_identify_cache(): Number of cache levels to PoC 2 Debug: 475 58831 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee500f10 Debug: 476 58832 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 477 58832 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00000000 Debug: 478 58832 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 479 58832 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee400f10 Debug: 480 58832 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee300f10 Debug: 481 58833 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 482 58833 armv7a.c:430 armv7a_identify_cache(): data/unified cache index 127 << 6, way 3 << 30 Debug: 483 58833 armv7a.c:436 armv7a_identify_cache(): cacheline 64 bytes 32 KBytes asso 4 ways Debug: 484 58833 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00000001 Debug: 485 58833 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 486 58833 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee400f10 Debug: 487 58833 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee300f10 Debug: 488 58834 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 489 58834 armv7a.c:450 armv7a_identify_cache(): instruction cache index 511 << 5, way 1 << 31 Debug: 490 58834 armv7a.c:456 armv7a_identify_cache(): cacheline 32 bytes 32 KBytes asso 2 ways Debug: 491 58834 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00000002 Debug: 492 58834 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 493 58834 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee400f10 Debug: 494 58834 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee300f10 Debug: 495 58835 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 496 58835 armv7a.c:430 armv7a_identify_cache(): data/unified cache index 1023 << 6, way 7 << 29 Debug: 497 58835 armv7a.c:436 armv7a_identify_cache(): cacheline 64 bytes 512 KBytes asso 8 ways Debug: 498 58835 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00000000 Debug: 499 58835 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 500 58835 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee500f10 Debug: 501 58836 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100fb0 Debug: 502 58836 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 503 58836 armv7a.c:300 armv7a_read_mpidr(): bcm2836.cpu0: MPIDR 0x80000f00 Info : 504 58836 armv7a.c:306 armv7a_read_mpidr(): bcm2836.cpu0: MPIDR level2 0, cluster f, core 0, multi core, no SMT Debug: 505 58836 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00000013 Debug: 506 58836 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 507 58836 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe12ff000 Debug: 508 58837 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee070f95 Debug: 509 58837 arm_dpm.c:53 dpm_mrc(): MRC p15, 0, r0, c3, c0, 0 Debug: 510 58837 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee130f10 Debug: 511 58837 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee000e15 Debug: 512 58838 cortex_a.c:1142 cortex_a_post_debug_entry(): cp15_dacr_reg: 470f19c8 Debug: 513 58838 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x000001da Debug: 514 58838 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 515 58838 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe12ff000 Debug: 516 58838 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee070f95 Debug: 517 58838 target.c:1774 target_call_event_callbacks(): target event 0 (gdb-halt) for core bcm2836.cpu0 Debug: 518 58838 target.c:1774 target_call_event_callbacks(): target event 1 (halted) for core bcm2836.cpu0 User : 519 58838 armv4_5.c:795 arm_arch_state(): target halted in ARM state due to debug-request, current mode: Hypervisor cpsr: 0x000001da pc: 0x00008004 User : 520 58838 armv7a.c:552 armv7a_arch_state(): MMU: disabled, D-Cache: disabled, I-Cache: disabled Debug: 521 80962 command.c:153 script_debug(): command - step Debug: 522 80962 target.c:3322 handle_step_command(): - Debug: 523 80962 target.c:1774 target_call_event_callbacks(): target event 5 (step-start) for core bcm2836.cpu0 Debug: 524 80963 cortex_a.c:1323 cortex_a_set_breakpoint(): brp 0 control 0x4001e7 value 0x8004 Debug: 525 80963 target.c:2130 target_free_all_working_areas_restore(): freeing all working areas Debug: 526 80963 cortex_a.c:881 cortex_a_internal_restore(): resume pc = 0x00008004 Debug: 527 80963 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x000001da Debug: 528 80963 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 529 80963 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe12ff000 Debug: 530 80963 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee070f95 Debug: 531 80963 cortex_a.c:1268 cortex_a_restore_context(): Debug: 532 80964 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x000001da Debug: 533 80964 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 534 80964 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe12ff000 Debug: 535 80964 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee070f95 Debug: 536 80964 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00008004 Debug: 537 80964 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 538 80965 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe12fff10 Debug: 539 80965 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00008004 Debug: 540 80965 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 541 80965 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xe1a0f000 Debug: 542 80965 arm_dpm.c:354 dpm_write_reg(): WRITE: pc, 00008004 Debug: 543 80965 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00000000 Debug: 544 80965 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee100e15 Debug: 545 80965 arm_dpm.c:354 dpm_write_reg(): WRITE: r0, 00000000 Debug: 546 80965 cortex_a.c:335 cortex_a_write_dcc(): write DCC 0x00000c42 Debug: 547 80965 cortex_a.c:292 cortex_a_exec_opcode(): exec opcode 0xee101e15 Debug: 548 80966 arm_dpm.c:354 dpm_write_reg(): WRITE: r1, 00000c42 Debug: 549 80966 target.c:1774 target_call_event_callbacks(): target event 2 (resumed) for core bcm2836.cpu0 Debug: 550 80966 cortex_a.c:1013 cortex_a_resume(): target resumed at 0x00008004 Error: 551 81967 cortex_a.c:1238 cortex_a_step(): timeout waiting for target halt Debug: 552 81967 command.c:528 exec_command(): Command 'step' failed with error code -4 User : 553 81967 command.c:601 command_run_line(): Regards, Bob |
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From: Tommy M. <tom...@ho...> - 2024-07-03 11:44:43
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First thing to do in such situations is to capture and upload/post a verbose `openocd -d3` log for the problem scenario and that may shed some light on what's happening and why single stepping results in simply resuming execution. |
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From: Bob M <bo...@el...> - 2024-07-03 08:17:27
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I'm trying to perform single stepping on a Raspberry Pi 2, but it fails to single-step - it just runs on without stopping. The problem does not occur when I attempt to do exactly the same thing (albeit with different OCD config files) with a Raspberry Pi 3 using exactly the same kernel7.img, same build of OpenOCD. Open On-Chip Debugger > halt bcm2836.cpu0: MPIDR level2 0, cluster f, core 0, multi core, no SMT target halted in ARM state due to debug-request, current mode: Hypervisor cpsr: 0x000001da pc: 0x00008004 MMU: disabled, D-Cache: disabled, I-Cache: disabled > step timeout waiting for target halt > I've created a minimal repository at https://github.com/electricworry/openocd-raspberry-pi-2b which - through the short Makefile - shows exactly what I'm running and the OpenOCD config files I'm using. For the RPi3, I've taken the existing configs from the project - rpi3.cfg, minimodule.cfg (the FT2232H), and bcm2837.cfg. For the RPi2, there's no rpi2.cfg in the repo, so I've copied rpi3.cfg and modified it to import the bcm2836.cfg file which I think should be the right thing to do. I'm only a beginner user of openocd and JTAG so debugging this particular problem is beyond my current knowledge. But if anyone has any pointers about how to proceed with investigating the problem I would be happy to try, and if it gets resolved I'll submit a patch and config for the board. Alternatively, perhaps someone will tell me that the feature is broken on the RPi2 or that there's a simple fix that my scouring of mailing lists and forums has not turned up. Regards, Bob |
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From: Peter C. <pet...@ru...> - 2024-07-01 10:11:41
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Hello everybody, I have a long-winded TCL script going in OpenOCD that polls an address in memory, does things when the address contains a non-zero value, resets the value and keeps polling forever. It works fine. The problem is, as long as the TCL script is running, OpenOCD can't be stopped with SIGINT because apparently the TCL interpreter doesn't receive the signal. I have to kill -9 openocd. Is there a way to make the TCL script stop gracefully when OpenOCD is stopped normally? |
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From: Liviu I. <il...@li...> - 2024-06-20 09:13:01
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I did some further investigations, and in the end the board was recognised by openOCD. However something is weird, the board works only when connected to a USB3 port, and sometimes it fails the first attempt and requires a retry. I also installed the latest STM32CubeProgrammer and updated to the latest firmware (the on-board programmer is a STLINK-V3). The connection looks like this: ``` 1: Test command: /Users/ilg/MyProjects/micro-os-plus.github/micro-os-plus-iii/micro-os-plus-iii.git/tests/build/nucleo-h743zi-cmake-debug/xpacks/.bin/openocd "-c" "gdb_port disabled" "-c" "tcl_port disabled" "-c" "telnet_port disabled" "-f" "interface/stlink-dap.cfg" "-f" "target/stm32h7x.cfg" "-c" "program rtos-apis-test.elf verify" "-c" "arm semihosting enable" "-c" "arm semihosting_cmdline rtos-apis-test" "-c" "reset" 1: Working Directory: /Users/ilg/MyProjects/micro-os-plus.github/micro-os-plus-iii/micro-os-plus-iii.git/tests/build/nucleo-h743zi-cmake-debug/platform-bin 1: Test timeout computed to be: 10000000 1: xPack Open On-Chip Debugger 0.12.0+dev-01621-gd4607c225-dirty (2024-06-18-23:02) 1: Licensed under GNU GPL v2 1: For bug reports, read 1: http://openocd.org/doc/doxygen/bugs.html 1: Info : auto-selecting first available session transport "dapdirect_swd". To override use 'transport select <transport>'. 1: Info : STLINK V3J13M4 (API v3) VID:PID 0483:374E 1: Info : Target voltage: 3.284881 1: Info : Unable to match requested speed 1800 kHz, using 1000 kHz 1: Info : Unable to match requested speed 1800 kHz, using 1000 kHz 1: Info : clock speed 1000 kHz 1: Info : stlink_dap_op_connect(connect) 1: Info : SWD DPIDR 0x6ba02477 1: Info : [stm32h7x.ap2] Examination succeed 1: Info : [stm32h7x.cpu0] Cortex-M7 r1p1 processor detected 1: Warn : [stm32h7x.cpu0] Erratum 3092511: Cortex-M7 can halt in an incorrect address when breakpoint and exception occurs simultaneously 1: Info : [stm32h7x.cpu0] target has 8 breakpoints, 4 watchpoints 1: Info : [stm32h7x.cpu0] Examination succeed 1: Info : gdb port disabled 1: Info : gdb port disabled 1: [stm32h7x.cpu0] halted due to breakpoint, current mode: Thread 1: xPSR: 0x01000000 pc: 0x08000298 msp: 0x20020000 1: Info : Unable to match requested speed 4000 kHz, using 3300 kHz 1: Info : Unable to match requested speed 4000 kHz, using 3300 kHz 1: ** Programming Started ** 1: Info : Device: STM32H74x/75x 1: Info : flash size probed value 2048k 1: Info : STM32H7 flash has dual banks 1: Info : Bank (0) size is 1024 kb, base address is 0x08000000 1: Info : Padding image section 1 at 0x08051f54 with 12 bytes (bank write end alignment) 1: Warn : Adding extra erase range, 0x08051f60 .. 0x0805ffff 1: ** Programming Finished ** 1: ** Verify Started ** 1: ** Verified OK ** 1: semihosting is enabled 1: semihosting command line is [rtos-apis-test] 1: Info : tcl server disabled 1: Info : telnet server disabled 1: 1: Hardware initialised ... ``` |
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From: Liviu I. <il...@li...> - 2024-06-20 07:57:50
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> On 20 Jun 2024, at 10:13, Tommy Murphy <tom...@ho...> wrote: > > Might be worth posting a verbose `openocd -d3` log to see more detail about what's going on/wrong? sure: ``` 1: Test command: /Users/ilg/MyProjects/micro-os-plus.github/micro-os-plus-iii/micro-os-plus-iii.git/tests/build/nucleo-h743zi-cmake-debug/xpacks/.bin/openocd "-c" "gdb_port disabled" "-c" "tcl_port disabled" "-c" "telnet_port disabled" "-f" "interface/stlink-dap.cfg" "-f" "target/stm32h7x.cfg" "-d3" "-c" "program rtos-apis-test.elf verify" "-c" "arm semihosting enable" "-c" "arm semihosting_cmdline rtos-apis-test" "-c" "reset" 1: Working Directory: /Users/ilg/MyProjects/micro-os-plus.github/micro-os-plus-iii/micro-os-plus-iii.git/tests/build/nucleo-h743zi-cmake-debug/platform-bin 1: Test timeout computed to be: 10000000 1: xPack Open On-Chip Debugger 0.12.0+dev-01621-gd4607c225-dirty (2024-06-18-23:02) 1: Licensed under GNU GPL v2 1: For bug reports, read 1: http://openocd.org/doc/doxygen/bugs.html 1: User : 3 10 options.c:52 configuration_output_handler(): debug_level: 3User : 4 10 options.c:52 configuration_output_handler(): 1: Debug: 5 10 options.c:346 parse_cmdline_args(): ARGV[0] = "/Users/ilg/MyProjects/micro-os-plus.github/micro-os-plus-iii/micro-os-plus-iii.git/tests/build/nucleo-h743zi-cmake-debug/xpacks/.bin/openocd" 1: Debug: 6 10 options.c:346 parse_cmdline_args(): ARGV[1] = "-c" 1: Debug: 7 10 options.c:346 parse_cmdline_args(): ARGV[2] = "gdb_port disabled" 1: Debug: 8 10 options.c:346 parse_cmdline_args(): ARGV[3] = "-c" 1: Debug: 9 10 options.c:346 parse_cmdline_args(): ARGV[4] = "tcl_port disabled" 1: Debug: 10 10 options.c:346 parse_cmdline_args(): ARGV[5] = "-c" 1: Debug: 11 10 options.c:346 parse_cmdline_args(): ARGV[6] = "telnet_port disabled" 1: Debug: 12 10 options.c:346 parse_cmdline_args(): ARGV[7] = "-f" 1: Debug: 13 10 options.c:346 parse_cmdline_args(): ARGV[8] = "interface/stlink-dap.cfg" 1: Debug: 14 10 options.c:346 parse_cmdline_args(): ARGV[9] = "-f" 1: Debug: 15 10 options.c:346 parse_cmdline_args(): ARGV[10] = "target/stm32h7x.cfg" 1: Debug: 16 10 options.c:346 parse_cmdline_args(): ARGV[11] = "-d3" 1: Debug: 17 10 options.c:346 parse_cmdline_args(): ARGV[12] = "-c" 1: Debug: 18 10 options.c:346 parse_cmdline_args(): ARGV[13] = "program rtos-apis-test.elf verify" 1: Debug: 19 10 options.c:346 parse_cmdline_args(): ARGV[14] = "-c" 1: Debug: 20 10 options.c:346 parse_cmdline_args(): ARGV[15] = "arm semihosting enable" 1: Debug: 21 10 options.c:346 parse_cmdline_args(): ARGV[16] = "-c" 1: Debug: 22 10 options.c:346 parse_cmdline_args(): ARGV[17] = "arm semihosting_cmdline rtos-apis-test" 1: Debug: 23 10 options.c:346 parse_cmdline_args(): ARGV[18] = "-c" 1: Debug: 24 10 options.c:346 parse_cmdline_args(): ARGV[19] = "reset" 1: Debug: 25 10 options.c:233 add_default_dirs(): bindir=/Users/ilg/Work/xpack-dev-tools-build/openocd-0.12.0-4/darwin-x64/application/bin 1: Debug: 26 10 options.c:234 add_default_dirs(): pkgdatadir=/Users/ilg/Work/xpack-dev-tools-build/openocd-0.12.0-4/darwin-x64/application/openocd 1: Debug: 27 10 options.c:235 add_default_dirs(): exepath=/Users/ilg/Library/xPacks/@xpack-dev-tools/openocd/0.12.0-3.1/.content/bin 1: Debug: 28 10 options.c:236 add_default_dirs(): bin2data=../openocd 1: Debug: 29 10 configuration.c:33 add_script_search_dir(): adding /Users/ilg/Library/Preferences/org.openocd 1: Debug: 30 10 configuration.c:33 add_script_search_dir(): adding /Users/ilg/.config/openocd 1: Debug: 31 10 configuration.c:33 add_script_search_dir(): adding /Users/ilg/.openocd 1: Debug: 32 10 configuration.c:33 add_script_search_dir(): adding /Users/ilg/Library/xPacks/@xpack-dev-tools/openocd/0.12.0-3.1/.content/bin/../openocd/site 1: Debug: 33 10 configuration.c:33 add_script_search_dir(): adding /Users/ilg/Library/xPacks/@xpack-dev-tools/openocd/0.12.0-3.1/.content/bin/../openocd/scripts 1: Debug: 34 10 command.c:153 script_debug(): command - gdb_port disabled 1: Debug: 35 10 command.c:153 script_debug(): command - tcl_port disabled 1: Debug: 36 10 command.c:153 script_debug(): command - telnet_port disabled 1: Debug: 37 10 command.c:153 script_debug(): command - ocd_find interface/stlink-dap.cfg 1: Debug: 38 11 configuration.c:88 find_file(): found /Users/ilg/Library/xPacks/@xpack-dev-tools/openocd/0.12.0-3.1/.content/bin/../openocd/scripts/interface/stlink-dap.cfg 1: Debug: 39 11 command.c:153 script_debug(): command - adapter driver st-link 1: Debug: 40 11 command.c:153 script_debug(): command - st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 1: Debug: 41 12 command.c:153 script_debug(): command - ocd_find target/stm32h7x.cfg 1: Debug: 42 13 configuration.c:88 find_file(): found /Users/ilg/Library/xPacks/@xpack-dev-tools/openocd/0.12.0-3.1/.content/bin/../openocd/scripts/target/stm32h7x.cfg 1: Debug: 43 13 command.c:153 script_debug(): command - ocd_find target/swj-dp.tcl 1: Debug: 44 14 configuration.c:88 find_file(): found /Users/ilg/Library/xPacks/@xpack-dev-tools/openocd/0.12.0-3.1/.content/bin/../openocd/scripts/target/swj-dp.tcl 1: Debug: 45 14 command.c:153 script_debug(): command - transport select 1: Info : 46 14 transport.c:268 handle_transport_select(): auto-selecting first available session transport "dapdirect_swd". To override use 'transport select <transport>'. 1: Debug: 47 14 adi_v5_dapdirect.c:187 dapdirect_swd_select(): dapdirect_swd_select() 1: Debug: 48 14 command.c:153 script_debug(): command - ocd_find mem_helper.tcl 1: Debug: 49 14 configuration.c:88 find_file(): found /Users/ilg/Library/xPacks/@xpack-dev-tools/openocd/0.12.0-3.1/.content/bin/../openocd/scripts/mem_helper.tcl 1: Debug: 50 14 command.c:153 script_debug(): command - add_usage_text mrw address 1: Debug: 51 14 command.c:153 script_debug(): command - add_help_text mrw Returns value of word in memory. 1: Debug: 52 15 command.c:153 script_debug(): command - add_usage_text mrh address 1: Debug: 53 15 command.c:153 script_debug(): command - add_help_text mrh Returns value of halfword in memory. 1: Debug: 54 15 command.c:153 script_debug(): command - add_usage_text mrb address 1: Debug: 55 15 command.c:153 script_debug(): command - add_help_text mrb Returns value of byte in memory. 1: Debug: 56 15 command.c:153 script_debug(): command - add_usage_text mmw address setbits clearbits 1: Debug: 57 15 command.c:153 script_debug(): command - add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits; 1: Debug: 58 15 command.c:153 script_debug(): command - transport select 1: Debug: 59 15 command.c:153 script_debug(): command - transport select 1: Debug: 60 15 command.c:153 script_debug(): command - transport select 1: Debug: 61 15 command.c:153 script_debug(): command - swd newdap stm32h7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x6ba02477 1: Debug: 62 15 tcl.c:402 handle_jtag_newtap_args(): Creating New Tap, Chip: stm32h7x, Tap: cpu, Dotted: stm32h7x.cpu, 8 params 1: Debug: 63 15 core.c:1478 jtag_tap_init(): Created Tap: stm32h7x.cpu @ abs position 0, irlen 4, capture: 0x1 mask: 0xf 1: Debug: 64 15 command.c:153 script_debug(): command - dap create stm32h7x.dap -chain-position stm32h7x.cpu 1: Debug: 65 15 command.c:153 script_debug(): command - transport select 1: Debug: 66 15 command.c:153 script_debug(): command - transport select 1: Debug: 67 15 command.c:153 script_debug(): command - target create stm32h7x.ap2 mem_ap -dap stm32h7x.dap -ap-num 2 1: Debug: 68 15 command.c:153 script_debug(): command - swo create stm32h7x.swo -dap stm32h7x.dap -ap-num 2 -baseaddr 0xE00E3000 1: Debug: 69 15 command.c:153 script_debug(): command - tpiu create stm32h7x.tpiu -dap stm32h7x.dap -ap-num 2 -baseaddr 0xE00F5000 1: Debug: 70 16 command.c:153 script_debug(): command - target create stm32h7x.cpu0 cortex_m -endian little -dap stm32h7x.dap -ap-num 0 1: Debug: 71 16 command.c:259 register_command(): command 'tpiu' is already registered 1: Debug: 72 16 command.c:259 register_command(): command 'rtt' is already registered 1: Debug: 73 16 command.c:153 script_debug(): command - stm32h7x.cpu0 configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 1: Debug: 74 16 target.c:2130 target_free_all_working_areas_restore(): freeing all working areas 1: Debug: 75 16 target.c:2130 target_free_all_working_areas_restore(): freeing all working areas 1: Debug: 76 16 target.c:2130 target_free_all_working_areas_restore(): freeing all working areas 1: Debug: 77 16 command.c:153 script_debug(): command - flash bank stm32h7x.bank1.cpu0 stm32h7x 0x08000000 0 0 0 stm32h7x.cpu0 1: Debug: 78 17 tcl.c:1307 handle_flash_bank_command(): 'stm32h7x' driver usage field missing 1: Debug: 79 17 command.c:153 script_debug(): command - targets stm32h7x.cpu0 1: Debug: 80 17 command.c:153 script_debug(): command - adapter speed 1800 1: Debug: 81 17 adapter.c:250 adapter_config_khz(): handle adapter khz 1: Debug: 82 17 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value 1: Debug: 83 17 adapter.c:214 adapter_khz_to_speed(): convert khz to adapter specific speed value 1: Debug: 84 17 command.c:153 script_debug(): command - adapter srst delay 100 1: Debug: 85 17 command.c:153 script_debug(): command - transport select 1: Debug: 86 17 command.c:153 script_debug(): command - reset_config srst_nogate 1: Debug: 87 17 command.c:153 script_debug(): command - transport select 1: Debug: 88 17 command.c:153 script_debug(): command - stm32h7x.cpu0 cortex_m reset_config sysresetreq 1: Debug: 89 17 command.c:153 script_debug(): command - stm32h7x.dap apcsw 0x08000000 0x08000000 1: Debug: 90 17 arm_adi_v5.c:1202 dap_get_config_ap(): refcount AP#0x0 get_config 1 1: Debug: 91 17 arm_adi_v5.c:1217 dap_put_ap(): refcount AP#0x0 put 0 1: Debug: 92 17 command.c:153 script_debug(): command - stm32h7x.cpu0 configure -event examine-end 1: # Enable D3 and D1 DBG clocks 1: # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN 1: stm32h7x_dbgmcu_mmw 0x004 0x00600000 0 1: 1: # Enable debug during low power modes (uses more power) 1: # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain 1: stm32h7x_dbgmcu_mmw 0x004 0x00000007 0 1: # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain 1: stm32h7x_dbgmcu_mmw 0x004 0x00000038 0 1: 1: # Stop watchdog counters during halt 1: # DBGMCU_APB3FZ1 |= WWDG1 1: stm32h7x_dbgmcu_mmw 0x034 0x00000040 0 1: # DBGMCU_APB1LFZ1 |= WWDG2 1: stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0 1: # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2 1: stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0 1: 1: # Enable clock for tracing 1: # DBGMCU_CR |= TRACECLKEN 1: stm32h7x_dbgmcu_mmw 0x004 0x00100000 0 1: 1: # RM0399 (id 0x450) M7+M4 with SWO Funnel 1: # RM0433 (id 0x450) M7 with SWO Funnel 1: # RM0455 (id 0x480) M7 without SWO Funnel 1: # RM0468 (id 0x483) M7 without SWO Funnel 1: # Enable CM7 and CM4 slave ports in SWO trace Funnel 1: # Works ok also on devices single core and without SWO funnel 1: # Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF 1: # SWTF_CTRL |= ENS0 | ENS1 1: stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0 1: 1: Debug: 93 18 command.c:153 script_debug(): command - stm32h7x.cpu0 configure -event reset-init 1: # Clock after reset is HSI at 64 MHz, no need of PLL 1: adapter speed 4000 1: 1: Debug: 94 18 command.c:153 script_debug(): command - init 1: Debug: 95 18 command.c:153 script_debug(): command - target init 1: Debug: 96 18 command.c:153 script_debug(): command - target names 1: Debug: 97 18 command.c:153 script_debug(): command - stm32h7x.ap2 cget -event gdb-flash-erase-start 1: Debug: 98 18 command.c:153 script_debug(): command - stm32h7x.ap2 configure -event gdb-flash-erase-start reset init 1: Debug: 99 18 command.c:153 script_debug(): command - stm32h7x.ap2 cget -event gdb-flash-write-end 1: Debug: 100 18 command.c:153 script_debug(): command - stm32h7x.ap2 configure -event gdb-flash-write-end reset halt 1: Debug: 101 18 command.c:153 script_debug(): command - stm32h7x.ap2 cget -event gdb-attach 1: Debug: 102 18 command.c:153 script_debug(): command - stm32h7x.ap2 configure -event gdb-attach halt 1000 1: Debug: 103 18 command.c:153 script_debug(): command - stm32h7x.cpu0 cget -event gdb-flash-erase-start 1: Debug: 104 18 command.c:153 script_debug(): command - stm32h7x.cpu0 configure -event gdb-flash-erase-start reset init 1: Debug: 105 18 command.c:153 script_debug(): command - stm32h7x.cpu0 cget -event gdb-flash-write-end 1: Debug: 106 18 command.c:153 script_debug(): command - stm32h7x.cpu0 configure -event gdb-flash-write-end reset halt 1: Debug: 107 18 command.c:153 script_debug(): command - stm32h7x.cpu0 cget -event gdb-attach 1: Debug: 108 18 command.c:153 script_debug(): command - stm32h7x.cpu0 configure -event gdb-attach halt 1000 1: Debug: 109 18 target.c:1588 handle_target_init_command(): Initializing targets... 1: Debug: 110 18 mem_ap.c:61 mem_ap_init_target(): mem_ap_init_target 1: Debug: 111 18 semihosting_common.c:107 semihosting_common_init(): 1: Debug: 112 18 stlink_usb.c:5120 stlink_dap_init(): stlink_dap_init() 1: Debug: 113 18 stlink_usb.c:3732 stlink_open(): stlink_open 1: Debug: 114 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3744 serial: 1: Debug: 115 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3748 serial: 1: Debug: 116 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374b serial: 1: Debug: 117 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374d serial: 1: Debug: 118 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374e serial: 1: Debug: 119 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374f serial: 1: Debug: 120 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3752 serial: 1: Debug: 121 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3753 serial: 1: Debug: 122 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3754 serial: 1: Debug: 123 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3755 serial: 1: Debug: 124 18 stlink_usb.c:3746 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3757 serial: 1: Debug: 125 44 stlink_usb.c:686 jtag_libusb_bulk_transfer_n(): ERROR, failed to submit transfer 0, error -5 1: Debug: 126 1362 stlink_usb.c:686 jtag_libusb_bulk_transfer_n(): ERROR, failed to submit transfer 0, error -5 1: Error: 127 1362 stlink_usb.c:3470 stlink_usb_usb_open(): read version failed 1: Debug: 128 1362 stlink_usb.c:686 jtag_libusb_bulk_transfer_n(): ERROR, failed to submit transfer 0, error -5 1: Debug: 129 1365 command.c:529 exec_command(): Command 'init' failed with error code -4 1: Debug: 130 1365 command.c:153 script_debug(): command - echo ** OpenOCD init failed ** 1: Debug: 131 1365 log.c:412 gdb_timeout_warning(): keep_alive() was not invoked in the 1000 ms timelimit (1365 ms). This may cause trouble with GDB connections. 1: User : 132 1365 command.c:678 handle_echo(): ** OpenOCD init failed ** 1: Debug: 133 1365 command.c:153 script_debug(): command - shutdown error 1: User : 134 1365 server.c:760 handle_shutdown_command(): shutdown command invoked 1: Debug: 135 1365 command.c:529 exec_command(): Command 'shutdown' failed with error code -4 1: User : 136 1365 command.c:601 command_run_line(): 1: Debug: 137 1366 breakpoints.c:328 breakpoint_remove_all_internal(): [stm32h7x.ap2] Delete all breakpoints 1: Debug: 138 1366 mem_ap.c:71 mem_ap_deinit_target(): mem_ap_deinit_target 1: Debug: 139 1366 target.c:2130 target_free_all_working_areas_restore(): freeing all working areas 1: Debug: 140 1366 breakpoints.c:328 breakpoint_remove_all_internal(): [stm32h7x.cpu0] Delete all breakpoints 1: Debug: 141 1366 target.c:2130 target_free_all_working_areas_restore(): freeing all working areas 1/3 Test #1: rtos-apis-test ...................***Failed 1.41 sec ``` |
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From: Tommy M. <tom...@ho...> - 2024-06-20 07:13:58
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Might be worth posting a verbose `openocd -d3` log to see more detail about what's going on/wrong? |
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From: Liviu I. <il...@li...> - 2024-06-20 05:40:19
|
I'm trying to run some unit tests on a Nucleo-H745ZI, but openOCD is not happy with the device: ``` 1: Test command: /Users/ilg/MyProjects/micro-os-plus.github/micro-os-plus-iii/micro-os-plus-iii.git/tests/build/nucleo-h743zi-cmake-debug/xpacks/.bin/openocd "-c" "gdb_port disabled" "-c" "tcl_port disabled" "-c" "telnet_port disabled" "-f" "interface/stlink-dap.cfg" "-f" "target/stm32h7x.cfg" "-c" "program rtos-apis-test.elf verify" "-c" "arm semihosting enable" "-c" "arm semihosting_cmdline rtos-apis-test" "-c" "reset" 1: Working Directory: /Users/ilg/MyProjects/micro-os-plus.github/micro-os-plus-iii/micro-os-plus-iii.git/tests/build/nucleo-h743zi-cmake-debug/platform-bin 1: Test timeout computed to be: 10000000 1: xPack Open On-Chip Debugger 0.12.0+dev-01621-gd4607c225-dirty (2024-06-18-23:02) 1: Licensed under GNU GPL v2 1: For bug reports, read 1: http://openocd.org/doc/doxygen/bugs.html 1: Info : auto-selecting first available session transport "dapdirect_swd". To override use 'transport select <transport>'. 1: Error: read version failed 1: ** OpenOCD init failed ** 1: shutdown command invoked 1: ``` The configuration is a copy/paste from another one that runs fine on a Nucleo-F767ZI board. openOCD is compiled from the top git commit, plus the patch to fix the Cortex-M7 bug. I also tried `target/stm32h7x_dual_bank.cfg` and `board/st_nucleo_h745zi.cfg`, with the same result. Any suggestions? Liviu |
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From: Rob M. <Rob...@u-...> - 2024-06-19 15:19:16
|
I am trying to use OpenOCD (v0.12.2) to program/debug an NXP MCNX947 chip (ARM CM33) on a FRDM board. I can get OpenOCD to connect but it always bombs out with "Unable to reset target". I've tried setting reset_config to none and to srst_only but neither has made a difference. Can anyone suggest any other ways forward?
Here is the full output:
openocd -f ../openocd/scripts/interface/cmsis-dap.cfg -c "transport select swd" -c "reset_config srst_only" -c "gdb_port disabled" -c "tcl_port disabled" -c "telnet_port disabled" -c "adapter speed 1000" -c "program /TEMP/test_main reset"
xPack Open On-Chip Debugger 0.12.0+dev-01312-g18281b0c4-dirty (2023-09-04-22:32)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
swd
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
adapter speed: 1000 kHz
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: JTAG supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 1.10
Info : CMSIS-DAP: Serial# = KBEE1LS3QWE4M
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 1000 kHz
Warn : gdb services need one or more targets defined
embedded:startup.tcl:1524: Error: ** Unable to reset target **
in procedure 'program'
in procedure 'program_error' called at file "embedded:startup.tcl", line 1561
at file "embedded:startup.tcl", line 1524
|
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From: Dominic R. <Dom...@gm...> - 2024-05-30 09:05:33
|
Hi Martin,
Am 29/05/2024 um 12:01 schrieb Salko, MARTIN:
> Dear openocd users/developers.
>
> I have an issue with connecting to our product using the xds110 debuger,
> and openocd with gbd.
> I have openocd built using mingw-w64, from gitlab repository with
> following commit:
>
> 2c8376b - target/xtensa: avoid IHI for writes to non-executable memory
> (this is because support for ti am243x was added recently)
>
> I’m trying to connect to a running cpu, then reset it and run it again,
> I’d like to essentially do a step by step trace.
I'm not sure what you're trying to achieve is possible. Not due to
OpenOCD, but due to the way the AM24x works.
For all I know you can't debug these things from reset. There's a ROM
that is executing before you get a chance to take control. Typically
that ROM will load the bootloader, which then loads the application.
The ROM only accepts an image in x509 format that contains some
meta-data and is used for signature verification (in case of a fused
HS-SE device).
When working on bootloader stuff I'd put a while loop early in my code
and simply attach the debugger, then step out of the loop.
When working with application stuff you can put a "null" bootloader in
non-volatile memory that just sets up memory and the cores. You then
attach the debugger, load your application straight to RAM, and the
debug from there.
Maybe you could share a bit more about what problem you're trying to
solve, then I might be able to give you some hints on how to approach that.
Apart from that it'd be interesting how good "reset halt" is expected to
work these days with complex SoCs like the AM24x. My expectation is
"not", and what you're seeing then is just follow-up errors.
> This is an error I’m getting from open ocd, when gdb connects to the
> first core:
> oocd ('err', 'Error: JTAG-DP STICKY ERROR\r\n')
>
> oocd ('err', 'Error: Failed to read memory at 0xe000ed00\r\n')
>
> oocd ('err', 'Error executing event gdb-attach on target
> am243.cpu.sysctrl:\r\n')
>
Best Regards,
Dominic
|
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From: Salko, M. <mar...@si...> - 2024-05-29 13:37:05
|
Dear openocd users/developers.
I have an issue with connecting to our product using the xds110 debuger, and openocd with gbd.
I have openocd built using mingw-w64, from gitlab repository with following commit:
2c8376b - target/xtensa: avoid IHI for writes to non-executable memory
(this is because support for ti am243x was added recently)
I'm trying to connect to a running cpu, then reset it and run it again, I'd like to essentially do a step by step trace.
This is an error I'm getting from open ocd, when gdb connects to the first core:
oocd ('err', 'Error: JTAG-DP STICKY ERROR\r\n')
oocd ('err', 'Error: Failed to read memory at 0xe000ed00\r\n')
oocd ('err', 'Error executing event gdb-attach on target am243.cpu.sysctrl:\r\n')
gdb connects using command: "target extended-remote localhost:3333"
>From the schematic we use 5 pin jtag with emu0/1 pins pulled up high, so I think design wise this is fine (debugging tools provided)
This is my board.cfg:
source [find interface/xds110.cfg]
transport select jtag
reset_config srst_only srst_push_pull
adapter srst delay 20
set SOC am243
source [find target/ti_k3.cfg]
adapter speed 250
gdb_port 3333
bindto 0.0.0.0
init
reset halt
wait_halt
sleep 100
poll
am243.cpu.main0_r5.0 arp_examine
>From reading the documentation on arms side, sticky DP is an abort condition? As far as CoreSight is concerned.
And there is a register to clear it, so maybe that is what I have to do, However I have no experience in working directly with jtag or DP registers.
Any suggestions/help would be highly appreciated.
With best regards,
Martin.
|
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From: Abdullah Y. <abd...@yo...> - 2024-05-07 11:46:25
|
Hi Paul, Thank you for your support. Regards, Abdullah YILDIZ Design and Verification Team Member at YONGATEK Microelectronics From: Paul Fertser <fer...@gm...> Date: Tuesday, 30 April 2024 at 17:26 To: Abdullah YILDIZ <abd...@yo...> Cc: ope...@li... <ope...@li...> Subject: Re: [OpenOCD-user] Exporting SVF File from OpenOCD Hi, On Thu, Apr 25, 2024 at 12:39:49PM +0000, Abdullah YILDIZ wrote: > I need to export all JTAG transactions to a file in SVF (i.e., Serial Vector > Format) when I run a particular OpenOCD script. > > Is there any method to do this in OpenOCD? Not really, no. You could probably just grab -d4 log and extract all actions from it and convert to SVF with a simple script but you'll have to ignore the returned data. -- Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! mailto:fer...@gm... Important Notice: This e-mail and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager immediately. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately by e-mail if you have received this e-mail by mistake and delete all copies of this e-mail from your system. If you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited. YONGATEK does not represent, warrant and/or guarantee that the integrity of this communication has been maintained, nor that it is free of any error, virus, interception or interference. |
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From: José G. de C. R. <jos...@pr...> - 2024-05-05 22:42:10
|
On Sunday, May 5th, 2024 at 18:57, Ubaldo Tiberi <uba...@gm...> wrote: > If I run openocd on terminal with the right board/selection and I connect to it through with arm-none-eabi-gdb -ex "target extended-remote localhost:3333” everything works fine and I can happily debug my code. What version of openocd are you using? > However, if I run openocd on a terminal and I try to call gdb through some other tool (I am running Vimspector on Vim, but that apparently the same issue happens with VSCode as well, see below), I get a lot of warnings displayed on the openocd console like the following: > Warn : ignoring character 0x47 A few coworkers of mine use gdb + VSCode + cortex-m extension (but they are on Windows) and I don't remember any of them complaining about this. Once you tell me the version, I could check with them and try to reproduce it. > I googled a bit and I found some people encountering the same issues although on different platforms. Here are some examples: > > https://github.com/raspberrypi/openocd/issues/14 > https://esp32.com/viewtopic.php?t=26968 > https://www.esp32.com/viewtopic.php?t=16883 Just to make sure, both espressif and raspberry seem to use their own forks and I don't know how up to date it is. |
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From: Tommy M. <tom...@ho...> - 2024-05-05 22:39:27
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You probably need to capture and post the openocd -d3 verbose and GDB remote serial protocol logs for the working and non-working cases to aid with investigation/analysis. |
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From: Ubaldo T. <uba...@gm...> - 2024-05-05 21:58:17
|
Hi! If I run openocd on terminal with the right board/selection and I connect to it through with arm-none-eabi-gdb -ex "target extended-remote localhost:3333” everything works fine and I can happily debug my code. However, if I run openocd on a terminal and I try to call gdb through some other tool (I am running Vimspector on Vim, but that apparently the same issue happens with VSCode as well, see below), I get a lot of warnings displayed on the openocd console like the following: Warn : ignoring character 0x47 and obviously nothing is working. I googled a bit and I found some people encountering the same issues although on different platforms. Here are some examples: https://github.com/raspberrypi/openocd/issues/14 https://esp32.com/viewtopic.php?t=26968 https://www.esp32.com/viewtopic.php?t=16883 Does anybody know why that happens and how to solve it? Best, /Ubaldo |
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From: Paul F. <fer...@gm...> - 2024-04-30 14:26:55
|
Hi, On Thu, Apr 25, 2024 at 12:39:49PM +0000, Abdullah YILDIZ wrote: > I need to export all JTAG transactions to a file in SVF (i.e., Serial Vector > Format) when I run a particular OpenOCD script. > > Is there any method to do this in OpenOCD? Not really, no. You could probably just grab -d4 log and extract all actions from it and convert to SVF with a simple script but you'll have to ignore the returned data. -- Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! mailto:fer...@gm... |
|
From: Rob M. <Rob...@u-...> - 2024-04-28 12:46:20
|
In case anyone was following my posts about OpenOCD and STM32U5, the problem turns out to be nothing to do with OpenOCD; I can make it happen with the STM32Cube Programmer also. We set the SWD rate in our target code, always have done for STM32F4, but it seems that the same code with the STM32U5 on the NUCLEO-U575ZI-Q board causes the board to no longer connect to a debugger after it has been power-cycled; provided you don't power-cycle the board you can connect and disconnect to your hearts content, but after a power-cycle the STM32U5 needs to be recovered manually (connect its BOOT0 pin to VDD to make it boot from ROM, connect to it with the debugger under reset and erase all flash, then connect the BOOT0 pin back to GND again so that you can boot from flash) before it will connect to a debugger normally again. Even if we set the SWD rate to the same as what we understand the default to be, 2MHz, the problem remains. We have asked ST if the SWD rate-setting code needs to be different for STM32U5 or if this is some form of fundamental limitation of the debug arrangement on the NUCLEO-U575ZI-Q board. Rob -----Original Message----- From: Paul Fertser <fer...@gm...> Sent: Sunday, April 28, 2024 8:56 AM To: wieniawski <wie...@ou...> Cc: ope...@li... Subject: Re: [OpenOCD-user] OpenOCD using FT232H board **** This is an EXTERNAL email. It was sent from outside of u-blox. **** Hi, On Sun, Apr 28, 2024 at 11:20:59AM +0800, wieniawski wrote: > I am trying to using OpenOCD using a FT232H board. If you want to use it for SWD you either need an additional adapter (which would drive the output buffer depending on some additional signal) or to use the "resistor hack" (or if you're sure your FT232H doesn't have any buffering that can be direct connection without a resistor even). You also need to source the additional config for the SWD adapter or the resistor hack. There's no need to define TDO or TDI or SWDIO, those signals have fixed location on FTDI hardware and can't be changed. -- Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! mailto:fer...@gm... _______________________________________________ OpenOCD-user mailing list Ope...@li... https://lists.sourceforge.net/lists/listinfo/openocd-user |
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From: Paul F. <fer...@gm...> - 2024-04-28 07:56:17
|
Hi, On Sun, Apr 28, 2024 at 11:20:59AM +0800, wieniawski wrote: > I am trying to using OpenOCD using a FT232H board. If you want to use it for SWD you either need an additional adapter (which would drive the output buffer depending on some additional signal) or to use the "resistor hack" (or if you're sure your FT232H doesn't have any buffering that can be direct connection without a resistor even). You also need to source the additional config for the SWD adapter or the resistor hack. There's no need to define TDO or TDI or SWDIO, those signals have fixed location on FTDI hardware and can't be changed. -- Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! mailto:fer...@gm... |
|
From: wieniawski <wie...@ou...> - 2024-04-28 03:36:39
|
<html><head>
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<div>
<span>hi,
</span>
</div><div><span><br></span></div><div><span>I am trying to using OpenOCD using a FT232H board. (BTW, I am successfully using JLINK as the hardware adapter to connect to target STM32F407 board, so my software env and target board is OK).</span></div><div><span><br></span></div><div><span>and my command is</span></div><div><span>```bash</span></div><div><span>openocd -s d:/un-setup/OpenOCD/share/openocd/scripts/ -f interface/ftdi
</span><span style="line-height: 1.6;">/ft232h-module-swd.cfg -f target/stm32f4x.cfg</span></div><div><span>```</span></div><div><span><br></span></div><div><span>However, it turns out an error:</span></div><div><span>Error: Error connecting DP: cannot read IDR.</span></div><div><span><br></span></div><div><span>I guess that is due to an bus connection error between my FT232H board and target STM32F407 board.</span></div><div><span><br></span></div><div><span>I noticed that there are several lines in swd.cfg file:</span></div><div><span># Adafruit FT232H JTAG SWD
</span></div><div><span># Name Pin Name Func Func
</span></div><div><span># D0 J1-3 ADBUS0 TCK SWDCLK
</span></div><div><span># D1 J1-4 ADBUS1 TDO/DI SWDIO
</span></div><div><span># D2 J1-5 ADBUS2 TDI/DO SWDIO</span></div><div><span><br></span></div><div><span>Where, there are to SWDIO pin defined. And I tried both of these two pins connected to target MCU, same error happens.</span></div><div><span><br></span></div><div><span>Then I realized that SWDIO is a bi-direction pin. So I tried to uncomment there 2 lines in swd.cfg file</span></div><div><span>#ftdi layout_signal TDO -data 0x0002 -oe 0x0002
</span></div><div><span>#ftdi layout_signal TDI -data 0x0004</span></div><div><span><br></span></div><div><span>However, it came out same error again.</span></div><div><span><br></span></div><div><span>So I am guessing:</span></div><div><span><br></span></div><div><span>Do I need to short FT232H AD1 and AD2 together?</span></div><div>Or is there any extra short circuit like using TDO as the output enable signal to TDI?</div><div><br></div><div>Thx,</div><div><br></div><div><br></div>
<div>
<span>
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From: Abdullah Y. <abd...@yo...> - 2024-04-25 16:16:08
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Dear all, I need to export all JTAG transactions to a file in SVF (i.e., Serial Vector Format) when I run a particular OpenOCD script. Is there any method to do this in OpenOCD? Regards, Abdullah YILDIZ Design and Verification Team Member at YONGATEK Microelectronics Important Notice: This e-mail and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager immediately. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately by e-mail if you have received this e-mail by mistake and delete all copies of this e-mail from your system. If you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited. YONGATEK does not represent, warrant and/or guarantee that the integrity of this communication has been maintained, nor that it is free of any error, virus, interception or interference. |
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