On Thursday 25 March 2010, Laurent Gauch wrote:
> The JTAG frequency of the chain is not depending on the capability of
> the JTAG Dongle but is depending on the chain itself :
And its *DYNAMIC STATE..
COnsider that the events OpenOCD sends during the reset and init
sequences can help the "manual" configuration of the clock rates
which targets can currently support. Examples:
- right after reset, "slow" hardware default, e.g. 4 MHz, 32 KHz,
adjusted e.g. by a divide-by-six on most ARM cores.
After reset-init set up PLLLs etc, "fast" maybe 200 MHz
On entry to low power modes, "slow" again .... or annoyingly, on
some chips the core isn't even locked, so 0/6 clock rate may mean you
can't even use JTAG (or whatever)...
... adaptive clocking does some of that reconfiguration too, with
hardware assist instead of OpenOCD events and handlers.
But in no case is there a *SINGLE* max frequency that never changes.
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