openocd-devel

[Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Dennis.Cheng <m89...@gm...>]

Hi folks,

When I tried to use OpenOCD detect NAND flash in S3C2410 platform(nand probe
0), I got the "Address translation failure" result.
I tried "reset" then "halt", "Address translation failure" was still exist.
But when I enter "reset; halt" command, NAND flash probe is OK.
I think it is OpenOCD bug: S3C2410's MMU status was misunderstand, so
OpenOCD tried to translate address.

Dennis

Re: [Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Øyvind H. <oyv...@zy...>]

On Tue, Nov 3, 2009 at 4:06 AM, Dennis.Cheng <m89...@gm...> wrote:
> Hi folks,
>
> When I tried to use OpenOCD detect NAND flash in S3C2410 platform(nand probe
> 0), I got the "Address translation failure" result.
> I tried "reset" then "halt", "Address translation failure" was still exist.
> But when I enter "reset; halt" command, NAND flash probe is OK.
> I think it is OpenOCD bug: S3C2410's MMU status was misunderstand, so
> OpenOCD tried to translate address.

Could you provide debug_level 3 logs?

http://openocd.berlios.de/doc/doxygen/bugs.html

-- 
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer

Re: [Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Dennis.Cheng <m89...@gm...>]

> reset
JTAG tap: s3c2410.cpu tap/device found: 0x0032409d (mfg: 0x04e, part:
0x0324, ver: 0x0)
> halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x400000d3 pc: 0x33f94990
MMU: disabled, D-Cache: enabled, I-Cache: enabled
> nand probe 0
Address translation failure
Address translation failure
Address translation failure
Address translation failure
Address translation failure
Address translation failure
NAND flash device 'NAND 64MiB 3,3V 8-bit' found
>

///////////////////////
debug_level 3 logs ( after nand probe 0)

Debug: 178 243000 command.c:68 script_debug(): command - probe
Debug: 179 243000 command.c:77 script_debug(): probe -
argv[0]=ocd_nand_probe
Debug: 180 243000 command.c:77 script_debug(): probe - argv[1]=0
Debug: 181 243000 target.c:1543 target_write_u32(): address: 0x4e000000,
value:
0x00008353
Debug: 182 243000 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000004
Debug: 183 243000 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 184 243016 arm920t.c:562 arm920t_write_memory(): D-Cache enabled,
writing
 through to main memory
Debug: 185 243016 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0xfeffd380
, size: 0x00000004, count: 0x00000001
Debug: 186 243032 armv4_5_mmu.c:46 armv4_5_mmu_translate_va(): 1st lvl desc:
000
00000
Error: 187 243032 armv4_5_mmu.c:51 armv4_5_mmu_translate_va(): Address
translati
on failure
Debug: 188 243047 target.c:1566 target_write_u16(): address: 0x4e000004,
value:
0x000000ff
Debug: 189 243063 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000004
Debug: 190 243063 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 191 243079 arm920t.c:562 arm920t_write_memory(): D-Cache enabled,
writing
 through to main memory
Debug: 192 243094 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0xfeffd380
, size: 0x00000004, count: 0x00000001
Debug: 193 243094 armv4_5_mmu.c:46 armv4_5_mmu_translate_va(): 1st lvl desc:
000
00000
Error: 194 243110 armv4_5_mmu.c:51 armv4_5_mmu_translate_va(): Address
translati
on failure
Debug: 195 243125 target.c:1543 target_write_u32(): address: 0x4e000004,
value:
0x000000ff
Debug: 196 243141 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000004
Debug: 197 243141 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 198 243157 arm920t.c:562 arm920t_write_memory(): D-Cache enabled,
writing
 through to main memory
Debug: 199 243172 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0xfeffd380
, size: 0x00000004, count: 0x00000001
Debug: 200 243172 armv4_5_mmu.c:46 armv4_5_mmu_translate_va(): 1st lvl desc:
000
00000
Error: 201 243188 armv4_5_mmu.c:51 armv4_5_mmu_translate_va(): Address
translati
on failure
Debug: 202 243188 target.c:1566 target_write_u16(): address: 0x4e000004,
value:
0x00000090
Debug: 203 243204 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000004
Debug: 204 243204 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 205 243219 arm920t.c:562 arm920t_write_memory(): D-Cache enabled,
writing
 through to main memory
Debug: 206 243235 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0xfeffd380
, size: 0x00000004, count: 0x00000001
Debug: 207 243235 armv4_5_mmu.c:46 armv4_5_mmu_translate_va(): 1st lvl desc:
000
00000
Error: 208 243250 armv4_5_mmu.c:51 armv4_5_mmu_translate_va(): Address
translati
on failure
Debug: 209 243266 target.c:1566 target_write_u16(): address: 0x4e000008,
value:
0x00000000
Debug: 210 243266 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000004
Debug: 211 243266 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 212 243282 arm920t.c:562 arm920t_write_memory(): D-Cache enabled,
writing
 through to main memory
Debug: 213 243297 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0xfeffd380
, size: 0x00000004, count: 0x00000001
Debug: 214 243313 armv4_5_mmu.c:46 armv4_5_mmu_translate_va(): 1st lvl desc:
000
00000
Error: 215 243329 armv4_5_mmu.c:51 armv4_5_mmu_translate_va(): Address
translati
on failure
Debug: 216 243329 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0x4e00000c
, size: 0x00000001, count: 0x00000001
Debug: 217 243344 target.c:1519 target_read_u8(): address: 0x4e00000c,
value: 0x
ec
Debug: 218 243344 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0x4e00000c
, size: 0x00000001, count: 0x00000001
Debug: 219 243360 target.c:1519 target_read_u8(): address: 0x4e00000c,
value: 0x
76
Debug: 220 243375 nand.c:508 nand_probe(): found NAND 64MiB 3,3V 8-bit
(Samsung)

Debug: 221 243375 target.c:1543 target_write_u32(): address: 0x4e000000,
value:
0x00008353
Debug: 222 243375 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000004
Debug: 223 243391 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 224 243391 arm920t.c:562 arm920t_write_memory(): D-Cache enabled,
writing
 through to main memory
Debug: 225 243407 arm7_9_common.c:2282 arm7_9_read_memory(): address:
0xfeffd380
, size: 0x00000004, count: 0x00000001
Debug: 226 243422 armv4_5_mmu.c:46 armv4_5_mmu_translate_va(): 1st lvl desc:
000
00000
Error: 227 243422 armv4_5_mmu.c:51 armv4_5_mmu_translate_va(): Address
translati
on failure
User : 228 243438 command.c:400 command_print(): NAND flash device 'NAND
64MiB 3
,3V 8-bit' found



2009/11/3 Øyvind Harboe <oyv...@zy...>

> On Tue, Nov 3, 2009 at 4:06 AM, Dennis.Cheng <m89...@gm...> wrote:
> > Hi folks,
> >
> > When I tried to use OpenOCD detect NAND flash in S3C2410 platform(nand
> probe
> > 0), I got the "Address translation failure" result.
> > I tried "reset" then "halt", "Address translation failure" was still
> exist.
> > But when I enter "reset; halt" command, NAND flash probe is OK.
> > I think it is OpenOCD bug: S3C2410's MMU status was misunderstand, so
> > OpenOCD tried to translate address.
>
> Could you provide debug_level 3 logs?
>
> http://openocd.berlios.de/doc/doxygen/bugs.html
>
> --
> Øyvind Harboe
> http://www.zylin.com/zy1000.html
> ARM7 ARM9 ARM11 XScale Cortex
> JTAG debugger and flash programmer
>

Re: [Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Øyvind H. <oyv...@zy...>]

Could you try a git bisect procedure to find out if
this broke since 0.2 and what version that broke?

-- 
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer

Re: [Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Øyvind H. <oyv...@zy...>]

Try the attached patch.



-- 
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer

Re: [Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Øyvind H. <oyv...@zy...>]

On Tue, Nov 3, 2009 at 2:15 PM, Dennis.Cheng <m89...@gm...> wrote:
> Thanks. It works well :-).

I've pushed the fix.

I'm a little bit worried about being able to test the case where
a write to a cache line for a breakpoint.

Here the code has to flush that cache line + invalidate the cache line.


-- 
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer

Re: [Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Dennis.Cheng <m89...@gm...>]

In arm920t_write_memory, how about imitate arm926ejs_write_memory?

    if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) ||
(size==4)))
    {
        /* special case the handling of single word writes to bypass MMU
         * to allow implementation of breakpoints in memory marked read only
         * by MMU */
        if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
        {
            LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
            /* MCR p15,0,Rd,c7,c10,2 */
            retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0,
address);
            if (retval != ERROR_OK)
                return retval;
        }

            uint32_t pa, cb, ap;
            int type, domain;

            pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
address, &type, &cb, &domain, &ap);
            if (type == -1)
                return ERROR_OK;
            /* cacheable & bufferable means write-back region */
            if (cb == 3)
                armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
pa, size, count, buffer);
    } else
    {
        if ((retval = arm7_9_write_memory(target, address, size, count,
buffer)) != ERROR_OK)
            return retval;
    }

About I-cache, should arm920t follows arm926ejs ?
    if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
    {
        if (count <= 1)
        {
            /* invalidate ICache single entry with MVA */
            arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
        }
        else
        {
            /* invalidate ICache */
            arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
        }
    }

2009/11/3 Øyvind Harboe <oyv...@zy...>

> On Tue, Nov 3, 2009 at 2:15 PM, Dennis.Cheng <m89...@gm...> wrote:
> > Thanks. It works well :-).
>
> I've pushed the fix.
>
> I'm a little bit worried about being able to test the case where
> a write to a cache line for a breakpoint.
>
> Here the code has to flush that cache line + invalidate the cache line.
>
>
> --
> Øyvind Harboe
> http://www.zylin.com/zy1000.html
> ARM7 ARM9 ARM11 XScale Cortex
> JTAG debugger and flash programmer
>

Re: [Openocd-development] 0.3.0-rc1-dev bugs in s3c2410 nand probe

[Øyvind H. <oyv...@zy...>]

On Wed, Nov 4, 2009 at 4:24 AM, Dennis.Cheng <m89...@gm...> wrote:
> In arm920t_write_memory, how about imitate arm926ejs_write_memory?

Could you submit a patch?

I tried to make minimal changes before 0.3, but as soon as 0.3 is out
of the door I'd like arm920t to support breakpoints in memory
marked as read only by the MMU.

If you want to be a bit more ambitious it would be nice if you wrote
an implementation that could be shared between arm920t and arm926ejs...

-- 
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer