openocd-devel

[Openocd-development] XScale IXP42x 16-bit CFI flash detection fails

[Leon W. <leo...@gm...>]

Hello,

I am using a IXP420 processor with a 16-bit 28F128J3D75 Intel CFI
Flash device, in 16-bit mode. The processor runs in big-endian mode. I
use a BDI2000 under Linux, but am now setting up OpenOCD under Cygwin,
for production purposes at first instance.

Using OpenOCD from source, under CygWin under Windows XP (32-bit
little-endian), with a Amontec JTAGkey I cannot get the CFI flash
detection to work. I have tried the trunk (rev 206), xscale (rev 118)
and xscale-ixp-be (rev 179) branches.

Relevant piece of my config:

---
jtag_device 7 0x01 0x7f 0x7e
#target
target xscale big reset_halt 0 ixp42x
xscale debug_handler 0 0xfe000800
xscale cache_clean_address 0 0xfffe0000
#flash
#flash bank <type> <base> <size> <chip-width> <bus-width> <target#>
#chip and bus-width in byte
flash bank cfi 0x50000000 0x01000000 2 2 0
---

I think OpenOCD does not cover all 8-bit / 16-bit cases correctly, for
CFI querying, as described in Intel's Application Note 646 (Google for
"Intel AP-646").

# enable write access to flash chip select
mww 0xc4000000 0xbfff3c42

flash probe 0

probing failed for flash bank '#0' at 0x50000000

The log shows:

Debug:   xscale.c:1965 xscale_write_memory(): address: 0xc4000000,
size: 0x00000004, count: 0x00000001
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x50000aaa,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x50000554,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x50000aaa,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1895 xscale_read_memory(): address: 0x50000000,
size: 0x00000002, count: 0x00000001
Debug:   target.c:784 target_read_u16(): address: 0x50000000, value: 0x0018
Debug:   xscale.c:1895 xscale_read_memory(): address: 0x50000002,
size: 0x00000002, count: 0x00000001
Debug:   target.c:784 target_read_u16(): address: 0x50000002, value: 0x0089
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x50000000,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x50000000,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x500000aa,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1895 xscale_read_memory(): address: 0x50000020,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1895 xscale_read_memory(): address: 0x50000022,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1895 xscale_read_memory(): address: 0x50000024,
size: 0x00000002, count: 0x00000001
Debug:   cfi.c:1692 cfi_probe(): CFI qry returned: 0x52 0x51 0x01
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x50000000,
size: 0x00000002, count: 0x00000001
Debug:   xscale.c:1965 xscale_write_memory(): address: 0x50000000,
size: 0x00000002, count: 0x00000001


I tried to manually probe the device as follows:

# enable write access to flash chip select
mww 0xc4000000 0xbfff3c42

# query
mwh 0x500000aa 0x0098

# read QRY using half-words (half word = 16-bit)
mdh 0x50000020 4
0052 0051 0001 0059
R
Q
0x01
Y

The above definitely seems wrong.

# read QRY using words (32-bit = word)
mdw 0x50000020 4
0051 0052 0059 0001
Q
R
Y
0x01


The half-word reads are re-ordered, the word reads are correctly ordered.

Everything works fine under the BDI2000, as a reference:

Core#0>mmh 0x500000aa 0x9898
Core#0>mdh 0x50000020 4
50000020 : 0x0051      81  .Q
50000022 : 0x0052      82  .R
50000024 : 0x0059      89  .Y
50000026 : 0x0001       1  ..
Core#0>mmh 0x500000aa 0x9898
Core#0>md 0x50000020 4
50000020 : 0x00510052      5308498  .Q.R
50000024 : 0x00590001      5832705  .Y..
50000028 : 0x00000031           49  ...1
5000002c : 0x00000000            0  ....



First, what OpenOCD code base should I take for my setup, and what
might go wrong here?

When viewing the source code of target/xscale.c:xscale_write_memory()
I see a relevant part of the code commented out.

Please enlighten me :-)

Regards,
-- 
Leon

Re: [Openocd-development] XScale IXP42x 16-bit CFI flash detection fails

[Michael S. <rin...@di...>]

Leon Woestenberg wrote:
> Hello,
>
> I think OpenOCD does not cover all 8-bit / 16-bit cases correctly, for
> CFI querying, as described in Intel's Application Note 646 (Google for
> "Intel AP-646").
>
> # enable write access to flash chip select
> mww 0xc4000000 0xbfff3c42
>
> flash probe 0
>
> probing failed for flash bank '#0' at 0x50000000
>   
I ran into that problem, too - it is not only CFI, but all bus accesses 
that are not 32 bit cause strange results (data being on the right part 
of the bus, but byte enables are swapped). You need to switch the XScale 
core to big-endian mode:

target  xscale big         reset_init   0          ixp42x
target_script 0 reset ixp425.init

in ixp425.init:

wait_halt
# set big endian mode
reg XSCALE_CTRL 0xF8
# setup expansion bus CS
mww 0xc4000000 0xbd113c42 # CS0: Flash, 16 Bit, write enabled @0x50000000
flash probe 0



I was wondering if openocd should do the write to the XSCALE_CTRL 
register. Currently, if I am not mistaken, the "big" parameter is not 
used by the source code at all, and the current behaviour means that you 
must always use a startup script for a IXP42X CPU when running in 
big-endian mode.


cu
Michael

Re: [Openocd-development] XScale IXP42x 16-bit CFI flash detection fails

[Leon W. <leo...@gm...>]

Hello Michael,

On 9/11/07, Michael Schwingen <rin...@di...> wrote:
> Leon Woestenberg wrote:
> > probing failed for flash bank '#0' at 0x50000000
> >
> register. Currently, if I am not mistaken, the "big" parameter is not
> used by the source code at all, and the current behaviour means that you
> must always use a startup script for a IXP42X CPU when running in
> big-endian mode.
>
Yes, my false assumption was that openocd would set the target to big
endian mode.

Thanks for the help.

Given that you seem to have a working setup, did you get SDRAM
initialization and subsequent use of SDRAM (or cache) workspace to
work in combination with the cfi_write_block() commands?

I hate to re-invent wheels here, if you might have a known-good
configuration lying around, would you care to share it?

Regards,
-- 
Leon

Re: [Openocd-development] XScale IXP42x 16-bit CFI flash detection fails

[Leon W. <leo...@gm...>]

Hello,

I pursued getting the OpenOCD / IXP42x combo to work almost fully
correctly with a workspace area.

The (single sector) data I tried to flash and the subsequent dump
differ only in the first 16-bit:

--- /random.txt 2007-09-13 16:15:40.047915400 +0200
+++ /dump.txt   2007-09-13 16:17:46.685881800 +0200
@@ -1,4 +1,4 @@
-000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+000000 00 00 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 000010 de ad be ef 52 a8 c0 27 fc a6 eb ba fa 71 f4 1c
 000020 31 c7 44 dc c2 68 b2 24 99 a0 ba f2 bf f6 22 7f
 000030 fe b9 bc 73 c5 93 b7 db de 64 aa 87 31 91 b7 ba

Given that my second nibble (4 bits) always become zero after
programming I suspect this line to be redudant, as Intel docs tell me
0xff should be used to return to "read array" mode, not 0xf0.

int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)

/* return to read array mode */
cfi_command(bank, 0xf0, current_word);




config:

jtag_speed 0
reset_config trst_and_srst
jtag_device 7 0x01 0x7f 0x7e
target xscale big reset_init 0 ixp42x
target_script 0 reset /ixp42x_big.init
xscale debug_handler 0 0xfe000800
xscale cache_clean_address 0 0xfffe0000
flash bank cfi 0x50000000 0x01000000 2 2 0
working_area 0 0x01000000 0x00100000 nobackup

init script:

wait_halt
#set big endian mode
reg XSCALE_CTRL 0xF8
#setup expansion bus CS#0, write enable, @0x50000000
mww 0xc4000000 0xbcd23c42
flash probe 0
# 32 MB, CAS3
mww 0xcc000000 0x00000018
# disable refresh
mww 0xcc000004 0x00000000
# nop
mww 0xcc000008 0x00000003
sleep 20
# set refresh value
mww 0xcc000004 0x0000081a
# precharge all
mww 0xcc000008 0x00000002
sleep 20
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000004
mww 0xcc000008 0x00000001
mww 0xcc000008 0x00000006
sleep 200
# map SDRAM to 0x00000000
mww 0xc4000020 0x00fffffe



--
Leon