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[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit 4960c9018f2560b11ede91cde8a68dc56c690159
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 21 16:45:00 2010 -0800

    Various doc/comment updates
    
    Doxygen: don't be needlessly verbose; alphabetically sort members
    TODO: add random bits; clarify which manuals are referenced
    ARM disassembler: mention a few opcodes that still aren't handled
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/Doxyfile.in b/Doxyfile.in
index f6e3ced..658f667 100644
--- a/Doxyfile.in
+++ b/Doxyfile.in
@@ -384,7 +384,7 @@ HIDE_SCOPE_NAMES       = NO
 # will put a list of the files that are included by a file in the documentation
 # of that file.
 
-SHOW_INCLUDE_FILES     = YES
+SHOW_INCLUDE_FILES     = NO
 
 # If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
 # is inserted in the documentation for inline members.
@@ -403,7 +403,7 @@ SORT_MEMBER_DOCS       = YES
 # by member name. If set to NO (the default) the members will appear in
 # declaration order.
 
-SORT_BRIEF_DOCS        = NO
+SORT_BRIEF_DOCS        = YES
 
 # If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
 # hierarchy of group names into alphabetical order. If set to NO (the default)
@@ -692,13 +692,13 @@ SOURCE_BROWSER         = YES
 # Setting the INLINE_SOURCES tag to YES will include the body
 # of functions and classes directly in the documentation.
 
-INLINE_SOURCES         = YES
+INLINE_SOURCES         = NO
 
 # Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
 # doxygen to hide any special comment blocks from generated source code
 # fragments. Normal C and C++ comments will always remain visible.
 
-STRIP_CODE_COMMENTS    = NO
+STRIP_CODE_COMMENTS    = YES
 
 # If the REFERENCED_BY_RELATION tag is set to YES 
 # then for each documented function all documented
diff --git a/TODO b/TODO
index 41d3457..aa2277c 100644
--- a/TODO
+++ b/TODO
@@ -142,6 +142,8 @@ Once the above are completed:
   https://lists.berlios.de/pipermail/openocd-development/2009-May/006590.html
 - regression: "reset halt" between 729(works) and 788(fails): @par
 https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
+- registers
+  - add flush-value operation, call them all on resume/reset
 - mcr/mrc target->type support
   - missing from ARM920t, ARM966e, XScale.
   It's possible that the current syntax is unable to support read-modify-write
@@ -170,10 +172,18 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
 - Thumb2 single stepping: ARM1156T2 needs simulator support
 - Cortex A8 support (ML)
   - add target implementation (ML)
+- Cortex M3 support
+  - when stepping, only write dirtied registers (be faster)
+  - when connecting to halted core, fetch registers (startup is quirky)
 - Generic ARM run_algorithm() interface
   - tagged struct wrapping ARM instructions and metadata
   - not revision-specific (current: ARMv4+ARMv5 -or- ARMv6 -or- ARMv7)
   - usable with at least arm_nandwrite() and generic CFI drivers
+- ETM
+  - don't show FIFOFULL registers if they're not supported
+  - use comparators to get more breakpoints and watchpoints
+  - add "etm drivers" command
+  - trace driver init() via examine() paths only, not setup()/reset
 - MC1322x support (JW/DE?)
   - integrate and test support from JW (and DE?)
   - get working with a known good interface (i.e. not today's jlink)
@@ -356,9 +366,11 @@ to complete:
 - Develop milestone and release guidelines, processes, and scripts.
 - Develop "style" guidelines (and scripts) for maintainers:
   - reviewing patches
-  - committing to Subversion
-- Review The Guide for OpenOCD Users for documentation errors or omissions
-- Update The Manual for OpenOCD Developers:
+  - committing to git
+- Review Users' Guide for documentation errors or omissions
+  - "capture" and "ocd_find" commands
+  - "ocd_" prefix on various stuff
+- Update Developer's Manual (doxygen output)
   - Add documentation describing the architecture of each module
   - Provide more Technical Primers to bootstrap contributor knowledge
 
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 587131b..f02053f 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -50,6 +50,7 @@
  *       except as coprocessor 10/11 operations
  *     * Most ARM instructions through ARMv6 are decoded, but some
  *       of the post-ARMv4 opcodes may not be handled yet
+ *		CPS, SDIV, UDIV, LDREX*, STREX*, QASX, ...
  *     * NEON instructions are not understood (ARMv7-A)
  *
  *  - Thumb/Thumb2 decoding

commit 08b0be94b5fd13a8afe4f070bc7b471cc5c3423d
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 21 16:15:41 2010 -0800

    User's Guide secton on target hardware setup
    
    Highlight the needs to properly jumper development boards; to
    make the OpenOCD configuration match the jumpering; and to have
    a usable "reset-init" method when debugging early boot code.
    
    Specific mention of the "ATX Mode" that seems useful on
    many i.MX boards, forcing NAND boot.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 05b6f4e..ee5c723 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -23,7 +23,7 @@ of the Open On-Chip Debugger (OpenOCD).
 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
-@item Copyright @copyright{} 2009 David Brownell
+@item Copyright @copyright{} 2009-2010 David Brownell
 @end itemize
 
 @quotation
@@ -1027,6 +1027,86 @@ various kinds of message.
 
 @end itemize
 
+@section Target Hardware Setup
+
+Chip vendors often provide software development boards which
+are highly configurable, so that they can support all options
+that product boards may require.  @emph{Make sure that any
+jumpers or switches match the system configuration you are
+working with.}
+
+Common issues include:
+
+@itemize @bullet
+
+@item @b{JTAG setup} ...
+Boards may support more than one JTAG configuration.
+Examples include jumpers controlling pullups versus pulldowns
+on the nTRST and/or nSRST signals, and choice of connectors
+(e.g. which of two headers on the base board,
+or one from a daughtercard).
+For some Texas Instruments boards, you may need to jumper the
+EMU0 and EMU1 signals (which OpenOCD won't currently control).
+
+@item @b{Boot Modes} ...
+Complex chips often support multiple boot modes, controlled
+by external jumpers.  Make sure this is set up correctly.
+For example many i.MX boards from NXP need to be jumpered
+to "ATX mode" to start booting using the on-chip ROM, when
+using second stage bootloader code stored in a NAND flash chip.
+
+Such explicit configuration is common, and not limited to
+booting from NAND.  You might also need to set jumpers to
+start booting using code loaded from an MMC/SD card; external
+SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
+flash; some external host; or various other sources.
+
+
+@item @b{Memory Addressing} ...
+Boards which support multiple boot modes may also have jumpers
+to configure memory addressing.  One board, for example, jumpers
+external chipselect 0 (used for booting) to address either
+a large SRAM (which must be pre-loaded via JTAG), NOR flash,
+or NAND flash.  When it's jumpered to address NAND flash, that
+board must also be told to start booting from on-chip ROM.
+
+Your @file{board.cfg} file may also need to be told this jumper
+configuration, so that it can know whether to declare NOR flash
+using @command{flash bank} or instead declare NAND flash with
+@command{nand device}; and likewise which probe to perform in
+its @code{reset-init} handler.
+
+A closely related issue is bus width.  Jumpers might need to
+distinguish between 8 bit or 16 bit bus access for the flash
+used to start booting.
+
+@item @b{Peripheral Access} ...
+Development boards generally provide access to every peripheral
+on the chip, sometimes in multiple modes (such as by providing
+multiple audio codec chips).
+This interacts with software
+configuration of pin multiplexing, where for example a
+given pin may be routed either to the MMC/SD controller
+or the GPIO controller.  It also often interacts with
+configuration jumpers.  One jumper may be used to route
+signals to an MMC/SD card slot or an expansion bus (which
+might in turn affect booting); others might control which
+audio or video codecs are used.
+
+@end itemize
+
+Plus you should of course have @code{reset-init} event handlers
+which set up the hardware to match that jumper configuration.
+That includes in particular any oscillator or PLL used to clock
+the CPU, and any memory controllers needed to access external
+memory and peripherals.  Without such handlers, you won't be
+able to access those resources without working target firmware
+which can do that setup ... this can be awkward when you're
+trying to debug that target firmware.  Even if there's a ROM
+bootloader which handles a few issues, it rarely provides full
+access to all board-specific capabilities.
+
+
 @node Config File Guidelines
 @chapter Config File Guidelines
 

commit f06148612be714f74174bb86fe95f49df07c32fa
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 21 13:39:22 2010 -0800

    ADIv5 header cleanup (+ #defines)
    
    Update the comments about DP registers and some of the bitfields.
    Remove inappropriate (and unused) DP_ZERO declaration.
    
    Add some (currently unused) #defines needed for SWD protocol support,
    based on previous patches from Andreas Fritiofson and Simon Qian.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 675a173..861a13d 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -42,22 +42,42 @@
 #define JTAG_ACK_OK_FAULT	0x2
 #define JTAG_ACK_WAIT		0x1
 
+/* three-bit ACK values for SWD access (sent LSB first) */
+#define SWD_ACK_OK		0x4
+#define SWD_ACK_WAIT		0x2
+#define SWD_ACK_FAULT		0x1
+
 #define DPAP_WRITE		0
 #define DPAP_READ		1
 
-/* A[3:0] for DP registers (for JTAG, stored in DPACC) */
-#define DP_ZERO			0
-#define DP_CTRL_STAT	0x4
-#define DP_SELECT		0x8
-#define DP_RDBUFF		0xC
+/* A[3:0] for DP registers; A[1:0] are always zero.
+ * - JTAG accesses all of these via JTAG_DP_DPACC, except for
+ *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
+ * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
+ */
+#define DP_IDCODE		0		/* SWD: read */
+#define DP_ABORT		0		/* SWD: write */
+#define DP_CTRL_STAT		0x4		/* r/w */
+#define DP_WCR			0x4		/* SWD: r/w (mux CTRLSEL) */
+#define DP_RESEND		0x8		/* SWD: read */
+#define DP_SELECT		0x8		/* JTAG: r/w; SWD: write */
+#define DP_RDBUFF		0xC		/* read-only */
+
+/* Fields of the DP's AP ABORT register */
+#define DAPABORT		(1 << 0)
+#define STKCMPCLR		(1 << 1)	/* SWD-only */
+#define STKERRCLR		(1 << 2)	/* SWD-only */
+#define WDERRCLR		(1 << 3)	/* SWD-only */
+#define ORUNERRCLR		(1 << 4)	/* SWD-only */
 
 /* Fields of the DP's CTRL/STAT register */
 #define CORUNDETECT		(1 << 0)
 #define SSTICKYORUN		(1 << 1)
 /* 3:2 - transaction mode (e.g. pushed compare) */
+#define SSTICKYCMP		(1 << 4)
 #define SSTICKYERR		(1 << 5)
-#define READOK			(1 << 6)
-#define WDATAERR		(1 << 7)
+#define READOK			(1 << 6)	/* SWD-only */
+#define WDATAERR		(1 << 7)	/* SWD-only */
 /* 11:8 - mask lanes for pushed compare or verify ops */
 /* 21:12 - transaction counter */
 #define CDBGRSTREQ		(1 << 26)

-----------------------------------------------------------------------

Summary of changes:
 Doxyfile.in                   |    8 ++--
 TODO                          |   18 +++++++-
 doc/openocd.texi              |   82 ++++++++++++++++++++++++++++++++++++++++-
 src/target/arm_adi_v5.h       |   34 +++++++++++++---
 src/target/arm_disassembler.c |    1 +
 5 files changed, 128 insertions(+), 15 deletions(-)


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