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commit 900d745567809d9f0163cfde5832b10ec0581a0e
Author: Dean Glazeski <dn...@gm...>
Date: Wed Dec 9 12:51:52 2009 -0600
Olimex SAM9-L9260 board configuration update.
This updates the board configuration for the SAM9-L9260 board with the
configuration for the on-board NAND and dataflash. Included are commands
for configuring the AT91SAM9 NAND flash driver.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index 5c4714e..7c4b2cc 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -35,6 +35,7 @@ $_TARGETNAME configure -event reset-init {
##
# Clock configuration for 99.328 MHz main clock.
##
+ puts "Setting up clock"
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup
sleep 20 # wait 20 ms (need 15.6 ms for startup)
mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz)
@@ -53,6 +54,7 @@ $_TARGETNAME configure -event reset-init {
##
# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
##
+ puts "Configuring SDRAM"
mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31
@@ -86,4 +88,54 @@ $_TARGETNAME configure -event reset-init {
mww 0x20000000 0
mww 0xffffea04 0x2b6 # SDRAMC_TR : set refresh timer count to 7 us
+
+ ##
+ # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
+ ##
+ puts "Configuring NAND flash"
+ mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
+ mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+ mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
+ mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
+ mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
+ mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
+
+ mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
+
+ mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
+ mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
+ mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
+ mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+ # 3 TDF cycles, no optimization
+
+ mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
+ mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+ nand probe at91sam9260.flash
+
+ ##
+ # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
+ ##
+ puts "Setting up dataflash"
+ mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
+ # 2(SPI0_SPCK), and 11(SPI0_NPCS1)
+ mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
+ mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
+ mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
+
+ mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
+ mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
+ mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
+
+ mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
+ # 250ns delay before SPCK, 250ns b/n tx
+
+ mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
+ mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
}
+
+nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
-----------------------------------------------------------------------
Summary of changes:
tcl/board/olimex_sam9_l9260.cfg | 52 +++++++++++++++++++++++++++++++++++++++
1 files changed, 52 insertions(+), 0 deletions(-)
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