openocd-commit

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  81aec6be045792f3ed6a2d8fdbf1f534993b5c14 (commit)
       via  bbb754aa395be74ceac0c01640fb33c0fae52c20 (commit)
       via  19ad7f828ba36f398f52749c2f33e25a3ea78ac2 (commit)
       via  927ae6899df12e4667d181575cc0494bf12ff209 (commit)
       via  0a1b7dcfc40385f09b5eb088cd97d6ff25a5816d (commit)
       via  0529c14bfeb113ee37f4d961f9309102d57a1e39 (commit)
       via  a4a2808c2a849eddd5d7d454c048ffdfd89ca9c6 (commit)
       via  7b0314c377cc7c6a90db34d6d3e9e723d6d2b94a (commit)
       via  7936ab16da93f91258e17e4699360dc3f43728ce (commit)
       via  efb93efd6f2eb7aa555e4e86e95b636003ccf37a (commit)
       via  ecd709fa55333413f070939beadae98acac0e4c2 (commit)
       via  5da53f17f072289ce7ecbb9cffcdf5ed080b352c (commit)
      from  30a6e683b85291b8248a2f6189aa292fdf43162d (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 81aec6be045792f3ed6a2d8fdbf1f534993b5c14
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:08 2009 -0800

    ARM: list number of HW breakpoints/watchpoints
    
    When starting up, say how many hardware breakpoints and watchpoints
    are available on various targets.
    
    This makes it easier to tell GDB how many of those resources exist.
    Its remote protocol currently has no way to ask OpenOCD for that
    information, so it must configured by hand (or not at all).
    
    Update the docs to mention this; remove obsolete "don't do this" info.
    Presentation of GDB setup information is still a mess, but at least
    it calls out the three components that need setup.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ef395ea..a83c966 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6497,6 +6497,21 @@ a bit of googling to find something that fits your requirements.
 @cindex GDB
 OpenOCD complies with the remote gdbserver protocol, and as such can be used
 to debug remote targets.
+Setting up GDB to work with OpenOCD can involve several components:
+
+@itemize
+@item OpenOCD itself may need to be configured.  @xref{GDB Configuration}.
+@item GDB itself may need configuration, as shown in this chapter.
+@item If you have a GUI environment like Eclipse,
+that also will probably need to be configured.
+@end itemize
+
+Of course, the version of GDB you use will need to be one which has
+been built to know about the target CPU you're using.  It's probably
+part of the tool chain you're using.  For example, if you are doing
+cross-development for ARM on an x86 PC, instead of using the native
+x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
+if that's the tool chain used to compile your code.
 
 @anchor{Connecting to GDB}
 @section Connecting to GDB
@@ -6528,19 +6543,34 @@ session.
 To list the available OpenOCD commands type @command{monitor help} on the
 GDB command line.
 
+@section Configuring GDB for OpenOCD
+
 OpenOCD supports the gdb @option{qSupported} packet, this enables information
 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
 packet size and the device's memory map.
+You do not need to configure the packet size by hand,
+and the relevant parts of the memory map should be automatically
+set up when you declare (NOR) flash banks.
+
+However, there are other things which GDB can't currently query.
+You may need to set those up by hand.
+As OpenOCD starts up, you will often see a line reporting
+something like:
 
-Previous versions of OpenOCD required the following GDB options to increase
-the packet size and speed up GDB communication:
 @example
-set remote memory-write-packet-size 1024
-set remote memory-write-packet-size fixed
-set remote memory-read-packet-size 1024
-set remote memory-read-packet-size fixed
+Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
 @end example
-This is now handled in the @option{qSupported} PacketSize and should not be required.
+
+You can pass that information to GDB with these commands:
+
+@example
+set remote hardware-breakpoint-limit 6
+set remote hardware-watchpoint-limit 4
+@end example
+
+With that particular hardware (Cortex-M3) the hardware breakpoints
+only work for code running from flash memory.  Most other ARM systems
+do not have such restrictions.
 
 @section Programming using GDB
 @cindex Programming using GDB
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 558b211..bdd3233 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1608,6 +1608,12 @@ static int cortex_m3_examine(struct target *target)
 
 		/* Setup DWT */
 		cortex_m3_dwt_setup(cortex_m3, target);
+
+		/* These hardware breakpoints only work for code in flash! */
+		LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
+				target_name(target),
+				cortex_m3->fp_num_code,
+				cortex_m3->dwt_num_comp);
 	}
 
 	return ERROR_OK;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index cca9cc0..eb04bd1 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -289,6 +289,9 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 				buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 
+	LOG_INFO("%s: hardware has 2 breakpoints or watchpoints",
+			target_name(target));
+
 	return reg_cache;
 }
 
diff --git a/src/target/xscale.c b/src/target/xscale.c
index ac697da..9ed9eea 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2970,6 +2970,9 @@ static int xscale_init_arch_info(struct target *target,
 	xscale->dbr0_used = 0;
 	xscale->dbr1_used = 0;
 
+	LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
+			target_name(target));
+
 	xscale->arm_bkpt = ARMV5_BKPT(0x0);
 	xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 

commit bbb754aa395be74ceac0c01640fb33c0fae52c20
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:08 2009 -0800

    target: add debug_reason_name()
    
    Provide and use debug_reason_name() instead of expecting targets
    to call Jim_Nvp_value2name_simple().  Less dependency on Jim, and
    the code becomes more clear too.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index dce6d6a..1c4923b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -595,8 +595,7 @@ int arm_arch_state(struct target *target)
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
 			arm_state_strings[armv4_5->core_state],
-			Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-					target->debug_reason)->name,
+			debug_reason_name(target),
 			arm_mode_name(armv4_5->core_mode),
 			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index fc3f47c..d4f6309 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -480,8 +480,7 @@ int armv7m_arch_state(struct target *target)
 
 	LOG_USER("target halted due to %s, current mode: %s %s\n"
 		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
-		Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-				target->debug_reason)->name,
+		debug_reason_name(target),
 		armv7m_mode_strings[armv7m->core_mode],
 		armv7m_exception_string(armv7m->exception_number),
 		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 48d0720..e8ea541 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -254,7 +254,7 @@ int mips32_arch_state(struct target *target)
 	}
 
 	LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
-		Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
+		debug_reason_name(target),
 		buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 
 	return ERROR_OK;
diff --git a/src/target/target.c b/src/target/target.c
index 597046f..f249d38 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -187,7 +187,7 @@ const Jim_Nvp nvp_target_state[] = {
 	{ .name = NULL, .value = -1 },
 };
 
-const Jim_Nvp nvp_target_debug_reason [] = {
+static const Jim_Nvp nvp_target_debug_reason [] = {
 	{ .name = "debug-request"            , .value = DBG_REASON_DBGRQ },
 	{ .name = "breakpoint"               , .value = DBG_REASON_BREAKPOINT },
 	{ .name = "watchpoint"               , .value = DBG_REASON_WATCHPOINT },
@@ -214,6 +214,19 @@ const Jim_Nvp nvp_reset_modes[] = {
 	{ .name = NULL     , .value = -1 },
 };
 
+const char *debug_reason_name(struct target *t)
+{
+	const char *cp;
+
+	cp = Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+			t->debug_reason)->name;
+	if (!cp) {
+		LOG_ERROR("Invalid debug reason: %d", (int)(t->debug_reason));
+		cp = "(*BUG*unknown*BUG*)";
+	}
+	return cp;
+}
+
 const char *
 target_state_name( struct target *t )
 {
diff --git a/src/target/target.h b/src/target/target.h
index 7319069..dd3d4f7 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -91,8 +91,6 @@ enum target_debug_reason
 	DBG_REASON_UNDEFINED = 6
 };
 
-extern const Jim_Nvp nvp_target_debug_reason[];
-
 enum target_endianess
 {
 	TARGET_ENDIAN_UNKNOWN = 0,
@@ -165,6 +163,8 @@ static inline const char *target_name(struct target *target)
 	return target->cmd_name;
 }
 
+const char *debug_reason_name(struct target *t);
+
 enum target_event
 {
 	/* LD historical names

commit 19ad7f828ba36f398f52749c2f33e25a3ea78ac2
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:08 2009 -0800

    ARM: don't clone arm_arch_state() code
    
    Have various ARM cores delegate to arm_arch_state() to display
    basic information, instead of duplicating that logic.
    
    This shrinks the code, makes them all report when semihosting
    is active, and highlights which data are specific to this core.
    (Like ARM720 not having separate instruction and data caches.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 48f0358..84c66b8 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -235,14 +235,8 @@ static int arm720t_arch_state(struct target *target)
 
 	armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, Cache: %s",
 			 state[arm720t->armv4_5_mmu.mmu_enabled],
 			 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 217c63c..c5b7c88 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -449,14 +449,8 @@ int arm920t_arch_state(struct target *target)
 
 	armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 			 state[arm920t->armv4_5_mmu.mmu_enabled],
 			 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index c7ef708..4ac92a2 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -505,14 +505,8 @@ int arm926ejs_arch_state(struct target *target)
 
 	armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 			 state[arm926ejs->armv4_5_mmu.mmu_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 61994dc..ac697da 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -865,15 +865,8 @@ static int xscale_arch_state(struct target *target)
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s"
-			"%s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
 			 state[xscale->armv4_5_mmu.mmu_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],

commit 927ae6899df12e4667d181575cc0494bf12ff209
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:07 2009 -0800

    User's Guide: add quickie setup notes
    
    Add a brief "setup with no customization" note showing the
    how easily things can work if standard OpenOCD config scripts
    already exist.  We've had some new users comment that this
    information is needlessly hard to find, so that starting to
    use OpenOCD is more difficult than it should be.
    
    Plus describe a few other issues that come up when setting
    up an OpenOCD server.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index b0aa7c6..ef395ea 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -501,8 +501,43 @@ Configuration files and scripts are searched for in
 @end enumerate
 The first found file with a matching file name will be used.
 
+@section Simple setup, no customization
+
+In the best case, you can use two scripts from one of the script
+libraries, hook up your JTAG adapter, and start the server ... and
+your JTAG setup will just work "out of the box".  Always try to
+start by reusing those scripts, but assume you'll need more
+customization even if this works.  @xref{OpenOCD Project Setup}.
+
+If you find a script for your JTAG adapter, and for your board or
+target, you may be able to hook up your JTAG adapter then start
+the server like:
+
+@example
+openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
+@end example
+
+You might also need to configure which reset signals are present,
+using @option{-c 'reset_config trst_and_srst'} or something similar.
+If all goes well you'll see output something like
+
+@example
+Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
+For bug reports, read
+        http://openocd.berlios.de/doc/doxygen/bugs.html
+Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
+       (mfg: 0x23b, part: 0xba00, ver: 0x3)
+@end example
+
+Seeing that "tap/device found" message, and no warnings, means
+the JTAG communication is working.  That's a key milestone, but
+you'll probably need more project-specific setup.
+
+@section What OpenOCD does as it starts
+
 OpenOCD starts by processing the configuration commands provided
-on the command line or in @file{openocd.cfg}.
+on the command line or, if there were no @option{-c command} or
+@option{-f file.cfg} options given, in @file{openocd.cfg}.
 @xref{Configuration Stage}.
 At the end of the configuration stage it verifies the JTAG scan
 chain defined using those commands; your configuration should
@@ -548,6 +583,8 @@ just connecting the JTAG adapter hardware (dongle) to your development board
 and then starting the OpenOCD server.
 You also need to configure that server so that it knows
 about that adapter and board, and helps your work.
+You may also want to connect OpenOCD to GDB, possibly
+using Eclipse or some other GUI.
 
 @section Hooking up the JTAG Adapter
 
@@ -604,7 +641,8 @@ you are using to run OpenOCD.
 For Ethernet, consult the documentation and your network administrator.
 
 For USB based JTAG adapters you have an easy sanity check at this point:
-does the host operating system see the JTAG adapter?
+does the host operating system see the JTAG adapter?  If that host is an
+MS-Windows host, you'll need to install a driver before OpenOCD works.
 
 @item @emph{Connect the adapter's power supply, if needed.}
 This step is primarily for non-USB adapters,
@@ -629,6 +667,7 @@ A simple way to organize them all involves keeping a
 single directory for your work with a given board.
 When you start OpenOCD from that directory,
 it searches there first for configuration files, scripts,
+files accessed through semihosting,
 and for code you upload to the target board.
 It is also the natural place to write files,
 such as log files and data you download from the board.

commit 0a1b7dcfc40385f09b5eb088cd97d6ff25a5816d
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:54:13 2009 -0800

    ARM: use <target/arm.h> not armv4_5.h
    
    Move most declarations in <target/armv4_5.h> to <target/arm.h>
    and update users.
    
    What's left in the older file is stuff that I think should be
    removed ... the old register cache access stuff, which makes it
    awkward to support microcontroller profile (Cortex-M) cores.
    
    The armv4_5_run_algorithm() declaration was moved too, even
    though it's not yet as generic as it probably ought to be.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c
index 4c74675..0cd39c0 100644
--- a/src/flash/nand/arm_io.c
+++ b/src/flash/nand/arm_io.c
@@ -27,7 +27,7 @@
 #include "core.h"
 #include "arm_io.h"
 #include <helper/binarybuffer.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/algorithm.h>
 
 
diff --git a/src/flash/nand/orion.c b/src/flash/nand/orion.c
index 01d4a08..b46ffae 100644
--- a/src/flash/nand/orion.c
+++ b/src/flash/nand/orion.c
@@ -28,7 +28,7 @@
 
 #include "imp.h"
 #include "arm_io.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
 
 
 struct orion_nand_controller
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index 57018bb..211b54e 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -27,7 +27,7 @@
 #include <helper/binarybuffer.h>
 #include <helper/time_support.h>
 #include <target/algorithm.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 
 
 static int aduc702x_build_sector_list(struct flash_bank *bank);
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 1ab9341..71270b9 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -26,7 +26,7 @@
 #include "imp.h"
 #include "cfi.h"
 #include "non_cfi.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index ce74bbb..13dd731 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -26,7 +26,7 @@
 #include "imp.h"
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/image.h>
 
 
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index ef693e9..040097a 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -26,7 +26,7 @@
 
 #include "imp.h"
 #include "str7x.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index bd7bf7a..f1d5d15 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -97,6 +97,7 @@ MIPS32_SRC = \
 
 noinst_HEADERS = \
 	algorithm.h \
+	arm.h \
 	arm_dpm.h \
 	arm_jtag.h \
 	arm_adi_v5.h \
diff --git a/src/target/armv4_5.h b/src/target/arm.h
similarity index 62%
copy from src/target/armv4_5.h
copy to src/target/arm.h
index c8882ed..00dbe2d 100644
--- a/src/target/armv4_5.h
+++ b/src/target/arm.h
@@ -1,36 +1,45 @@
-/***************************************************************************
- *   Copyright (C) 2005 by Dominic Rath                                    *
- *   Dom...@gm...                                                   *
- *                                                                         *
- *   Copyright (C) 2008 by Spencer Oliver                                  *
- *   sp...@sp...                                                  *
- *                                                                         *
- *   Copyright (C) 2009 by Øyvind Harboe                                   *
- *   oyv...@zy...                                               *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-#ifndef ARMV4_5_H
-#define ARMV4_5_H
+/*
+ * Copyright (C) 2005 by Dominic Rath
+ * Dom...@gm...
+ *
+ * Copyright (C) 2008 by Spencer Oliver
+ * sp...@sp...
+ *
+ * Copyright (C) 2009 by Øyvind Harboe
+ * oyv...@zy...
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef ARM_H
+#define ARM_H
 
 #include <target/target.h>
 #include <helper/command.h>
 
 
 /**
+ * @file
+ * Holds the interface to ARM cores.
+ *
+ * At this writing, only "classic ARM" cores built on the ARMv4 register
+ * and mode model are supported.  The Thumb2-only microcontroller profile
+ * support has not yet been integrated, affecting Cortex-M parts.
+ */
+
+/**
  * These numbers match the five low bits of the *PSR registers on
  * "classic ARM" processors, which build on the ARMv4 processor
  * modes and register set.
@@ -60,22 +69,6 @@ enum arm_state {
 
 extern const char *arm_state_strings[];
 
-/* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
- * index into the armv4_5_core_reg_map array.  Its remaining users are
- * remnants which could as easily walk * the register cache directly as
- * use the expensive ARMV4_5_CORE_REG_MODE() macro.
- */
-int arm_mode_to_number(enum arm_mode mode);
-enum arm_mode armv4_5_number_to_mode(int number);
-
-extern const int armv4_5_core_reg_map[8][17];
-
-#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
-		cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
-
-/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
-enum { ARMV4_5_CPSR = 31, };
-
 #define ARM_COMMON_MAGIC 0x0A450A45
 
 /**
@@ -85,8 +78,7 @@ enum { ARMV4_5_CPSR = 31, };
  * Cortex-M series cores do not support as many core states or shadowed
  * registers as traditional ARM cores, and only support Thumb2 instructions.
  */
-struct arm
-{
+struct arm {
 	int common_magic;
 	struct reg_cache *core_cache;
 
@@ -168,16 +160,14 @@ static inline bool is_arm(struct arm *arm)
 	return arm && arm->common_magic == ARM_COMMON_MAGIC;
 }
 
-struct arm_algorithm
-{
+struct arm_algorithm {
 	int common_magic;
 
 	enum arm_mode core_mode;
 	enum arm_state core_state;
 };
 
-struct arm_reg
-{
+struct arm_reg {
 	int num;
 	enum arm_mode mode;
 	struct target *target;
@@ -187,14 +177,15 @@ struct arm_reg
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 
+extern const struct command_registration arm_command_handlers[];
+
 int arm_arch_state(struct target *target);
 int arm_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
 
-extern const struct command_registration arm_command_handlers[];
-
 int arm_init_arch_info(struct target *target, struct arm *arm);
 
+/* REVISIT rename this once it's usable by ARMv7-M */
 int armv4_5_run_algorithm(struct target *target,
 		int num_mem_params, struct mem_param *mem_params,
 		int num_reg_params, struct reg_param *reg_params,
@@ -212,4 +203,4 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;
 
-#endif /* ARMV4_5_H */
+#endif /* ARM_H */
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 421f8d1..bce5bd9 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -23,7 +23,7 @@
 #ifndef ARM11_H
 #define ARM11_H
 
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/arm_dpm.h>
 
 #define ARM11_TAP_DEFAULT			TAP_INVALID
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 03071df..64a99fb 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -39,6 +39,7 @@
 #include "arm_semihosting.h"
 #include "algorithm.h"
 #include "register.h"
+#include "armv4_5.h"
 
 
 /**
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 7555bec..bce17ef 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -29,7 +29,7 @@
 #ifndef ARM7_9_COMMON_H
 #define ARM7_9_COMMON_H
 
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/arm_jtag.h>
 
 #define	ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 406e30a..bd9c5d1 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"		/* REVISIT to become arm.h */
+#include "arm.h"
 #include "arm_dpm.h"
 #include <jtag/jtag.h>
 #include "register.h"
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index d448d54..f4244c8 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -34,6 +34,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "register.h"
 #include "arm_semihosting.h"
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 443f29b..908c613 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -24,6 +24,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_disassembler.h"
 #include "arm_simulator.h"
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 7fec97b..dce6d6a 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,6 +27,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_jtag.h"
 #include "breakpoints.h"
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index c8882ed..bacdb72 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -26,39 +26,10 @@
 #ifndef ARMV4_5_H
 #define ARMV4_5_H
 
-#include <target/target.h>
-#include <helper/command.h>
-
-
-/**
- * These numbers match the five low bits of the *PSR registers on
- * "classic ARM" processors, which build on the ARMv4 processor
- * modes and register set.
+/* This stuff "knows" that its callers aren't talking
+ * to microcontroller profile (current Cortex-M) parts.
+ * We want to phase it out so core code can be shared.
  */
-enum arm_mode {
-	ARM_MODE_USR = 16,
-	ARM_MODE_FIQ = 17,
-	ARM_MODE_IRQ = 18,
-	ARM_MODE_SVC = 19,
-	ARM_MODE_ABT = 23,
-	ARM_MODE_MON = 26,
-	ARM_MODE_UND = 27,
-	ARM_MODE_SYS = 31,
-	ARM_MODE_ANY = -1
-};
-
-const char *arm_mode_name(unsigned psr_mode);
-bool is_arm_mode(unsigned psr_mode);
-
-/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
-enum arm_state {
-	ARM_STATE_ARM,
-	ARM_STATE_THUMB,
-	ARM_STATE_JAZELLE,
-	ARM_STATE_THUMB_EE,
-};
-
-extern const char *arm_state_strings[];
 
 /* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
  * index into the armv4_5_core_reg_map array.  Its remaining users are
@@ -76,140 +47,4 @@ extern const int armv4_5_core_reg_map[8][17];
 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
 enum { ARMV4_5_CPSR = 31, };
 
-#define ARM_COMMON_MAGIC 0x0A450A45
-
-/**
- * Represents a generic ARM core, with standard application registers.
- *
- * There are sixteen application registers (including PC, SP, LR) and a PSR.
- * Cortex-M series cores do not support as many core states or shadowed
- * registers as traditional ARM cores, and only support Thumb2 instructions.
- */
-struct arm
-{
-	int common_magic;
-	struct reg_cache *core_cache;
-
-	/** Handle to the CPSR; valid in all core modes. */
-	struct reg *cpsr;
-
-	/** Handle to the SPSR; valid only in core modes with an SPSR. */
-	struct reg *spsr;
-
-	/** Support for arm_reg_current() */
-	const int *map;
-
-	/**
-	 * Indicates what registers are in the ARM state core register set.
-	 * ARM_MODE_ANY indicates the standard set of 37 registers,
-	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
-	 * more registers are shadowed, for "Secure Monitor" mode.
-	 */
-	enum arm_mode core_type;
-
-	/** Record the current core mode: SVC, USR, or some other mode. */
-	enum arm_mode core_mode;
-
-	/** Record the current core state: ARM, Thumb, or otherwise. */
-	enum arm_state core_state;
-
-	/** Flag reporting unavailability of the BKPT instruction. */
-	bool is_armv4;
-
-	/** Flag reporting whether semihosting is active. */
-	bool is_semihosting;
-
-	/** Value to be returned by semihosting SYS_ERRNO request. */
-	int semihosting_errno;
-
-	/** Backpointer to the target. */
-	struct target *target;
-
-	/** Handle for the debug module, if one is present. */
-	struct arm_dpm *dpm;
-
-	/** Handle for the Embedded Trace Module, if one is present. */
-	struct etm_context *etm;
-
-	/* FIXME all these methods should take "struct arm *" not target */
-
-	/** Retrieve all core registers, for display. */
-	int (*full_context)(struct target *target);
-
-	/** Retrieve a single core register. */
-	int (*read_core_reg)(struct target *target, struct reg *reg,
-			int num, enum arm_mode mode);
-	int (*write_core_reg)(struct target *target, struct reg *reg,
-			int num, enum arm_mode mode, uint32_t value);
-
-	/** Read coprocessor register.  */
-	int (*mrc)(struct target *target, int cpnum,
-			uint32_t op1, uint32_t op2,
-			uint32_t CRn, uint32_t CRm,
-			uint32_t *value);
-
-	/** Write coprocessor register.  */
-	int (*mcr)(struct target *target, int cpnum,
-			uint32_t op1, uint32_t op2,
-			uint32_t CRn, uint32_t CRm,
-			uint32_t value);
-
-	void *arch_info;
-};
-
-/** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target *target)
-{
-	return target->arch_info;
-}
-
-static inline bool is_arm(struct arm *arm)
-{
-	return arm && arm->common_magic == ARM_COMMON_MAGIC;
-}
-
-struct arm_algorithm
-{
-	int common_magic;
-
-	enum arm_mode core_mode;
-	enum arm_state core_state;
-};
-
-struct arm_reg
-{
-	int num;
-	enum arm_mode mode;
-	struct target *target;
-	struct arm *armv4_5_common;
-	uint32_t value;
-};
-
-struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
-
-int arm_arch_state(struct target *target);
-int arm_get_gdb_reg_list(struct target *target,
-		struct reg **reg_list[], int *reg_list_size);
-
-extern const struct command_registration arm_command_handlers[];
-
-int arm_init_arch_info(struct target *target, struct arm *arm);
-
-int armv4_5_run_algorithm(struct target *target,
-		int num_mem_params, struct mem_param *mem_params,
-		int num_reg_params, struct reg_param *reg_params,
-		uint32_t entry_point, uint32_t exit_point,
-		int timeout_ms, void *arch_info);
-
-int arm_checksum_memory(struct target *target,
-		uint32_t address, uint32_t count, uint32_t *checksum);
-int arm_blank_check_memory(struct target *target,
-		uint32_t address, uint32_t count, uint32_t *blank);
-
-void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
-struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
-
-extern struct reg arm_gdb_dummy_fp_reg;
-extern struct reg arm_gdb_dummy_fps_reg;
-
 #endif /* ARMV4_5_H */
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 24ec819..663e5d9 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -20,7 +20,7 @@
 #define ARMV7A_H
 
 #include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/armv4_5_mmu.h>
 #include <target/armv4_5_cache.h>
 #include <target/arm_dpm.h>
@@ -114,22 +114,6 @@ target_to_armv7a(struct target *target)
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS	0xFB8
 
-struct armv7a_algorithm
-{
-	int common_magic;
-
-	enum arm_mode core_mode;
-	enum arm_state core_state;
-};
-
-struct armv7a_core_reg
-{
-	int num;
-	enum arm_mode mode;
-	struct target *target;
-	struct armv7a_common *armv7a_common;
-};
-
 int armv7a_arch_state(struct target *target);
 struct reg_cache *armv7a_build_reg_cache(struct target *target,
 		struct armv7a_common *armv7a_common);
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index c60ab8c..f662e16 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -27,7 +27,7 @@
 #define ARMV7M_COMMON_H
 
 #include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 
 /* define for enabling armv7 gdb workarounds */
 #if 1
diff --git a/src/target/etb.c b/src/target/etb.c
index bc0e1bf..3113eca 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "etm.h"
 #include "etb.h"
 #include "register.h"
diff --git a/src/target/etm.c b/src/target/etm.c
index b45fcf5..3aace81 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "etm.h"
 #include "etb.h"
 #include "image.h"
diff --git a/src/target/etm_dummy.c b/src/target/etm_dummy.c
index 647774f..19a078f 100644
--- a/src/target/etm_dummy.c
+++ b/src/target/etm_dummy.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "etm_dummy.h"
 
 
diff --git a/src/target/oocd_trace.c b/src/target/oocd_trace.c
index ac79f18..ae3a5df 100644
--- a/src/target/oocd_trace.c
+++ b/src/target/oocd_trace.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "oocd_trace.h"
 
 /*
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 816579a..61994dc 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -37,6 +37,7 @@
 #include "register.h"
 #include "image.h"
 #include "arm_opcodes.h"
+#include "armv4_5.h"
 
 
 /*
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 43edeec..97038d8 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -23,7 +23,7 @@
 #ifndef XSCALE_H
 #define XSCALE_H
 
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/armv4_5_mmu.h>
 #include <target/trace.h>
 

commit 0529c14bfeb113ee37f4d961f9309102d57a1e39
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:54:13 2009 -0800

    ARM: rename some generic routines
    
    Rename some (mostly) generic ARM functions:
    
        armv4_5_arch_state()       --> arm_arch_state()
        armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list()
        armv4_5_init_arch_info()   --> arm_init_arch_info()
    
    Cores using the microcontroller profile may want a different
    arch_state() routine though.
    
    (Also fix strange indentation in arm_arch_state: use tabs only!
    And update a call to it, removing assignment-in-conditional.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 7868c23..7b29f53 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -373,7 +373,7 @@ static int arm11_arch_state(struct target *target)
 	struct arm11_common *arm11 = target_to_arm11(target);
 	int retval;
 
-	retval = armv4_5_arch_state(target);
+	retval = arm_arch_state(target);
 
 	/* REVISIT also display ARM11-specific MMU and cache status ... */
 
@@ -1150,7 +1150,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 	if (!arm11)
 		return ERROR_FAIL;
 
-	armv4_5_init_arch_info(target, &arm11->arm);
+	arm_init_arch_info(target, &arm11->arm);
 
 	arm11->jtag_info.tap = target->tap;
 	arm11->jtag_info.scann_size = 5;
@@ -1387,7 +1387,7 @@ struct target_type arm11_target = {
 	.deassert_reset =	arm11_deassert_reset,
 	.soft_reset_halt =	arm11_soft_reset_halt,
 
-	.get_gdb_reg_list =	armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list =	arm_get_gdb_reg_list,
 
 	.read_memory =		arm11_read_memory,
 	.write_memory =		arm11_write_memory,
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 14d2184..48f0358 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -557,7 +557,7 @@ struct target_type arm720t_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm720t_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm720t_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 905e108..03071df 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2885,7 +2885,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 	armv4_5->write_core_reg = arm7_9_write_core_reg;
 	armv4_5->full_context = arm7_9_full_context;
 
-	if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+	retval = arm_init_arch_info(target, armv4_5);
+	if (retval != ERROR_OK)
 		return retval;
 
 	return target_register_timer_callback(arm7_9_handle_target_request,
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index d204f95..d576d07 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -720,7 +720,7 @@ struct target_type arm7tdmi_target =
 	.name = "arm7tdmi",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -732,7 +732,7 @@ struct target_type arm7tdmi_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 1fcae43..217c63c 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -1453,7 +1453,7 @@ struct target_type arm920t_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm920t_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm920t_read_memory,
 	.write_memory = arm920t_write_memory,
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d882050..c7ef708 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -801,7 +801,7 @@ struct target_type arm926ejs_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm926ejs_write_memory,
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index e4bfe57..82be738 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -252,7 +252,7 @@ struct target_type arm966e_target =
 	.name = "arm966e",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -264,7 +264,7 @@ struct target_type arm966e_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 05f0246..301412c 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -937,7 +937,7 @@ struct target_type arm9tdmi_target =
 	.name = "arm9tdmi",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -949,7 +949,7 @@ struct target_type arm9tdmi_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index ad89b2f..7fec97b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -581,7 +581,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
 	return cache;
 }
 
-int armv4_5_arch_state(struct target *target)
+int arm_arch_state(struct target *target)
 {
 	struct arm *armv4_5 = target_to_arm(target);
 
@@ -593,11 +593,11 @@ int armv4_5_arch_state(struct target *target)
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+			arm_state_strings[armv4_5->core_state],
+			Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 					target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
+			arm_mode_name(armv4_5->core_mode),
+			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
 					0, 32),
 			armv4_5->is_semihosting ? ", semihosting" : "");
@@ -972,7 +972,8 @@ const struct command_registration arm_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
+int arm_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size)
 {
 	struct arm *armv4_5 = target_to_arm(target);
 	int i;
@@ -1419,7 +1420,7 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
+int arm_init_arch_info(struct target *target, struct arm *armv4_5)
 {
 	target->arch_info = armv4_5;
 	armv4_5->target = target;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 4b2ccf8..c8882ed 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -187,13 +187,13 @@ struct arm_reg
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 
-int armv4_5_arch_state(struct target *target);
-int armv4_5_get_gdb_reg_list(struct target *target,
+int arm_arch_state(struct target *target);
+int arm_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
 
 extern const struct command_registration arm_command_handlers[];
 
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
+int arm_init_arch_info(struct target *target, struct arm *arm);
 
 int armv4_5_run_algorithm(struct target *target,
 		int num_mem_params, struct mem_param *mem_params,
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 3cc86bc..31538c2 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -100,7 +100,7 @@ int armv7a_arch_state(struct target *target)
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	armv4_5_arch_state(target);
+	arm_arch_state(target);
 
 	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 		 state[armv7a->armv4_5_mmu.mmu_enabled],
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 1ac0a30..593e895 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1603,7 +1603,7 @@ static int cortex_a8_init_arch_info(struct target *target,
 //	arm7_9->handle_target_request = cortex_a8_handle_target_request;
 
 	/* REVISIT v7a setup should be in a v7a-specific routine */
-	armv4_5_init_arch_info(target, armv4_5);
+	arm_init_arch_info(target, armv4_5);
 	armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
 	target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
@@ -1686,7 +1686,7 @@ struct target_type cortexa8_target = {
 	.deassert_reset = cortex_a8_deassert_reset,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = cortex_a8_read_memory,
 	.write_memory = cortex_a8_write_memory,
diff --git a/src/target/fa526.c b/src/target/fa526.c
index 9c01ec7..7c6cae6 100644
--- a/src/target/fa526.c
+++ b/src/target/fa526.c
@@ -370,7 +370,7 @@ struct target_type fa526_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm920t_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm920t_read_memory,
 	.write_memory = arm920t_write_memory,
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index c912137..19ed0cd 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -694,7 +694,7 @@ struct target_type feroceon_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm926ejs_write_memory,
@@ -721,7 +721,7 @@ struct target_type dragonite_target =
 	.name = "dragonite",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -733,7 +733,7 @@ struct target_type dragonite_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/xscale.c b/src/target/xscale.c
index b36d9fd..816579a 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2993,7 +2993,7 @@ static int xscale_init_arch_info(struct target *target,
 	armv4_5->write_core_reg = xscale_write_core_reg;
 	armv4_5->full_context = xscale_full_context;
 
-	armv4_5_init_arch_info(target, armv4_5);
+	arm_init_arch_info(target, armv4_5);
 
 	xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
 	xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
@@ -3722,7 +3722,7 @@ struct target_type xscale_target =
 	.deassert_reset = xscale_deassert_reset,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = xscale_read_memory,
 	.read_phys_memory = xscale_read_phys_memory,

commit a4a2808c2a849eddd5d7d454c048ffdfd89ca9c6
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:54:12 2009 -0800

    ARM: move opcode macros to <target/arm_opcodes.h>
    
    Move the ARM opcode macros from <target/armv4_5.h>, and a few
    Thumb2 ones from <target/armv7m.h>, to more appropriate homes
    in a new <target/arm_opcodes.h> file.
    
    Removed duplicate opcodes from that v7m/Thumb2 set.  Protected
    a few macro argument references by adding missing parentheses.
    
    Tightening up some of the line lengths turned up a curious artifact:
    the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
    There's currently no explanation for why it's done that way...
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 0caf3e0..18896f7 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -29,6 +29,7 @@
 #include "lpc2000.h"
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
+#include <target/arm_opcodes.h>
 #include <target/armv7m.h>
 
 
@@ -263,8 +264,10 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
 		switch(lpc2000_info->variant)
 		{
 			case lpc1700:
-				target_buffer_set_u32(target, jump_gate, ARMV7M_T_BX(12));
-				target_buffer_set_u32(target, jump_gate + 4, ARMV7M_T_B(0xfffffe));
+				target_buffer_set_u32(target, jump_gate,
+						ARMV4_5_T_BX(12));
+				target_buffer_set_u32(target, jump_gate + 4,
+						ARMV4_5_T_B(0xfffffe));
 				break;
 			case lpc2000_v1:
 			case lpc2000_v2:
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 0486b04..7868c23 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -34,6 +34,7 @@
 #include "target_type.h"
 #include "algorithm.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 #if 0
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 207db78..14d2184 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -28,6 +28,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index fffc632..d204f95 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -30,6 +30,7 @@
 #include "arm7tdmi.h"
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 6a005d6..1fcae43 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -25,6 +25,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index cacb942..d882050 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -28,6 +28,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 9fe513c..e4bfe57 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -26,6 +26,7 @@
 
 #include "arm966e.h"
 #include "target_type.h"
+#include "arm_opcodes.h"
 
 
 #if 0
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 09199c7..05f0246 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -30,6 +30,7 @@
 #include "arm9tdmi.h"
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 1ddf530..406e30a 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -27,6 +27,7 @@
 #include "register.h"
 #include "breakpoints.h"
 #include "target_type.h"
+#include "arm_opcodes.h"
 
 
 /**
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
new file mode 100644
index 0000000..b3b5143
--- /dev/null
+++ b/src/target/arm_opcodes.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2005 by Dominic Rath
+ * Dom...@gm...
+ *
+ * Copyright (C) 2008 by Spencer Oliver
+ * sp...@sp...
+ *
+ * Copyright (C) 2009 by Øyvind Harboe
+ * oyv...@zy...
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ARM_OPCODES_H
+#define __ARM_OPCODES_H
+
+/* ARM mode instructions */
+
+/* Store multiple increment after
+ * Rn: base register
+ * List: for each bit in list: store register
+ * S: in priviledged mode: store user-mode registers
+ * W = 1: update the base register. W = 0: leave the base register untouched
+ */
+#define ARMV4_5_STMIA(Rn, List, S, W) \
+	(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+
+/* Load multiple increment after
+ * Rn: base register
+ * List: for each bit in list: store register
+ * S: in priviledged mode: store user-mode registers
+ * W = 1: update the base register. W = 0: leave the base register untouched
+ */
+#define ARMV4_5_LDMIA(Rn, List, S, W) \
+	(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+
+/* MOV r8, r8 */
+#define ARMV4_5_NOP					(0xe1a08008)
+
+/* Move PSR to general purpose register
+ * R = 1: SPSR R = 0: CPSR
+ * Rn: target register
+ */
+#define ARMV4_5_MRS(Rn, R)	(0xe10f0000 | ((R) << 22) | ((Rn) << 12))
+
+/* Store register
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STR(Rd, Rn)	(0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Load register
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDR(Rd, Rn)	(0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Move general purpose register to PSR
+ * R = 1: SPSR R = 0: CPSR
+ * Field: Field mask
+ * 1: control field 2: extension field 4: status field 8: flags field
+ * Rm: source register
+ */
+#define ARMV4_5_MSR_GP(Rm, Field, R) \
+	(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
+#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
+	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
+
+/* Load Register Halfword Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRH_IP(Rd, Rn)	(0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Load Register Byte Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Store register Halfword Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRH_IP(Rd, Rn)	(0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Store register Byte Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRB_IP(Rd, Rn)	(0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Branch (and Link)
+ * Im: Branch target (left-shifted by 2 bits, added to PC)
+ * L: 1: branch and link 0: branch only
+ */
+#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
+
+/* Branch and exchange (ARM state)
+ * Rm: register holding branch target address
+ */
+#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
+
+/* Move to ARM register from coprocessor
+ * CP: Coprocessor number
+ * op1: Coprocessor opcode
+ * Rd: destination register
+ * CRn: first coprocessor operand
+ * CRm: second coprocessor operand
+ * op2: Second coprocessor opcode
+ */
+#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
+	(0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
+	| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+
+/* Move to coprocessor from ARM register
+ * CP: Coprocessor number
+ * op1: Coprocessor opcode
+ * Rd: destination register
+ * CRn: first coprocessor operand
+ * CRm: second coprocessor operand
+ * op2: Second coprocessor opcode
+ */
+#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
+	(0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
+	| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+
+/* Breakpoint instruction (ARMv5)
+ * Im: 16-bit immediate
+ */
+#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
+
+
+/* Thumb mode instructions
+ *
+ * FIXME there must be some reason all these opcodes are 32-bits
+ * not 16-bits ... this should get either an explanatory comment,
+ * or be changed not to duplicate the opcode.
+ */
+
+/* Store register (Thumb mode)
+ * Rd: source register
+ * Rn: base register
+ */
+#define ARMV4_5_T_STR(Rd, Rn) \
+	((0x6000 | (Rd) | ((Rn) << 3)) | \
+	((0x6000 | (Rd) | ((Rn) << 3)) << 16))
+
+/* Load register (Thumb state)
+ * Rd: destination register
+ * Rn: base register
+ */
+#define ARMV4_5_T_LDR(Rd, Rn) \
+	((0x6800 | ((Rn) << 3) | (Rd)) \
+	| ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
+
+/* Load multiple (Thumb state)
+ * Rn: base register
+ * List: for each bit in list: store register
+ */
+#define ARMV4_5_T_LDMIA(Rn, List) \
+	((0xc800 | ((Rn) << 8) | (List)) \
+	| ((0xc800 | ((Rn) << 8) | (List)) << 16))
+
+/* Load register with PC relative addressing
+ * Rd: register to load
+ */
+#define ARMV4_5_T_LDR_PCREL(Rd) \
+	((0x4800 | ((Rd) << 8)) \
+	| ((0x4800 | ((Rd) << 8)) << 16))
+
+/* Move hi register (Thumb mode)
+ * Rd: destination register
+ * Rm: source register
+ */
+#define ARMV4_5_T_MOV(Rd, Rm) \
+	((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
+		(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
+	| ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
+		(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
+
+/* No operation (Thumb mode)
+ * NOTE:  this is "MOV r8, r8" ... Thumb2 adds two
+ * architected NOPs, 16-bit and 32-bit.
+ */
+#define ARMV4_5_T_NOP	(0x46c0 | (0x46c0 << 16))
+
+/* Move immediate to register (Thumb state)
+ * Rd: destination register
+ * Im: 8-bit immediate value
+ */
+#define ARMV4_5_T_MOV_IM(Rd, Im) \
+	((0x2000 | ((Rd) << 8) | (Im)) \
+	| ((0x2000 | ((Rd) << 8) | (Im)) << 16))
+
+/* Branch and Exchange
+ * Rm: register containing branch target
+ */
+#define ARMV4_5_T_BX(Rm) \
+	((0x4700 | ((Rm) << 3)) \
+	| ((0x4700 | ((Rm) << 3)) << 16))
+
+/* Branch (Thumb state)
+ * Imm: Branch target
+ */
+#define ARMV4_5_T_B(Imm) \
+	((0xe000 | (Imm)) \
+	| ((0xe000 | (Imm)) << 16))
+
+/* Breakpoint instruction (ARMv5) (Thumb state)
+ * Im: 8-bit immediate
+ */
+#define ARMV5_T_BKPT(Im) \
+	((0xbe00 | (Im)) \
+	| ((0xbe00 | (Im)) << 16))
+
+/* Move to Register from Special Register
+ *	32 bit Thumb2 instruction
+ * Rd: destination register
+ * SYSm: source special register
+ */
+#define ARM_T2_MRS(Rd, SYSm) \
+	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
+
+/* Move from Register from ...
 
[truncated message content]