This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via acd6d3399486110e69db8d5ec752e10067c29ad0 (commit)
from 146e841fc920e1caea702ef42e2088244b9b8464 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit acd6d3399486110e69db8d5ec752e10067c29ad0
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 10:11:31 2009 -0800
User's Guide: more semihosting info
List it in the concept index, in the section about target software
changes a project might want to consider, and in the section about
debug messaging.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4d13f07..b6be87e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -873,6 +873,20 @@ handling issues like:
@itemize @bullet
+@item @b{ARM Semihosting}...
+@cindex ARM semihosting
+When linked with a special runtime library provided with many
+toolchains@footnote{See chapter 8 "Semihosting" in
+@uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
+ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
+The CodeSourcery EABI toolchain also includes a semihosting library.},
+your target code can use I/O facilities on the debug host. That library
+provides a small set of system calls which are handled by OpenOCD.
+It can let the debugger provide your system console and a file system,
+helping with early debugging or providing a more capable environment
+for sometimes-complex tasks like installing system firmware onto
+NAND or SPI flash.
+
@item @b{ARM Wait-For-Interrupt}...
Many ARM chips synchronize the JTAG clock using the core clock.
Low power states which stop that core clock thus prevent JTAG access.
@@ -5675,6 +5689,7 @@ speeds, like the 32kHz startup clock of an AT91RM9200.
@end deffn
@deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
+@cindex ARM semihosting
Display status of semihosting, after optionally changing that status.
Semihosting allows for code executing on an ARM target to use the
@@ -6049,8 +6064,12 @@ This finishes by listing the current vector catch configuration.
@cindex tracing
@cindex libdcc
@cindex DCC
-OpenOCD can process certain requests from target software. Currently
-@command{target_request debugmsgs}
+OpenOCD can process certain requests from target software, when
+the target uses appropriate libraries.
+The most powerful mechanism is semihosting, but there is also
+a lighter weight mechanism using only the DCC channel.
+
+Currently @command{target_request debugmsgs}
is supported only for @option{arm7_9} and @option{cortex_m3} cores.
These messages are received as part of target polling, so
you need to have @command{poll on} active to receive them.
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 23 +++++++++++++++++++++--
1 files changed, 21 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
