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From: David B. <dbr...@us...> - 2009-11-14 01:59:39
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This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
via ecab0cfe25600ad13c174b78a637515943cc870a (commit)
via 817bf743023de7fea901e89157da57b90c7c326c (commit)
via 44d6a531f7ad07ec20962fe1c61bb7787f2c7cf5 (commit)
from aafb916bea1153b8d2f4706e4a62628f49741133 (commit)
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- Log -----------------------------------------------------------------
commit ecab0cfe25600ad13c174b78a637515943cc870a
Author: David Brownell <dbr...@us...>
Date: Fri Nov 13 16:58:14 2009 -0800
ARM11: ETM + ETB support
Kick in ETM (and ETB) support for ARM11. Tested on OMAP 2420,
so update that configuration. (That's an ARM1136ejs, ETB,
OpenGL ES1.1, C55x DSP, etc.)
Also update the other ARM11 ETM + ETB targets in the tree
to set up these modules. (Not tested.)
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index b30e518..7a30bc7 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1898,6 +1898,20 @@ static int arm11_examine(struct target *target)
if (retval != ERROR_OK)
return retval;
+ /* ETM on ARM11 still uses original scanchain 6 access mode */
+ if (arm11->arm.etm && !target_was_examined(target)) {
+ *register_get_last_cache_p(&target->reg_cache) =
+ etm_build_reg_cache(target, &arm11->jtag_info,
+ arm11->arm.etm);
+ retval = etm_setup(target);
+ }
+
+ /* FIXME this sets a flag in the (shared) arm11_target structure,
+ * not in the (per-cpu) "target" structure ... so it's clearly
+ * wrong in the case of e.g. two different ARM11 chips on the
+ * same board. (Maybe ARM11 MPCore works though.) Whoever calls
+ * the examine() method should set a target-specific flag...
+ */
target_set_examined(target);
return ERROR_OK;
@@ -2212,5 +2226,5 @@ int arm11_register_commands(struct command_context *cmd_ctx)
arm11_handle_vcr, COMMAND_ANY,
"Control (Interrupt) Vector Catch Register");
- return ERROR_OK;
+ return etm_register_commands(cmd_ctx);
}
diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index 9a2aed3..b613ba6 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -60,3 +60,7 @@ target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg
index b899084..d47abdc 100644
--- a/tcl/target/imx35.cfg
+++ b/tcl/target/imx35.cfg
@@ -48,3 +48,7 @@ target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index a579866..5cf47b2 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -49,7 +49,6 @@ $_TARGETNAME configure -work-area-phys 0x40210000
$_TARGETNAME configure -work-area-size 0x00081000
$_TARGETNAME configure -work-area-backup 0
-# trace setup
-# REVISIT ... as of 12-June-2009, OpenOCD's ETM code can't talk to ARM11 cores.
-#etm config $_TARGETNAME 16 normal full etb
-#etb config $_TARGETNAME $_CHIPNAME.etb
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg
index e451fd6..9137199 100644
--- a/tcl/target/samsung_s3c6410.cfg
+++ b/tcl/target/samsung_s3c6410.cfg
@@ -47,3 +47,7 @@ jtag_ntrst_delay 500
#reset configuration
reset_config trst_and_srst
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
commit 817bf743023de7fea901e89157da57b90c7c326c
Author: David Brownell <dbr...@us...>
Date: Fri Nov 13 16:56:11 2009 -0800
ARM11: revert etmr/etmw commands
These aren't desirable, given "standard" ETM support.
Also remove the now-unused arm11_find_target().
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 4ebe61f..b30e518 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -2076,29 +2076,6 @@ static const uint32_t arm11_coproc_instruction_limits[] =
0xFFFFFFFF, /* value */
};
-static struct arm11_common * arm11_find_target(const char * arg)
-{
- struct jtag_tap * tap;
- struct target * t;
-
- tap = jtag_tap_by_string(arg);
-
- if (!tap)
- return 0;
-
- for (t = all_targets; t; t = t->next)
- {
- if (t->tap != tap)
- continue;
-
- /* if (t->type == arm11_target) */
- if (0 == strcmp(target_get_name(t), "arm11"))
- return t->arch_info;
- }
-
- return 0;
-}
-
static int arm11_mrc_inner(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t *value, bool read)
@@ -2154,58 +2131,6 @@ static int arm11_mcr(struct target *target, int cpnum,
return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
}
-static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
-{
- if (argc != (read ? 2 : 3))
- {
- LOG_ERROR("Invalid number of arguments.");
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- struct arm11_common * arm11 = arm11_find_target(args[0]);
-
- if (!arm11)
- {
- LOG_ERROR("Parameter 1 is not the target name of an ARM11 device.");
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- uint32_t address;
- COMMAND_PARSE_NUMBER(u32, args[1], address);
-
- if (!read)
- {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, args[2], value);
-
- LOG_INFO("ETM write register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
- address, address, value, value);
-
- CHECK_RETVAL(arm11_write_etm(arm11, address, value));
- }
- else
- {
- uint32_t value;
-
- CHECK_RETVAL(arm11_read_etm(arm11, address, &value));
-
- LOG_INFO("ETM read register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
- address, address, value, value);
- }
-
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(arm11_handle_etmr)
-{
- return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, true);
-}
-
-COMMAND_HANDLER(arm11_handle_etmw)
-{
- return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, false);
-}
-
#define ARM11_HANDLER(x) .x = arm11_##x
struct target_type arm11_target = {
@@ -2259,14 +2184,6 @@ int arm11_register_commands(struct command_context *cmd_ctx)
top_cmd = register_command(cmd_ctx, NULL, "arm11",
NULL, COMMAND_ANY, NULL);
- register_command(cmd_ctx, top_cmd, "etmr",
- arm11_handle_etmr, COMMAND_ANY,
- "Read Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address>");
-
- register_command(cmd_ctx, top_cmd, "etmw",
- arm11_handle_etmw, COMMAND_ANY,
- "Write Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address> <value>");
-
/* "hardware_step" is only here to check if the default
* simulate + breakpoint implementation is broken.
* TEMPORARY! NOT DOCUMENTED!
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 6caad0e..e48758f 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -190,9 +190,4 @@ struct arm11_reg_state
int arm11_register_commands(struct command_context *cmd_ctx);
-int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t *value);
-int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value);
-
-
-
#endif /* ARM11_H */
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 40361dc..a95dcdd 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -941,80 +941,3 @@ int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32
return arm11_run_instr_data_finish(arm11);
}
-
-/** Write Embedded Trace Macrocell (ETM) via Scan chain 6
- *
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
- *
- * \param arm11 Target state variable.
- * \param address 7 bit ETM register address
- * \param value Value to be written
- *
- * \return Error status
- *
- * \remarks This is a stand-alone function that executes the JTAG command queue.
- */
-int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value)
-{
- CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
-
- /* Uses INTEST for read and write */
- arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
-
- struct scan_field chain6_fields[3];
-
- uint8_t nRW = 1;
-
- arm11_setup_field(arm11, 32, &value, NULL, chain6_fields + 0);
- arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
- arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
-
- arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
-
- CHECK_RETVAL(jtag_execute_queue());
-
- return ERROR_OK;
-}
-
-/** Read Embedded Trace Macrocell (ETM) via Scan chain 6
- *
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
- *
- * \param arm11 Target state variable.
- * \param address 7 bit ETM register address
- * \param value Pointer that receives value that was read
- *
- * \return Error status
- *
- * \remarks This is a stand-alone function that executes the JTAG command queue.
- */
-int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t * value)
-{
- CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
-
- /* Uses INTEST for read and write */
- arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
-
- struct scan_field chain6_fields[3];
-
- uint8_t nRW = 0;
-
- arm11_setup_field(arm11, 32, NULL, NULL, chain6_fields + 0);
- arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
- arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
-
- arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
-
- /* Data is made available in Capture-DR and shifted out on the next access */
-
- arm11_setup_field(arm11, 32, NULL, value, chain6_fields + 0);
- arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
- arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
-
- arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
-
- CHECK_RETVAL(jtag_execute_queue());
-
- return ERROR_OK;
-}
-
commit 44d6a531f7ad07ec20962fe1c61bb7787f2c7cf5
Author: David Brownell <dbr...@us...>
Date: Fri Nov 13 16:56:11 2009 -0800
iMX2* + ETB targets: hook up ETM and ETB
ARM9 cores with an ETB will have a matching ETM.
Hook them both up by default.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/tcl/target/imx25.cfg b/tcl/target/imx25.cfg
index 6474a85..ead6610 100644
--- a/tcl/target/imx25.cfg
+++ b/tcl/target/imx25.cfg
@@ -38,4 +38,9 @@ if { [info exists SDMATAPID ] } {
jtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
+ -chain-position $_TARGETNAME
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/tcl/target/imx27.cfg b/tcl/target/imx27.cfg
index 039e83c..dabae6d 100644
--- a/tcl/target/imx27.cfg
+++ b/tcl/target/imx27.cfg
@@ -47,3 +47,7 @@ $_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \
#
arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
-----------------------------------------------------------------------
Summary of changes:
src/target/arm11.c | 99 ++++++----------------------------------
src/target/arm11.h | 5 --
src/target/arm11_dbgtap.c | 77 -------------------------------
tcl/target/imx25.cfg | 7 ++-
tcl/target/imx27.cfg | 4 ++
tcl/target/imx31.cfg | 4 ++
tcl/target/imx35.cfg | 4 ++
tcl/target/omap2420.cfg | 7 +--
tcl/target/samsung_s3c6410.cfg | 4 ++
9 files changed, 40 insertions(+), 171 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
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