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From: David B. <dbr...@us...> - 2009-11-06 07:13:45
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- Log -----------------------------------------------------------------
commit 6a0af06bd9f66780d2c3e9f69c40f2b89ad90605
Author: David Brownell <dbr...@us...>
Date: Thu Nov 5 22:04:25 2009 -0800
ARM: shrink offsets
Move various embedded target structs to the beginnings of
their containers ... pretty much the way C++ or Obj-C
would for single inheritance.
This shrinks code that accesses those embedded structs by
letting common offsets use smaller instructions. Sample
before/after sizes (on amd64):
17181 312 0 17493 4455 arm920t.o
16810 312 0 17122 42e2 arm920t.o
Where the "after" is the smaller number, with this patch
over the ones leveraging that embedding knowledge.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm720t.h b/src/target/arm720t.h
index 0689e44..c10cbe1 100644
--- a/src/target/arm720t.h
+++ b/src/target/arm720t.h
@@ -27,9 +27,9 @@
typedef struct arm720t_common_s
{
+ arm7tdmi_common_t arm7tdmi_common;
uint32_t common_magic;
armv4_5_mmu_common_t armv4_5_mmu;
- arm7tdmi_common_t arm7tdmi_common;
uint32_t cp15_control_reg;
uint32_t fsr_reg;
uint32_t far_reg;
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 9eafc1d..9c42b6b 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -39,6 +39,7 @@
*/
typedef struct arm7_9_common_s
{
+ armv4_5_common_t armv4_5_common;
uint32_t common_magic;
arm_jtag_t jtag_info; /**< JTAG information for target */
@@ -107,7 +108,6 @@ typedef struct arm7_9_common_s
void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
- armv4_5_common_t armv4_5_common;
} arm7_9_common_t;
diff --git a/src/target/arm920t.h b/src/target/arm920t.h
index eb66eaa..af0f982 100644
--- a/src/target/arm920t.h
+++ b/src/target/arm920t.h
@@ -27,9 +27,9 @@
typedef struct arm920t_common_s
{
+ arm9tdmi_common_t arm9tdmi_common;
uint32_t common_magic;
armv4_5_mmu_common_t armv4_5_mmu;
- arm9tdmi_common_t arm9tdmi_common;
uint32_t cp15_control_reg;
uint32_t d_fsr;
uint32_t i_fsr;
diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h
index ff811e3..01e3c09 100644
--- a/src/target/arm926ejs.h
+++ b/src/target/arm926ejs.h
@@ -27,9 +27,9 @@
typedef struct arm926ejs_common_s
{
+ arm9tdmi_common_t arm9tdmi_common;
uint32_t common_magic;
armv4_5_mmu_common_t armv4_5_mmu;
- arm9tdmi_common_t arm9tdmi_common;
int (*read_cp15)(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
int (*write_cp15)(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
uint32_t cp15_control_reg;
diff --git a/src/target/arm966e.h b/src/target/arm966e.h
index 710f207..e8346f9 100644
--- a/src/target/arm966e.h
+++ b/src/target/arm966e.h
@@ -29,8 +29,8 @@
typedef struct arm966e_common_s
{
- int common_magic;
arm9tdmi_common_t arm9tdmi_common;
+ int common_magic;
uint32_t cp15_control_reg;
} arm966e_common_t;
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 56db181..433ecfc 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -80,6 +80,9 @@ typedef struct xscale_trace_s
typedef struct xscale_common_s
{
+ /* armv4/5 common stuff */
+ armv4_5_common_t armv4_5_common;
+
int common_magic;
/* XScale registers (CP15, DBG) */
@@ -121,9 +124,6 @@ typedef struct xscale_common_s
int arch_debug_reason;
- /* armv4/5 common stuff */
- armv4_5_common_t armv4_5_common;
-
/* MMU/Caches */
armv4_5_mmu_common_t armv4_5_mmu;
uint32_t cp15_control_reg;
commit 03ac53a2cfdb7d0715f7060cecf8719068f6fae1
Author: David Brownell <dbr...@us...>
Date: Thu Nov 5 22:04:22 2009 -0800
ARM: other code uses the new inheritance/nesting scheme
Remove most remaining uses of target->arch_info from ARM
infrastructure, where it hasn't already been updated.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 21c5c7a..2a0aefc 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -172,8 +172,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
*/
int arm7_9_setup(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
return arm7_9_clear_watchpoints(arm7_9);
}
@@ -192,18 +191,18 @@ int arm7_9_setup(target_t *target)
*/
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ /* FIXME stop using this routine; just target_to_arm7_9() and
+ * verify the resulting pointer using a replacement routine
+ * that emits a usage message.
+ */
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
- {
- return -1;
- }
+ return ERROR_TARGET_INVALID;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
- {
- return -1;
- }
+ return ERROR_TARGET_INVALID;
*armv4_5_p = armv4_5;
*arm7_9_p = arm7_9;
@@ -224,8 +223,7 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm
*/
int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
@@ -355,9 +353,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
-
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
breakpoint->unique_id,
@@ -451,8 +447,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
*/
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
@@ -503,8 +498,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
{
@@ -540,8 +534,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
int rw_mask = 1;
uint32_t mask;
@@ -612,8 +605,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
@@ -660,8 +652,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
*/
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
@@ -695,8 +686,7 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
if (watchpoint->set)
{
@@ -723,9 +713,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
int arm7_9_execute_sys_speed(struct target_s *target)
{
int retval;
-
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@@ -778,8 +766,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
static int set = 0;
static uint8_t check_value[4], check_mask[4];
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
@@ -820,8 +807,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
*/
int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t *data;
int retval = ERROR_OK;
@@ -857,8 +843,7 @@ int arm7_9_handle_target_request(void *priv)
target_t *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
@@ -916,8 +901,7 @@ int arm7_9_handle_target_request(void *priv)
int arm7_9_poll(target_t *target)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* read debug status register */
@@ -1009,8 +993,8 @@ int arm7_9_poll(target_t *target)
*/
int arm7_9_assert_reset(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+
LOG_DEBUG("target->state: %s",
target_state_name(target));
@@ -1141,8 +1125,7 @@ int arm7_9_deassert_reset(target_t *target)
*/
int arm7_9_clear_halt(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
/* we used DBGRQ only if we didn't come out of reset */
@@ -1199,8 +1182,8 @@ int arm7_9_clear_halt(target_t *target)
*/
int arm7_9_soft_reset_halt(struct target_s *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
@@ -1318,8 +1301,7 @@ int arm7_9_halt(target_t *target)
return ERROR_OK;
}
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
@@ -1381,9 +1363,8 @@ int arm7_9_debug_entry(target_t *target)
uint32_t r0_thumb, pc_thumb;
uint32_t cpsr;
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
@@ -1536,8 +1517,8 @@ int arm7_9_full_context(target_t *target)
{
int i;
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
LOG_DEBUG("-");
@@ -1627,8 +1608,8 @@ int arm7_9_full_context(target_t *target)
*/
int arm7_9_restore_context(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *reg;
armv4_5_core_reg_t *reg_arch_info;
enum armv4_5_mode current_mode = armv4_5->core_mode;
@@ -1777,8 +1758,7 @@ int arm7_9_restore_context(target_t *target)
*/
int arm7_9_restart_core(struct target_s *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
@@ -1831,8 +1811,8 @@ void arm7_9_enable_breakpoints(struct target_s *target)
int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err, retval = ERROR_OK;
@@ -1991,9 +1971,8 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
@@ -2029,8 +2008,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
void arm7_9_disable_eice_step(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
@@ -2045,8 +2023,8 @@ void arm7_9_disable_eice_step(target_t *target)
int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = NULL;
int err, retval;
@@ -2141,8 +2119,8 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
uint32_t* reg_p[16];
uint32_t value;
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
@@ -2205,8 +2183,8 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
{
uint32_t reg[16];
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
@@ -2265,9 +2243,8 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t reg[16];
uint32_t num_accesses = 0;
int thisrun_accesses;
@@ -2441,8 +2418,8 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
uint32_t reg[16];
@@ -2628,8 +2605,7 @@ static uint8_t *dcc_buffer;
static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
return retval;
@@ -2694,8 +2670,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
int i;
if (!arm7_9->dcc_downloads)
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index d86ac24..9eafc1d 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -108,7 +108,6 @@ typedef struct arm7_9_common_s
void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
armv4_5_common_t armv4_5_common;
- void *arch_info;
} arm7_9_common_t;
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 27957b2..2d35af9 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -825,21 +825,19 @@ static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
-
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
struct arm_sim_interface sim;
- sim.user_data=armv4_5;
- sim.get_reg=&armv4_5_get_reg;
- sim.set_reg=&armv4_5_set_reg;
- sim.get_reg_mode=&armv4_5_get_reg_mode;
- sim.set_reg_mode=&armv4_5_set_reg_mode;
- sim.get_cpsr=&armv4_5_get_cpsr;
- sim.get_mode=&armv4_5_get_mode;
- sim.get_state=&armv4_5_get_state;
- sim.set_state=&armv4_5_set_state;
+ sim.user_data = armv4_5;
+ sim.get_reg = &armv4_5_get_reg;
+ sim.set_reg = &armv4_5_set_reg;
+ sim.get_reg_mode = &armv4_5_get_reg_mode;
+ sim.set_reg_mode = &armv4_5_set_reg_mode;
+ sim.get_cpsr = &armv4_5_get_cpsr;
+ sim.get_mode = &armv4_5_get_mode;
+ sim.get_state = &armv4_5_get_state;
+ sim.set_state = &armv4_5_set_state;
return arm_simulate_step_core(target, dry_run_pc, &sim);
-
}
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 9d942ae..0fe9ee4 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -189,7 +189,7 @@ int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
{
armv4_5_core_reg_t *armv4_5 = reg->arch_info;
target_t *target = armv4_5->target;
- armv4_5_common_t *armv4_5_target = target->arch_info;
+ struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
@@ -237,7 +237,7 @@ int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
int armv4_5_invalidate_core_regs(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
for (i = 0; i < 37; i++)
@@ -289,7 +289,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5
int armv4_5_arch_state(struct target_s *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
@@ -313,7 +313,7 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha
int output_len;
int mode, num;
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
@@ -362,7 +362,7 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha
int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
@@ -393,7 +393,7 @@ handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx,
{
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
uint32_t address;
int count = 1;
int i;
@@ -487,7 +487,7 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx)
int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
@@ -516,7 +516,7 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list
static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
@@ -547,7 +547,7 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t ex
int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info))
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
enum armv4_5_mode core_mode = armv4_5->core_mode;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 9909084..faeef38 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -276,10 +276,13 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
int embeddedice_setup(target_t *target)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- /* explicitly disable monitor mode */
+ /* Explicitly disable monitor mode. For now we only support halting
+ * debug ... we don't know how to talk with a resident debug monitor
+ * that manages break requests. ARM's "Angel Debug Monitor" is one
+ * common example of such code.
+ */
if (arm7_9->has_monitor_mode)
{
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
diff --git a/src/target/etm.c b/src/target/etm.c
index 8229bb0..21087b2 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -410,8 +410,7 @@ int etm_setup(target_t *target)
{
int retval;
uint32_t etm_ctrl_value;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
etm_context_t *etm_ctx = arm7_9->etm_ctx;
reg_t *etm_ctrl_reg;
commit a81df55f393478cdef9197c248a1b64d26465589
Author: David Brownell <dbr...@us...>
Date: Thu Nov 5 22:04:13 2009 -0800
Cortex-A8: use the new inheritance/nesting scheme
Use target_to_armv7a() etc, replacing needless pointer traversals.
Stop using X->arch_info scheme in most ARMv7-A and Cortex-A8 code.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 1583e99..6dfbb16 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -176,10 +176,7 @@ reg_t armv7a_gdb_dummy_fp_reg =
void armv7a_show_fault_registers(target_t *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
armv7a->read_cp15(target, 0, 0, 5, 0, &dfsr);
armv7a->read_cp15(target, 0, 1, 5, 0, &ifsr);
@@ -200,8 +197,8 @@ int armv7a_arch_state(struct target_s *target)
"disabled", "enabled"
};
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
@@ -237,8 +234,7 @@ static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
return dap_baseaddr_command(cmd_ctx, swjdp, args, argc);
@@ -248,8 +244,7 @@ static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
return dap_memaccess_command(cmd_ctx, swjdp, args, argc);
@@ -259,8 +254,7 @@ static int handle_dap_apsel_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
return dap_apsel_command(cmd_ctx, swjdp, args, argc);
@@ -270,8 +264,7 @@ static int handle_dap_apid_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
return dap_apid_command(cmd_ctx, swjdp, args, argc);
@@ -281,8 +274,7 @@ static int handle_dap_info_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
uint32_t apsel;
@@ -305,7 +297,7 @@ handle_armv7a_disassemble_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int thumb = 0;
int count = 1;
uint32_t address;
@@ -342,7 +334,7 @@ handle_armv7a_disassemble_command(struct command_context_s *cmd_ctx,
default:
usage:
command_print(cmd_ctx,
- "usage: armv4_5 disassemble <address> [<count> ['thumb']]");
+ "usage: armv7a disassemble <address> [<count> ['thumb']]");
return ERROR_OK;
}
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 3fc97f1..2ad0321 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -107,7 +107,6 @@ typedef struct armv7a_common_s
/* Cache and Memory Management Unit */
armv4_5_mmu_common_t armv4_5_mmu;
armv4_5_common_t armv4_5_common;
- void *arch_info;
// int (*full_context)(struct target_s *target);
// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 29fffae..141b439 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -128,9 +128,7 @@ target_type_t cortexa8_target =
*/
int cortex_a8_init_debug_access(target_t *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
int retval;
@@ -160,9 +158,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
{
uint32_t dscr;
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
@@ -203,9 +199,7 @@ int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
uint32_t * regfile)
{
int retval = ERROR_OK;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
@@ -222,9 +216,7 @@ int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
@@ -243,10 +235,7 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
{
int retval;
uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
@@ -310,10 +299,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
int retval = ERROR_OK;
uint8_t reg = regnum&0xFF;
uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
if (reg > 16)
@@ -354,10 +340,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
@@ -404,10 +387,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
{
int retval;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
retval = mem_ap_write_atomic_u32(swjdp, address, value);
@@ -423,16 +403,12 @@ int cortex_a8_poll(target_t *target)
{
int retval = ERROR_OK;
uint32_t dscr;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
-
enum target_state prev_target_state = target->state;
-
uint8_t saved_apsel = dap_ap_get_select(swjdp);
+
dap_ap_select(swjdp, swjdp_debugap);
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -492,12 +468,8 @@ int cortex_a8_halt(target_t *target)
{
int retval = ERROR_OK;
uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
@@ -533,9 +505,8 @@ out:
int cortex_a8_resume(struct target_s *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
// breakpoint_t *breakpoint = NULL;
@@ -658,11 +629,9 @@ int cortex_a8_debug_entry(target_t *target)
uint32_t regfile[16], pc, cpsr, dscr;
int retval = ERROR_OK;
working_area_t *regfile_working_area = NULL;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
@@ -785,10 +754,8 @@ int cortex_a8_debug_entry(target_t *target)
void cortex_a8_post_debug_entry(target_t *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
// cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
/* examine cp15 control reg */
@@ -820,9 +787,8 @@ void cortex_a8_post_debug_entry(target_t *target)
int cortex_a8_step(struct target_s *target, int current, uint32_t address,
int handle_breakpoints)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
breakpoint_t *breakpoint = NULL;
breakpoint_t stepbreakpoint;
@@ -901,10 +867,8 @@ int cortex_a8_restore_context(target_t *target)
{
int i;
uint32_t value;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
LOG_DEBUG(" ");
@@ -939,8 +903,7 @@ int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
armv4_5_mode_t mode, uint32_t * value)
{
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if ((num <= ARM_CPSR))
{
@@ -978,9 +941,7 @@ int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
{
int retval;
// uint32_t reg;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
@@ -1021,7 +982,8 @@ int cortex_a8_read_core_reg(struct target_s *target, int num,
{
uint32_t value;
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+
cortex_a8_dap_read_coreregister_u32(target, &value, num);
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -1041,7 +1003,7 @@ int cortex_a8_write_core_reg(struct target_s *target, int num,
enum armv4_5_mode mode, uint32_t value)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
cortex_a8_dap_write_coreregister_u32(target, value, num);
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -1068,12 +1030,8 @@ int cortex_a8_set_breakpoint(struct target_s *target,
int brp_i=0;
uint32_t control;
uint8_t byte_addr_select = 0x0F;
-
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
if (breakpoint->set)
@@ -1143,10 +1101,8 @@ int cortex_a8_set_breakpoint(struct target_s *target,
int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
if (!breakpoint->set)
@@ -1202,10 +1158,7 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
{
@@ -1222,10 +1175,7 @@ int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
#if 0
/* It is perfectly possible to remove brakpoints while the taget is running */
@@ -1291,9 +1241,7 @@ int cortex_a8_deassert_reset(target_t *target)
int cortex_a8_read_memory(struct target_s *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
int retval = ERROR_OK;
@@ -1328,9 +1276,7 @@ int cortex_a8_read_memory(struct target_s *target, uint32_t address,
int cortex_a8_write_memory(struct target_s *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
int retval;
@@ -1416,11 +1362,9 @@ int cortex_a8_handle_target_request(void *priv)
target_t *target = priv;
if (!target->type->examined)
return ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
if (!target->dbg_msg_enabled)
return ERROR_OK;
@@ -1457,13 +1401,9 @@ int cortex_a8_handle_target_request(void *priv)
int cortex_a8_examine(struct target_s *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
-
int i;
int retval = ERROR_OK;
uint32_t didr, ctypr, ttypr, cpuid;
@@ -1559,8 +1499,7 @@ int cortex_a8_examine(struct target_s *target)
void cortex_a8_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
@@ -1586,8 +1525,6 @@ int cortex_a8_init_arch_info(target_t *target,
/* Setup cortex_a8_common_t */
cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
- cortex_a8->arch_info = NULL;
- armv7a->arch_info = cortex_a8;
armv4_5->arch_info = armv7a;
armv4_5_init_arch_info(target, armv4_5);
@@ -1656,8 +1593,7 @@ static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common_s *armv7a = target_to_armv7a(target);
return armv4_5_handle_cache_info_command(cmd_ctx,
&armv7a->armv4_5_mmu.armv4_5_cache);
diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index b98a7de..b4cb327 100644
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -134,7 +134,6 @@ typedef struct cortex_a8_common_s
int fast_reg_read;
armv7a_common_t armv7a_common;
- void *arch_info;
} cortex_a8_common_t;
static inline struct cortex_a8_common_s *
commit fec3c4763ad4cf2996fa138c4fd0f555e32e5e9f
Author: David Brownell <dbr...@us...>
Date: Thu Nov 5 22:04:04 2009 -0800
ARM7TDMI uses the new inheritance/nesting scheme
Use target_to_arm7_9(), replacing needless pointer traversals.
Also: remove now-useless contents of arm7tdmi struct; it's
almost ready to be removed.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 27a8337..8b929d4 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -44,9 +44,7 @@
static int arm7tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
@@ -268,9 +266,7 @@ static int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info,
static void arm7tdmi_change_to_arm(target_t *target,
uint32_t *r0, uint32_t *pc)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
@@ -327,9 +323,7 @@ static void arm7tdmi_read_core_regs(target_t *target,
uint32_t mask, uint32_t* core_regs[16])
{
int i;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
@@ -354,9 +348,7 @@ static void arm7tdmi_read_core_regs_target_buffer(target_t *target,
uint32_t mask, void* buffer, int size)
{
int i;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
@@ -396,9 +388,7 @@ static void arm7tdmi_read_core_regs_target_buffer(target_t *target,
static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
@@ -416,9 +406,7 @@ static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
@@ -448,9 +436,7 @@ static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
static void arm7tdmi_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
@@ -469,9 +455,7 @@ static void arm7tdmi_write_core_regs(target_t *target,
uint32_t mask, uint32_t core_regs[16])
{
int i;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@@ -495,9 +479,7 @@ static void arm7tdmi_write_core_regs(target_t *target,
static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
@@ -508,9 +490,7 @@ static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
static void arm7tdmi_load_hword_reg(target_t *target, int num)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
@@ -521,9 +501,7 @@ static void arm7tdmi_load_hword_reg(target_t *target, int num)
static void arm7tdmi_load_byte_reg(target_t *target, int num)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
@@ -534,9 +512,7 @@ static void arm7tdmi_load_byte_reg(target_t *target, int num)
static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
@@ -547,9 +523,7 @@ static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
static void arm7tdmi_store_hword_reg(target_t *target, int num)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
@@ -560,9 +534,7 @@ static void arm7tdmi_store_hword_reg(target_t *target, int num)
static void arm7tdmi_store_byte_reg(target_t *target, int num)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
@@ -573,9 +545,7 @@ static void arm7tdmi_store_byte_reg(target_t *target, int num)
static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
@@ -600,9 +570,7 @@ static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
static void arm7tdmi_branch_resume(target_t *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
@@ -611,14 +579,13 @@ static void arm7tdmi_branch_resume(target_t *target)
static void arm7tdmi_branch_resume_thumb(target_t *target)
{
- LOG_DEBUG("-");
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ LOG_DEBUG("-");
+
/* LDMIA r0, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
@@ -673,8 +640,7 @@ static void arm7tdmi_branch_resume_thumb(target_t *target)
static void arm7tdmi_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
@@ -682,9 +648,10 @@ static void arm7tdmi_build_reg_cache(target_t *target)
int arm7tdmi_examine(struct target_s *target)
{
+ struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+
+
if (!target_was_examined(target))
{
/* get pointers to arch-specific information */
@@ -725,11 +692,7 @@ int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
{
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
-
- arm7_9 = &arm7tdmi->arm7_9_common;
- armv4_5 = &arm7_9->armv4_5_common;
+ struct arm7_9_common_s *arm7_9 = &arm7tdmi->arm7_9_common;
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
@@ -771,10 +734,6 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
arm7_9->thumb_bkpt = 0xdeee;
arm7_9->dbgreq_adjust_pc = 2;
- arm7_9->arch_info = arm7tdmi;
-
- arm7tdmi->arch_info = NULL;
- arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
arm7_9_init_arch_info(target, arm7_9);
diff --git a/src/target/arm7tdmi.h b/src/target/arm7tdmi.h
index da5c040..f69ba49 100644
--- a/src/target/arm7tdmi.h
+++ b/src/target/arm7tdmi.h
@@ -25,12 +25,11 @@
#include "embeddedice.h"
-#define ARM7TDMI_COMMON_MAGIC 0x00a700a7
-
+/* FIXME we don't really need a separate arm7tdmi struct any more...
+ * remove it, the arm7/arm9 common struct suffices.
+ */
typedef struct arm7tdmi_common_s
{
- int common_magic;
- void *arch_info;
arm7_9_common_t arm7_9_common;
} arm7tdmi_common_t;
commit 11fe2ec62e30e4b580ace6821ac4293ed91d53f1
Author: David Brownell <dbr...@us...>
Date: Thu Nov 5 22:03:56 2009 -0800
ARM720 uses the new inheritance/nesting scheme
Use target_to_arm720(), replacing needless pointer traversals
and simplifying a bunch of nasty code. Stop setting arch_info
for arm720 type parts, it's not used any longer.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index cb21d5f..673296e 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -41,14 +41,15 @@
static int arm720t_scan_cp15(target_t *target,
uint32_t out, uint32_t *in, int instruction, int clock)
{
- int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ int retval;
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+ arm_jtag_t *jtag_info;
scan_field_t fields[2];
uint8_t out_buf[4];
uint8_t instruction_buf = instruction;
+ jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info;
+
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
jtag_set_end_state(TAP_DRPAUSE);
@@ -184,10 +185,7 @@ static void arm720t_enable_mmu_caches(target_t *target,
static void arm720t_post_debug_entry(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
- arm720t_common_t *arm720t = arm7tdmi->arch_info;
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
/* examine cp15 control reg */
arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
@@ -206,68 +204,35 @@ static void arm720t_post_debug_entry(target_t *target)
static void arm720t_pre_restore_context(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
- arm720t_common_t *arm720t = arm7tdmi->arch_info;
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
/* restore i/d fault status and address register */
arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
}
-static int arm720t_get_arch_pointers(target_t *target,
- armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p,
- arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
+static int arm720t_verify_pointer(struct command_context_s *cmd_ctx,
+ struct arm720t_common_s *arm720t)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9;
- arm7tdmi_common_t *arm7tdmi;
- arm720t_common_t *arm720t;
-
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
- {
- return -1;
- }
-
- arm7_9 = armv4_5->arch_info;
- if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
- {
- return -1;
- }
-
- arm7tdmi = arm7_9->arch_info;
- if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
- {
- return -1;
- }
-
- arm720t = arm7tdmi->arch_info;
- if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
- {
- return -1;
+ if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
+ command_print(cmd_ctx, "target is not an ARM720");
+ return ERROR_TARGET_INVALID;
}
-
- *armv4_5_p = armv4_5;
- *arm7_9_p = arm7_9;
- *arm7tdmi_p = arm7tdmi;
- *arm720t_p = arm720t;
-
return ERROR_OK;
}
static int arm720t_arch...
[truncated message content] |
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