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commit dc187298ea70a8895f8781833dd9036730d33ce5
Author: Tomas Vanek <va...@fb...>
Date: Mon Oct 20 16:01:04 2025 +0200
target/cortex_m: do not expose BASEPRI and FAULTMASK registers
on ARMv6M variants (mainly Cortex-M0 and Cortex-M0+) and
on ARMv8M baseline (e.g.Cortex-M23). The devices do not have
BASEPRI and FAULTMASK functionally implemented and the corresponding
register bits are just read as zero, write ignored.
ARMv6-M Architecture Reference Manual:
Table D3-2 Programmersâ model feature comparison
Reduced exception priority management: PRIMASK
special-purpose register. No support for changing the
priority of configurable exceptions when they are active.
Armv8-M Architecture Reference Manual:
B3.32 Special-purpose mask registers, PRIMASK, BASEPRI, FAULTMASK,
for configurable priority boosting
A PE without the Main Extension implements PRIMASK, but does not
implement FAULTMASK and BASEPRI.
Change-Id: I332cc79718852c0109148817a214a2657960370b
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9174
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 9f0b6284b..d15575bd7 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2887,7 +2887,7 @@ int cortex_m_examine(struct target *target)
if (armv7m->fp_feature != FPV5_MVE_F && armv7m->fp_feature != FPV5_MVE_I)
armv7m->arm.core_cache->reg_list[ARMV8M_VPR].exist = false;
- if (cortex_m->core_info->arch == ARM_ARCH_V8M) {
+ if (armv7m->arm.arch == ARM_ARCH_V8M) {
bool cm_has_tz = cortex_m_has_tz(target);
bool main_ext = cortex_m_main_extension(target, cpuid);
bool baseline = !main_ext;
@@ -2908,6 +2908,11 @@ int cortex_m_examine(struct target *target)
armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM_NS].exist = false;
armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM].exist = false;
armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM].exist = false;
+
+ armv7m->arm.core_cache->reg_list[ARMV8M_BASEPRI_S].exist = false;
+ armv7m->arm.core_cache->reg_list[ARMV8M_FAULTMASK_S].exist = false;
+ armv7m->arm.core_cache->reg_list[ARMV8M_BASEPRI_NS].exist = false;
+ armv7m->arm.core_cache->reg_list[ARMV8M_FAULTMASK_NS].exist = false;
} else {
/* There is no separate regsel for msplim/psplim of ARMV8M mainline
with the security extension that would point to correct alias
@@ -2917,6 +2922,11 @@ int cortex_m_examine(struct target *target)
armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM].exist = false;
}
}
+
+ if (baseline) {
+ armv7m->arm.core_cache->reg_list[ARMV7M_BASEPRI].exist = false;
+ armv7m->arm.core_cache->reg_list[ARMV7M_FAULTMASK].exist = false;
+ }
} else {
/* Security extension and stack limit checking introduced in ARMV8M */
for (size_t idx = ARMV8M_TZ_FIRST_REG; idx <= ARMV8M_TZ_LAST_REG; idx++)
@@ -2924,6 +2934,11 @@ int cortex_m_examine(struct target *target)
armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM].exist = false;
armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM].exist = false;
+
+ if (armv7m->arm.arch == ARM_ARCH_V6M) {
+ armv7m->arm.core_cache->reg_list[ARMV7M_BASEPRI].exist = false;
+ armv7m->arm.core_cache->reg_list[ARMV7M_FAULTMASK].exist = false;
+ }
}
if (!armv7m->is_hla_target) {
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
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