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From: openocd-gerrit <ope...@us...> - 2025-11-12 20:17:25
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- Log -----------------------------------------------------------------
commit bd303d6a3daa64a671eca6f951eaac88b86346de
Author: Antonio Borneo <bor...@gm...>
Date: Sat Aug 2 19:33:37 2025 +0200
target: riscv: align switch and case statements
The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.
Align the code accordingly.
While there, put at newline the command after the 'case'.
No changes are reported by
git log -p -w --ignore-blank-lines --patience
apart from the newline after 'case'.
Change-Id: Id856e24100de6fb0442afe8bc51545b0138ef02d
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9069
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evg...@sy...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 69ad5fcbf..139d555f8 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -230,19 +230,25 @@ static unsigned int slot_offset(const struct target *target, slot_t slot)
{
riscv011_info_t *info = get_info(target);
switch (riscv_xlen(target)) {
- case 32:
- switch (slot) {
- case SLOT0: return 4;
- case SLOT1: return 5;
- case SLOT_LAST: return info->dramsize-1;
- }
- break;
- case 64:
- switch (slot) {
- case SLOT0: return 4;
- case SLOT1: return 6;
- case SLOT_LAST: return info->dramsize-2;
- }
+ case 32:
+ switch (slot) {
+ case SLOT0:
+ return 4;
+ case SLOT1:
+ return 5;
+ case SLOT_LAST:
+ return info->dramsize - 1;
+ }
+ break;
+ case 64:
+ switch (slot) {
+ case SLOT0:
+ return 4;
+ case SLOT1:
+ return 6;
+ case SLOT_LAST:
+ return info->dramsize - 2;
+ }
}
LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
riscv_xlen(target), slot);
@@ -254,10 +260,10 @@ static uint32_t load(const struct target *target, unsigned int rd,
unsigned int base, int16_t offset)
{
switch (riscv_xlen(target)) {
- case 32:
- return lw(rd, base, offset);
- case 64:
- return ld(rd, base, offset);
+ case 32:
+ return lw(rd, base, offset);
+ case 64:
+ return ld(rd, base, offset);
}
assert(0);
return 0; /* Silence -Werror=return-type */
@@ -267,10 +273,10 @@ static uint32_t store(const struct target *target, unsigned int src,
unsigned int base, int16_t offset)
{
switch (riscv_xlen(target)) {
- case 32:
- return sw(src, base, offset);
- case 64:
- return sd(src, base, offset);
+ case 32:
+ return sw(src, base, offset);
+ case 64:
+ return sd(src, base, offset);
}
assert(0);
return 0; /* Silence -Werror=return-type */
@@ -641,13 +647,13 @@ static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
{
const struct target *target = scans->target;
switch (riscv_xlen(target)) {
- case 32:
- scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
- break;
- case 64:
- scans_add_read32(scans, slot_offset(target, slot), false);
- scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
- break;
+ case 32:
+ scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
+ break;
+ case 64:
+ scans_add_read32(scans, slot_offset(target, slot), false);
+ scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
+ break;
}
}
@@ -906,19 +912,19 @@ static int cache_write(struct target *target, unsigned int address, bool run)
dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
DBUS_OP_SIZE);
switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug RAM write failed. Hardware error?");
- scans_delete(scans);
- return ERROR_FAIL;
- case DBUS_STATUS_BUSY:
- errors++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- scans_delete(scans);
- return ERROR_FAIL;
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ scans_delete(scans);
+ return ERROR_FAIL;
+ case DBUS_STATUS_BUSY:
+ errors++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ scans_delete(scans);
+ return ERROR_FAIL;
}
}
@@ -1680,17 +1686,17 @@ static riscv_error_t handle_halt_routine(struct target *target)
uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
info->addrbits);
switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug access failed. Hardware error?");
- goto error;
- case DBUS_STATUS_BUSY:
- dbus_busy++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- goto error;
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug access failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ goto error;
}
if (data & DMCONTROL_INTERRUPT) {
interrupt_set++;
@@ -1699,111 +1705,111 @@ static riscv_error_t handle_halt_routine(struct target *target)
if (address == 4 || address == 5) {
unsigned int reg;
switch (result) {
- case 0:
- reg = 1;
- break;
- case 1:
- reg = 2;
- break;
- case 2:
- reg = 3;
- break;
- case 3:
- reg = 4;
- break;
- case 4:
- reg = 5;
- break;
- case 5:
- reg = 6;
- break;
- case 6:
- reg = 7;
- break;
- /* S0 */
- /* S1 */
- case 7:
- reg = 10;
- break;
- case 8:
- reg = 11;
- break;
- case 9:
- reg = 12;
- break;
- case 10:
- reg = 13;
- break;
- case 11:
- reg = 14;
- break;
- case 12:
- reg = 15;
- break;
- case 13:
- reg = 16;
- break;
- case 14:
- reg = 17;
- break;
- case 15:
- reg = 18;
- break;
- case 16:
- reg = 19;
- break;
- case 17:
- reg = 20;
- break;
- case 18:
- reg = 21;
- break;
- case 19:
- reg = 22;
- break;
- case 20:
- reg = 23;
- break;
- case 21:
- reg = 24;
- break;
- case 22:
- reg = 25;
- break;
- case 23:
- reg = 26;
- break;
- case 24:
- reg = 27;
- break;
- case 25:
- reg = 28;
- break;
- case 26:
- reg = 29;
- break;
- case 27:
- reg = 30;
- break;
- case 28:
- reg = 31;
- break;
- case 29:
- reg = S1;
- break;
- case 30:
- reg = S0;
- break;
- case 31:
- reg = GDB_REGNO_DPC;
- break;
- case 32:
- reg = GDB_REGNO_DCSR;
- break;
- default:
- assert(0);
- LOG_ERROR("Got invalid register result %d", result);
- goto error;
+ case 0:
+ reg = 1;
+ break;
+ case 1:
+ reg = 2;
+ break;
+ case 2:
+ reg = 3;
+ break;
+ case 3:
+ reg = 4;
+ break;
+ case 4:
+ reg = 5;
+ break;
+ case 5:
+ reg = 6;
+ break;
+ case 6:
+ reg = 7;
+ break;
+ /* S0 */
+ /* S1 */
+ case 7:
+ reg = 10;
+ break;
+ case 8:
+ reg = 11;
+ break;
+ case 9:
+ reg = 12;
+ break;
+ case 10:
+ reg = 13;
+ break;
+ case 11:
+ reg = 14;
+ break;
+ case 12:
+ reg = 15;
+ break;
+ case 13:
+ reg = 16;
+ break;
+ case 14:
+ reg = 17;
+ break;
+ case 15:
+ reg = 18;
+ break;
+ case 16:
+ reg = 19;
+ break;
+ case 17:
+ reg = 20;
+ break;
+ case 18:
+ reg = 21;
+ break;
+ case 19:
+ reg = 22;
+ break;
+ case 20:
+ reg = 23;
+ break;
+ case 21:
+ reg = 24;
+ break;
+ case 22:
+ reg = 25;
+ break;
+ case 23:
+ reg = 26;
+ break;
+ case 24:
+ reg = 27;
+ break;
+ case 25:
+ reg = 28;
+ break;
+ case 26:
+ reg = 29;
+ break;
+ case 27:
+ reg = 30;
+ break;
+ case 28:
+ reg = 31;
+ break;
+ case 29:
+ reg = S1;
+ break;
+ case 30:
+ reg = S0;
+ break;
+ case 31:
+ reg = GDB_REGNO_DPC;
+ break;
+ case 32:
+ reg = GDB_REGNO_DCSR;
+ break;
+ default:
+ assert(0);
+ LOG_ERROR("Got invalid register result %d", result);
+ goto error;
}
if (riscv_xlen(target) == 32) {
reg_cache_set(target, reg, data & 0xffffffff);
@@ -1860,22 +1866,22 @@ static int handle_halt(struct target *target, bool announce)
int cause = get_field(info->dcsr, DCSR_CAUSE);
switch (cause) {
- case DCSR_CAUSE_SWBP:
- target->debug_reason = DBG_REASON_BREAKPOINT;
- break;
- case DCSR_CAUSE_HWBP:
- target->debug_reason = DBG_REASON_WATCHPOINT;
- break;
- case DCSR_CAUSE_DEBUGINT:
- target->debug_reason = DBG_REASON_DBGRQ;
- break;
- case DCSR_CAUSE_STEP:
- target->debug_reason = DBG_REASON_SINGLESTEP;
- break;
- case DCSR_CAUSE_HALT:
- default:
- LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
- cause, info->dcsr);
+ case DCSR_CAUSE_SWBP:
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ break;
+ case DCSR_CAUSE_HWBP:
+ target->debug_reason = DBG_REASON_WATCHPOINT;
+ break;
+ case DCSR_CAUSE_DEBUGINT:
+ target->debug_reason = DBG_REASON_DBGRQ;
+ break;
+ case DCSR_CAUSE_STEP:
+ target->debug_reason = DBG_REASON_SINGLESTEP;
+ break;
+ case DCSR_CAUSE_HALT:
+ default:
+ LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
+ cause, info->dcsr);
}
if (info->never_halted) {
@@ -2032,21 +2038,21 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
switch (size) {
- case 1:
- cache_set32(target, 1, lb(S1, S0, 0));
- cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
- break;
- case 2:
- cache_set32(target, 1, lh(S1, S0, 0));
- cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
- break;
- case 4:
- cache_set32(target, 1, lw(S1, S0, 0));
- cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
- break;
- default:
- LOG_ERROR("Unsupported size: %d", size);
- return ERROR_FAIL;
+ case 1:
+ cache_set32(target, 1, lb(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ case 2:
+ cache_set32(target, 1, lh(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ case 4:
+ cache_set32(target, 1, lw(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ default:
+ LOG_ERROR("Unsupported size: %d", size);
+ return ERROR_FAIL;
}
cache_set_jump(target, 3);
cache_write(target, CACHE_NO_READ, false);
@@ -2089,17 +2095,17 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
DBUS_OP_SIZE);
switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug RAM write failed. Hardware error?");
- goto error;
- case DBUS_STATUS_BUSY:
- dbus_busy++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- return ERROR_FAIL;
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
}
uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
DBUS_DATA_SIZE);
@@ -2110,19 +2116,19 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
} else if (i + j > 1) {
uint32_t offset = size * (i + j - 2);
switch (size) {
- case 1:
- buffer[offset] = data;
- break;
- case 2:
- buffer[offset] = data;
- buffer[offset+1] = data >> 8;
- break;
- case 4:
- buffer[offset] = data;
- buffer[offset+1] = data >> 8;
- buffer[offset+2] = data >> 16;
- buffer[offset+3] = data >> 24;
- break;
+ case 1:
+ buffer[offset] = data;
+ break;
+ case 2:
+ buffer[offset] = data;
+ buffer[offset + 1] = data >> 8;
+ break;
+ case 4:
+ buffer[offset] = data;
+ buffer[offset + 1] = data >> 8;
+ buffer[offset + 2] = data >> 16;
+ buffer[offset + 3] = data >> 24;
+ break;
}
}
LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
@@ -2167,21 +2173,21 @@ error:
static int setup_write_memory(struct target *target, uint32_t size)
{
switch (size) {
- case 1:
- cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
- cache_set32(target, 1, sb(S0, T0, 0));
- break;
- case 2:
- cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
- cache_set32(target, 1, sh(S0, T0, 0));
- break;
- case 4:
- cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
- cache_set32(target, 1, sw(S0, T0, 0));
- break;
- default:
- LOG_ERROR("Unsupported size: %d", size);
- return ERROR_FAIL;
+ case 1:
+ cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sb(S0, T0, 0));
+ break;
+ case 2:
+ cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sh(S0, T0, 0));
+ break;
+ case 4:
+ cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sw(S0, T0, 0));
+ break;
+ default:
+ LOG_ERROR("Unsupported size: %d", size);
+ return ERROR_FAIL;
}
cache_set32(target, 2, addi(T0, T0, size));
cache_set_jump(target, 3);
@@ -2241,21 +2247,21 @@ static int write_memory(struct target *target, const struct riscv_mem_access_arg
uint32_t value;
uint32_t offset = size * (i + j);
switch (size) {
- case 1:
- value = buffer[offset];
- break;
- case 2:
- value = buffer[offset] |
- (buffer[offset+1] << 8);
- break;
- case 4:
- value = buffer[offset] |
- ((uint32_t) buffer[offset+1] << 8) |
- ((uint32_t) buffer[offset+2] << 16) |
- ((uint32_t) buffer[offset+3] << 24);
- break;
- default:
- goto error;
+ case 1:
+ value = buffer[offset];
+ break;
+ case 2:
+ value = buffer[offset] |
+ (buffer[offset + 1] << 8);
+ break;
+ case 4:
+ value = buffer[offset] |
+ ((uint32_t)buffer[offset + 1] << 8) |
+ ((uint32_t)buffer[offset + 2] << 16) |
+ ((uint32_t)buffer[offset + 3] << 24);
+ break;
+ default:
+ goto error;
}
scans_add_write32(scans, 4, value, true);
@@ -2274,17 +2280,17 @@ static int write_memory(struct target *target, const struct riscv_mem_access_arg
dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
DBUS_OP_SIZE);
switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug RAM write failed. Hardware error?");
- goto error;
- case DBUS_STATUS_BUSY:
- dbus_busy++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- return ERROR_FAIL;
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
}
int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
if (interrupt)
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 336a7514e..2a947bd69 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -592,15 +592,15 @@ static int increase_ac_busy_delay(struct target *target)
static uint32_t __attribute__((unused)) abstract_register_size(unsigned int width)
{
switch (width) {
- case 32:
- return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2);
- case 64:
- return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3);
- case 128:
- return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4);
- default:
- LOG_ERROR("Unsupported register width: %d", width);
- return 0;
+ case 32:
+ return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2);
+ case 64:
+ return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3);
+ case 128:
+ return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4);
+ default:
+ LOG_ERROR("Unsupported register width: %d", width);
+ return 0;
}
}
@@ -737,12 +737,12 @@ int riscv013_execute_abstract_command(struct target *target, uint32_t command,
*cmderr = CMDERR_NONE;
if (debug_level >= LOG_LVL_DEBUG) {
switch (get_field(command, DM_COMMAND_CMDTYPE)) {
- case 0:
- LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
- break;
- default:
- LOG_TARGET_DEBUG(target, "command=0x%x", command);
- break;
+ case 0:
+ LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
+ break;
+ default:
+ LOG_TARGET_DEBUG(target, "command=0x%x", command);
+ break;
}
}
@@ -854,14 +854,14 @@ static int write_abstract_arg(struct target *target, unsigned int index,
{
unsigned int offset = index * size_bits / 32;
switch (size_bits) {
- default:
- LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
- return ERROR_FAIL;
- case 64:
- dm_write(target, DM_DATA0 + offset + 1, (uint32_t)(value >> 32));
- /* falls through */
- case 32:
- dm_write(target, DM_DATA0 + offset, (uint32_t)value);
+ default:
+ LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
+ return ERROR_FAIL;
+ case 64:
+ dm_write(target, DM_DATA0 + offset + 1, (uint32_t)(value >> 32));
+ /* falls through */
+ case 32:
+ dm_write(target, DM_DATA0 + offset, (uint32_t)value);
}
return ERROR_OK;
}
@@ -874,16 +874,16 @@ uint32_t riscv013_access_register_command(struct target *target, uint32_t number
{
uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
switch (size) {
- case 32:
- command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2);
- break;
- case 64:
- command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
- break;
- default:
- LOG_TARGET_ERROR(target, "%d-bit register %s not supported.",
- size, riscv_reg_gdb_regno_name(target, number));
- assert(0);
+ case 32:
+ command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2);
+ break;
+ case 64:
+ command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
+ break;
+ default:
+ LOG_TARGET_ERROR(target, "%d-bit register %s not supported.",
+ size, riscv_reg_gdb_regno_name(target, number));
+ assert(0);
}
if (number <= GDB_REGNO_XPR31) {
@@ -1003,19 +1003,19 @@ cleanup:
static uint32_t abstract_memory_size(unsigned int width)
{
switch (width) {
- case 8:
- return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0);
- case 16:
- return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1);
- case 32:
- return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2);
- case 64:
- return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3);
- case 128:
- return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4);
- default:
- LOG_ERROR("Unsupported memory width: %d", width);
- return 0;
+ case 8:
+ return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0);
+ case 16:
+ return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1);
+ case 32:
+ return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2);
+ case 64:
+ return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3);
+ case 128:
+ return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4);
+ default:
+ LOG_ERROR("Unsupported memory width: %d", width);
+ return 0;
}
}
@@ -1251,38 +1251,38 @@ static int scratch_read64(struct target *target, scratch_mem_t *scratch,
{
uint32_t v;
switch (scratch->memory_space) {
- case SPACE_DM_DATA:
- if (dm_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK)
- return ERROR_FAIL;
- *value = v;
- if (dm_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK)
- return ERROR_FAIL;
- *value |= ((uint64_t) v) << 32;
- break;
- case SPACE_DMI_PROGBUF:
- if (dm_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK)
- return ERROR_FAIL;
- *value = v;
- if (dm_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK)
+ case SPACE_DM_DATA:
+ if (dm_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK)
+ return ERROR_FAIL;
+ *value = v;
+ if (dm_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK)
+ return ERROR_FAIL;
+ *value |= ((uint64_t)v) << 32;
+ break;
+ case SPACE_DMI_PROGBUF:
+ if (dm_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK)
+ return ERROR_FAIL;
+ *value = v;
+ if (dm_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK)
+ return ERROR_FAIL;
+ *value |= ((uint64_t)v) << 32;
+ break;
+ case SPACE_DMI_RAM:
+ {
+ uint8_t buffer[8] = {0};
+ const struct riscv_mem_access_args args = {
+ .address = scratch->debug_address,
+ .read_buffer = buffer,
+ .size = 4,
+ .count = 2,
+ .increment = 4,
+ };
+ if (riscv013_access_memory(target, args) != ERROR_OK)
return ERROR_FAIL;
- *value |= ((uint64_t) v) << 32;
- break;
- case SPACE_DMI_RAM:
- {
- uint8_t buffer[8] = {0};
- const struct riscv_mem_access_args args = {
- .address = scratch->debug_address,
- .read_buffer = buffer,
- .size = 4,
- .count = 2,
- .increment = 4,
- };
- if (riscv013_access_memory(target, args) != ERROR_OK)
- return ERROR_FAIL;
- *value = buf_get_u64(buffer,
- /* first = */ 0, /* bit_num = */ 64);
- }
- break;
+ *value = buf_get_u64(buffer,
+ /* first = */ 0, /* bit_num = */ 64);
+ }
+ break;
}
return ERROR_OK;
}
@@ -1291,38 +1291,38 @@ static int scratch_write64(struct target *target, scratch_mem_t *scratch,
uint64_t value)
{
switch (scratch->memory_space) {
- case SPACE_DM_DATA:
- dm_write(target, DM_DATA0 + scratch->debug_address, (uint32_t)value);
- dm_write(target, DM_DATA1 + scratch->debug_address, (uint32_t)(value >> 32));
- break;
- case SPACE_DMI_PROGBUF:
- dm_write(target, DM_PROGBUF0 + scratch->debug_address, (uint32_t)value);
- dm_write(target, DM_PROGBUF1 + scratch->debug_address, (uint32_t)(value >> 32));
- riscv013_invalidate_cached_progbuf(target);
- break;
- case SPACE_DMI_RAM:
- {
- uint8_t buffer[8] = {
- value,
- value >> 8,
- value >> 16,
- value >> 24,
- value >> 32,
- value >> 40,
- value >> 48,
- value >> 56
- };
- const struct riscv_mem_access_args args = {
- .address = scratch->debug_address,
- .write_buffer = buffer,
- .size = 4,
- .count = 2,
- .increment = 4,
- };
- if (riscv013_access_memory(target, args) != ERROR_OK)
- return ERROR_FAIL;
- }
- break;
+ case SPACE_DM_DATA:
+ dm_write(target, DM_DATA0 + scratch->debug_address, (uint32_t)value);
+ dm_write(target, DM_DATA1 + scratch->debug_address, (uint32_t)(value >> 32));
+ break;
+ case SPACE_DMI_PROGBUF:
+ dm_write(target, DM_PROGBUF0 + scratch->debug_address, (uint32_t)value);
+ dm_write(target, DM_PROGBUF1 + scratch->debug_address, (uint32_t)(value >> 32));
+ riscv013_invalidate_cached_progbuf(target);
+ break;
+ case SPACE_DMI_RAM:
+ {
+ uint8_t buffer[8] = {
+ value,
+ value >> 8,
+ value >> 16,
+ value >> 24,
+ value >> 32,
+ value >> 40,
+ value >> 48,
+ value >> 56
+ };
+ const struct riscv_mem_access_args args = {
+ .address = scratch->debug_address,
+ .write_buffer = buffer,
+ .size = 4,
+ .count = 2,
+ .increment = 4,
+ };
+ if (riscv013_access_memory(target, args) != ERROR_OK)
+ return ERROR_FAIL;
+ }
+ break;
}
return ERROR_OK;
}
@@ -2451,16 +2451,16 @@ int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
static uint32_t sb_sbaccess(unsigned int size_bytes)
{
switch (size_bytes) {
- case 1:
- return set_field(0, DM_SBCS_SBACCESS, 0);
- case 2:
- return set_field(0, DM_SBCS_SBACCESS, 1);
- case 4:
- return set_field(0, DM_SBCS_SBACCESS, 2);
- case 8:
- return set_field(0, DM_SBCS_SBACCESS, 3);
- case 16:
- return set_field(0, DM_SBCS_SBACCESS, 4);
+ case 1:
+ return set_field(0, DM_SBCS_SBACCESS, 0);
+ case 2:
+ return set_field(0, DM_SBCS_SBACCESS, 1);
+ case 4:
+ return set_field(0, DM_SBCS_SBACCESS, 2);
+ case 8:
+ return set_field(0, DM_SBCS_SBACCESS, 3);
+ case 16:
+ return set_field(0, DM_SBCS_SBACCESS, 4);
}
assert(0);
return 0;
@@ -2581,18 +2581,18 @@ static int sba_supports_access(struct target *target, unsigned int size_bytes)
{
RISCV013_INFO(info);
switch (size_bytes) {
- case 1:
- return get_field(info->sbcs, DM_SBCS_SBACCESS8);
- case 2:
- return get_field(info->sbcs, DM_SBCS_SBACCESS16);
- case 4:
- return get_field(info->sbcs, DM_SBCS_SBACCESS32);
- case 8:
- return get_field(info->sbcs, DM_SBCS_SBACCESS64);
- case 16:
- return get_field(info->sbcs, DM_SBCS_SBACCESS128);
- default:
- return 0;
+ case 1:
+ return get_field(info->sbcs, DM_SBCS_SBACCESS8);
+ case 2:
+ return get_field(info->sbcs, DM_SBCS_SBACCESS16);
+ case 4:
+ return get_field(info->sbcs, DM_SBCS_SBACCESS32);
+ case 8:
+ return get_field(info->sbcs, DM_SBCS_SBACCESS64);
+ case 16:
+ return get_field(info->sbcs, DM_SBCS_SBACCESS128);
+ default:
+ return 0;
}
}
@@ -3113,19 +3113,19 @@ static void log_memory_access64(target_addr_t address, uint64_t value,
sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%0%d" PRIx64,
address, is_read ? "read" : "write", size_bytes * 2);
switch (size_bytes) {
- case 1:
- value &= 0xff;
- break;
- case 2:
- value &= 0xffff;
- break;
- case 4:
- value &= 0xffffffffUL;
- break;
- case 8:
- break;
- default:
- assert(false);
+ case 1:
+ value &= 0xff;
+ break;
+ case 2:
+ value &= 0xffff;
+ break;
+ case 4:
+ value &= 0xffffffffUL;
+ break;
+ case 8:
+ break;
+ default:
+ assert(false);
}
LOG_DEBUG(fmt, value);
}
@@ -4580,19 +4580,19 @@ riscv013_access_memory(struct target *target, const struct riscv_mem_access_args
for (unsigned int i = 0; i < r->num_enabled_mem_access_methods; ++i) {
enum riscv_mem_access_method method = r->mem_access_methods[i];
switch (method) {
- case RISCV_MEM_ACCESS_PROGBUF:
- skip_reason[method] = access_memory_progbuf(target, args);
- break;
- case RISCV_MEM_ACCESS_SYSBUS:
- skip_reason[method] = access_memory_sysbus(target, args);
- break;
- case RISCV_MEM_ACCESS_ABSTRACT:
- skip_reason[method] = access_memory_abstract(target, args);
- break;
- default:
- LOG_TARGET_ERROR(target, "Unknown memory access method: %d", method);
- assert(false && "Unknown memory access method");
- goto failure;
+ case RISCV_MEM_ACCESS_PROGBUF:
+ skip_reason[method] = access_memory_progbuf(target, args);
+ break;
+ case RISCV_MEM_ACCESS_SYSBUS:
+ skip_reason[method] = access_memory_sysbus(target, args);
+ break;
+ case RISCV_MEM_ACCESS_ABSTRACT:
+ skip_reason[method] = access_memory_abstract(target, args);
+ break;
+ default:
+ LOG_TARGET_ERROR(target, "Unknown memory access method: %d", method);
+ assert(false && "Unknown memory access method");
+ goto failure;
}
if (is_mem_access_failed(skip_reason[method]))
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 2b6d0c755..7ef875f80 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -462,16 +462,16 @@ static struct target_type *get_target_type(struct target *target)
RISCV_INFO(info);
switch (info->dtm_version) {
- case DTM_DTMCS_VERSION_0_11:
- return &riscv011_target;
- case DTM_DTMCS_VERSION_1_0:
- return &riscv013_target;
- default:
- /* TODO: once we have proper support for non-examined targets
- * we should have an assert here */
- LOG_TARGET_ERROR(target, "Unsupported DTM version: %d",
- info->dtm_version);
- return NULL;
+ case DTM_DTMCS_VERSION_0_11:
+ return &riscv011_target;
+ case DTM_DTMCS_VERSION_1_0:
+ return &riscv013_target;
+ default:
+ /* TODO: once we have proper support for non-examined targets
+ * we should have an assert here */
+ LOG_TARGET_ERROR(target, "Unsupported DTM version: %d",
+ info->dtm_version);
+ return NULL;
}
}
@@ -1857,39 +1857,39 @@ static int riscv_trigger_detect_hit_bits(struct target *target, int64_t *unique_
uint64_t hit_mask = 0;
switch (type) {
- case CSR_TDATA1_TYPE_LEGACY:
- /* Doesn't support hit bit. */
- break;
- case CSR_TDATA1_TYPE_MCONTROL:
- hit_mask = CSR_MCONTROL_HIT;
+ case CSR_TDATA1_TYPE_LEGACY:
+ /* Doesn't support hit bit. */
+ break;
+ case CSR_TDATA1_TYPE_MCONTROL:
+ hit_mask = CSR_MCONTROL_HIT;
+ *need_single_step = true;
+ break;
+ case CSR_TDATA1_TYPE_MCONTROL6:
+ hit_mask = CSR_MCONTROL6_HIT0 | CSR_MCONTROL6_HIT1;
+ if (r->tinfo_version == CSR_TINFO_VERSION_0) {
*need_single_step = true;
- break;
- case CSR_TDATA1_TYPE_MCONTROL6:
- hit_mask = CSR_MCONTROL6_HIT0 | CSR_MCONTROL6_HIT1;
- if (r->tinfo_version == CSR_TINFO_VERSION_0) {
+ } else if (r->tinfo_version == RISCV_TINFO_VERSION_UNKNOWN
+ || r->tinfo_version == CSR_TINFO_VERSION_1) {
+ enum mctrl6hitstatus hits_status = check_mcontrol6_hit_status(target,
+ tdata1, hit_mask);
+ if (hits_status == M6_HIT_ERROR)
+ return ERROR_FAIL;
+ if (hits_status == M6_HIT_BEFORE || hits_status == M6_HIT_NOT_SUPPORTED)
*need_single_step = true;
- } else if (r->tinfo_version == RISCV_TINFO_VERSION_UNKNOWN
- || r->tinfo_version == CSR_TINFO_VERSION_1) {
- enum mctrl6hitstatus hits_status = check_mcontrol6_hit_status(target,
- tdata1, hit_mask);
- if (hits_status == M6_HIT_ERROR)
- return ERROR_...
[truncated message content] |
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