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From: oharboe at B. <oh...@ma...> - 2009-04-27 14:02:08
|
Author: oharboe
Date: 2009-04-27 14:02:07 +0200 (Mon, 27 Apr 2009)
New Revision: 1543
Modified:
trunk/src/target/arm11.c
trunk/src/target/arm11.h
trunk/src/target/arm11_dbgtap.c
Log:
more error handling
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-27 11:24:01 UTC (rev 1542)
+++ trunk/src/target/arm11.c 2009-04-27 12:02:07 UTC (rev 1543)
@@ -932,7 +932,8 @@
u32 next_instruction;
- arm11_read_memory_word(arm11, R(PC), &next_instruction);
+ if ((arm11_read_memory_word(arm11, R(PC), &next_instruction))!=ERROR_OK)
+ return retval;
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
@@ -976,7 +977,8 @@
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ if ((retval=arm11_sc7_run(arm11, brp, asizeof(brp)))!=ERROR_OK)
+ return retval;
/* resume */
@@ -987,7 +989,8 @@
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
- arm11_leave_debug_state(arm11);
+ if ((retval=arm11_leave_debug_state(arm11))!=ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
@@ -1018,7 +1021,8 @@
arm11_sc7_clear_vbw(arm11);
/* save state */
- arm11_on_enter_debug_state(arm11);
+ if((retval = arm11_on_enter_debug_state(arm11))!=ERROR_OK)
+ return retval;
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h 2009-04-27 11:24:01 UTC (rev 1542)
+++ trunk/src/target/arm11.h 2009-04-27 12:02:07 UTC (rev 1543)
@@ -240,18 +240,18 @@
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
-void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
+int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
void arm11_run_instr_data_prepare (arm11_common_t * arm11);
void arm11_run_instr_data_finish (arm11_common_t * arm11);
-void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
+int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
-void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
-void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
+int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
@@ -271,12 +271,12 @@
function returns. */
} arm11_sc7_action_t;
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
/* Mid-level helper functions */
void arm11_sc7_clear_vbw(arm11_common_t * arm11);
void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
+int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
#endif /* ARM11_H */
Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c 2009-04-27 11:24:01 UTC (rev 1542)
+++ trunk/src/target/arm11_dbgtap.c 2009-04-27 12:02:07 UTC (rev 1543)
@@ -254,7 +254,7 @@
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
+int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
@@ -266,11 +266,15 @@
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
+
+ return ERROR_OK;
}
@@ -365,7 +369,7 @@
* \param count Number of opcodes to execute
*
*/
-void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
+int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -379,12 +383,16 @@
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
if (flag)
break;
}
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
@@ -414,7 +422,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -439,7 +447,9 @@
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
@@ -455,11 +465,15 @@
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
+
+ return ERROR_OK;
}
/** JTAG path for arm11_run_instr_data_to_core_noack
@@ -495,7 +509,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -536,7 +550,9 @@
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
size_t error_count = 0;
@@ -551,6 +567,8 @@
if (error_count)
LOG_ERROR("Transfer errors " ZU, error_count);
+
+ return ERROR_OK;
}
@@ -565,9 +583,9 @@
* \param data Data word to be passed to the core via DTR
*
*/
-void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
{
- arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
+ return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
@@ -584,7 +602,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -607,7 +625,9 @@
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
@@ -615,6 +635,8 @@
*data++ = Data;
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
@@ -666,7 +688,7 @@
* \param count Number of instructions in the list.
*
*/
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
@@ -706,7 +728,9 @@
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
@@ -738,6 +762,8 @@
{
JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
}}
+
+ return ERROR_OK;
}
/** Clear VCR and all breakpoints and watchpoints via scan chain 7
@@ -798,17 +824,22 @@
* \param result Pointer where to store result
*
*/
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
+int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
{
+ int retval;
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
+ if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK)
+ return retval;
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
- arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
+ if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK)
+ return retval;
arm11_run_instr_data_finish(arm11);
+
+ return ERROR_OK;
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 13:24:05
|
Author: oharboe
Date: 2009-04-27 13:24:01 +0200 (Mon, 27 Apr 2009)
New Revision: 1542
Modified:
trunk/src/target/arm11.c
trunk/src/target/arm11.h
trunk/src/target/arm11_dbgtap.c
Log:
a little bit more error handling in ARM11
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-27 10:37:07 UTC (rev 1541)
+++ trunk/src/target/arm11.c 2009-04-27 11:24:01 UTC (rev 1542)
@@ -48,7 +48,7 @@
#define FNC_INFO_NOTIMPLEMENTED
#endif
-static void arm11_on_enter_debug_state(arm11_common_t * arm11);
+static int arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
@@ -313,16 +313,18 @@
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
FNC_INFO;
+ int retval;
u32 dscr_local_tmp_copy;
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
- *dscr = arm11_read_DSCR(arm11);
+ if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
+ return retval;
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
@@ -353,6 +355,8 @@
arm11_sc7_clear_vbw(arm11);
}
+
+ return ERROR_OK;
}
@@ -366,7 +370,7 @@
* or on other occasions that stop the processor.
*
*/
-static void arm11_on_enter_debug_state(arm11_common_t * arm11)
+static int arm11_on_enter_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
@@ -378,9 +382,10 @@
}}
/* Save DSCR */
+ int retval;
+ if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
+ return retval;
- R(DSCR) = arm11_read_DSCR(arm11);
-
/* Save wDTR */
if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
@@ -514,6 +519,8 @@
arm11_run_instr_data_finish(arm11);
arm11_dump_reg_changes(arm11);
+
+ return ERROR_OK;
}
void arm11_dump_reg_changes(arm11_common_t * arm11)
@@ -546,7 +553,7 @@
* This is called in preparation for the RESTART function.
*
*/
-void arm11_leave_debug_state(arm11_common_t * arm11)
+int arm11_leave_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
@@ -572,7 +579,12 @@
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
- u32 DSCR = arm11_read_DSCR(arm11);
+ u32 DSCR;
+ int retval;
+ if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
+ {
+ return retval;
+ }
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
@@ -632,6 +644,8 @@
}
arm11_record_register_history(arm11);
+
+ return ERROR_OK;
}
void arm11_record_register_history(arm11_common_t * arm11)
@@ -658,11 +672,15 @@
if (arm11->trst_active)
return ERROR_OK;
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+ int retval;
+ if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
+ return retval;
LOG_DEBUG("DSCR %08x", dscr);
- arm11_check_init(arm11, &dscr);
+ if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
+ return retval;
if (dscr & ARM11_DSCR_CORE_HALTED)
{
@@ -747,7 +765,10 @@
while (1)
{
- dscr = arm11_read_DSCR(arm11);
+ int retval;
+ retval = arm11_read_DSCR(arm11, &dscr);
+ if (retval!=ERROR_OK)
+ return retval;
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
@@ -774,7 +795,7 @@
int retval = ERROR_OK;
FNC_INFO;
-
+
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
@@ -851,7 +872,10 @@
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+ retval = arm11_read_DSCR(arm11, &dscr);
+ if (retval!=ERROR_OK)
+ return retval;
LOG_DEBUG("DSCR %08x", dscr);
@@ -961,8 +985,8 @@
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
else
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
-
+
arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
@@ -978,7 +1002,10 @@
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+ retval = arm11_read_DSCR(arm11, &dscr);
+ if (retval!=ERROR_OK)
+ return retval;
LOG_DEBUG("DSCR %08x", dscr);
@@ -1987,7 +2014,7 @@
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
-
+
RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
step_irq_enable)
Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h 2009-04-27 10:37:07 UTC (rev 1541)
+++ trunk/src/target/arm11.h 2009-04-27 11:24:01 UTC (rev 1542)
@@ -91,7 +91,7 @@
bool trst_active;
bool halt_requested; /**< Keep track if arm11_halt() calls occured
during reset. Otherwise do it ASAP. */
-
+
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save processor state */
@@ -239,7 +239,7 @@
void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
-u32 arm11_read_DSCR (arm11_common_t * arm11);
+int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c 2009-04-27 10:37:07 UTC (rev 1541)
+++ trunk/src/target/arm11_dbgtap.c 2009-04-27 11:24:01 UTC (rev 1542)
@@ -216,7 +216,7 @@
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-u32 arm11_read_DSCR(arm11_common_t * arm11)
+int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
@@ -229,14 +229,20 @@
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ {
+ return retval;
+ }
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
- return dscr;
+ *value=dscr;
+
+ return retval;
}
/** Write the Debug Status and Control Register (DSCR)
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 12:37:09
|
Author: oharboe Date: 2009-04-27 12:37:07 +0200 (Mon, 27 Apr 2009) New Revision: 1541 Modified: zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi Log: fix cortex build problems Modified: zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi =================================================================== --- zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi 2009-04-27 10:32:13 UTC (rev 1540) +++ zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi 2009-04-27 10:37:07 UTC (rev 1541) @@ -181,10 +181,16 @@ KEEP (*(.text.*swjdp_scan*)) ; KEEP (*(.text.*ahbap_write_buf_u32*)) ; KEEP (*(.text.*ahbap_write_system_atomic_u32*)) ; + + KEEP (*(.text.*mem_ap_write_atomic_u32*)) ; + KEEP (*(.text.*mem_ap_read_atomic_u32*)) ; + + KEEP (*(.text.*ahbap_read_system_atomic_u32*)) ; KEEP (*(.text.*swjdp_transaction_endcheck*)) ; KEEP (*(.text.*buf_cmp_mask*)) ; KEEP (*(.text.*buf_cpy*)) ; + KEEP (*(.text.*dap_info_command*)) ; . = ALIGN (4); |
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 12:32:17
|
Author: oharboe
Date: 2009-04-27 12:32:13 +0200 (Mon, 27 Apr 2009)
New Revision: 1540
Added:
trunk/src/flash/avrf.c
trunk/src/flash/avrf.h
trunk/src/target/avrt.c
trunk/src/target/avrt.h
Modified:
trunk/src/flash/Makefile.am
trunk/src/flash/flash.c
trunk/src/target/Makefile.am
trunk/src/target/target.c
Log:
SimonQian <sim...@si...> AVR wip
Modified: trunk/src/flash/Makefile.am
===================================================================
--- trunk/src/flash/Makefile.am 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/Makefile.am 2009-04-27 10:32:13 UTC (rev 1540)
@@ -7,10 +7,10 @@
str7x.c str9x.c aduc702x.c nand.c nand_ecc.c \
lpc3180_nand_controller.c stellaris.c str9xpec.c stm32x.c tms470.c \
ecos.c orion_nand.c s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c \
- s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c pic32mx.c
+ s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c pic32mx.c avrf.c
noinst_HEADERS = \
flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h at91sam7_old.h str7x.h \
str9x.h nand.h lpc3180_nand_controller.h stellaris.h str9xpec.h \
stm32x.h tms470.h s3c24xx_nand.h s3c24xx_regs_nand.h lpc288x.h \
- mflash.h ocl.h pic32mx.h
+ mflash.h ocl.h pic32mx.h avrf.h
MAINTAINERCLEANFILES = Makefile.in
Added: trunk/src/flash/avrf.c
===================================================================
--- trunk/src/flash/avrf.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/avrf.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,500 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "avrf.h"
+#include "avrt.h"
+#include "flash.h"
+#include "target.h"
+#include "log.h"
+#include "algorithm.h"
+#include "binarybuffer.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+/* AVR_JTAG_Instructions */
+#define AVR_JTAG_INS_LEN 4
+// Public Instructions:
+#define AVR_JTAG_INS_EXTEST 0x00
+#define AVR_JTAG_INS_IDCODE 0x01
+#define AVR_JTAG_INS_SAMPLE_PRELOAD 0x02
+#define AVR_JTAG_INS_BYPASS 0x0F
+// AVR Specified Public Instructions:
+#define AVR_JTAG_INS_AVR_RESET 0x0C
+#define AVR_JTAG_INS_PROG_ENABLE 0x04
+#define AVR_JTAG_INS_PROG_COMMANDS 0x05
+#define AVR_JTAG_INS_PROG_PAGELOAD 0x06
+#define AVR_JTAG_INS_PROG_PAGEREAD 0x07
+
+// Data Registers:
+#define AVR_JTAG_REG_Bypass_Len 1
+#define AVR_JTAG_REG_DeviceID_Len 32
+
+#define AVR_JTAG_REG_Reset_Len 1
+#define AVR_JTAG_REG_JTAGID_Len 32
+#define AVR_JTAG_REG_ProgrammingEnable_Len 16
+#define AVR_JTAG_REG_ProgrammingCommand_Len 15
+#define AVR_JTAG_REG_FlashDataByte_Len 16
+
+avrf_type_t avft_chips_info[] =
+{
+// name, chip_id, flash_page_size, flash_page_num, eeprom_page_size, eeprom_page_num
+ {"atmega128", 0x9702, 256, 512, 8, 512},
+};
+
+static int avrf_register_commands(struct command_context_s *cmd_ctx);
+static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
+static int avrf_erase(struct flash_bank_s *bank, int first, int last);
+static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last);
+static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int avrf_probe(struct flash_bank_s *bank);
+static int avrf_auto_probe(struct flash_bank_s *bank);
+//static int avrf_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+static int avrf_protect_check(struct flash_bank_s *bank);
+static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size);
+
+static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+extern int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
+extern int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
+
+extern int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
+extern int mcu_write_dr(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
+extern int mcu_execute_queue(void);
+
+flash_driver_t avr_flash =
+{
+ .name = "avr",
+ .register_commands = avrf_register_commands,
+ .flash_bank_command = avrf_flash_bank_command,
+ .erase = avrf_erase,
+ .protect = avrf_protect,
+ .write = avrf_write,
+ .probe = avrf_probe,
+ .auto_probe = avrf_auto_probe,
+ .erase_check = default_flash_mem_blank_check,
+ .protect_check = avrf_protect_check,
+ .info = avrf_info
+};
+
+/* avr program functions */
+static int avr_jtag_reset(avr_common_t *avr, u32 reset)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, reset ,AVR_JTAG_REG_Reset_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtag_read_jtagid(avr_common_t *avr, u32 *id)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
+ avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_enterprogmode(avr_common_t *avr)
+{
+ avr_jtag_reset(avr, 1);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_leaveprogmode(avr_common_t *avr)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ avr_jtag_reset(avr, 0);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_chiperase(avr_common_t *avr)
+{
+ u32 poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do{
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("poll_value = 0x%04X", poll_value);
+ }while(!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_writeflashpage(avr_common_t *avr, u8 *page_buf, u32 buf_size, u32 addr, u32 page_size)
+{
+ u32 i, poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ // load addr high byte
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0700 | ((addr >> 9) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ // load addr low byte
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0300 | ((addr >> 1) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
+
+ for (i = 0; i < page_size; i++)
+ {
+ if (i < buf_size)
+ {
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, page_buf[i], 8);
+ }
+ else
+ {
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xFF, 8);
+ }
+ }
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do{
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("poll_value = 0x%04X", poll_value);
+ }while(!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+/* interface command */
+static int avrf_register_commands(struct command_context_s *cmd_ctx)
+{
+ command_t *avr_cmd = register_command(cmd_ctx, NULL, "avr", NULL, COMMAND_ANY, "avr flash specific commands");
+
+ register_command(cmd_ctx, avr_cmd, "mass_erase", avrf_handle_mass_erase_command, COMMAND_EXEC,
+ "mass erase device");
+
+ return ERROR_OK;
+}
+
+static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+{
+ avrf_flash_bank_t *avrf_info;
+
+ if (argc < 6)
+ {
+ LOG_WARNING("incomplete flash_bank avr configuration");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ avrf_info = malloc(sizeof(avrf_flash_bank_t));
+ bank->driver_priv = avrf_info;
+
+ avrf_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static int avrf_erase(struct flash_bank_s *bank, int first, int last)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+ u32 cur_size, cur_buffer_size, page_size;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ page_size = bank->sectors[0].size;
+ if ((offset % page_size) != 0)
+ {
+ LOG_WARNING("offset 0x%x breaks required %d-byte alignment", offset, page_size);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ LOG_DEBUG("offset is 0x%08X", offset);
+ LOG_DEBUG("count is %d", count);
+
+ if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ {
+ return ERROR_FAIL;
+ }
+
+ cur_size = 0;
+ while(count > 0)
+ {
+ if (count > page_size)
+ {
+ cur_buffer_size = page_size;
+ }
+ else
+ {
+ cur_buffer_size = count;
+ }
+ avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size);
+ count -= cur_buffer_size;
+ cur_size += cur_buffer_size;
+
+ keep_alive();
+ }
+
+ return avr_jtagprg_leaveprogmode(avr);
+}
+
+#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
+#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
+#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
+static int avrf_probe(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+ avrf_flash_bank_t *avrf_info = bank->driver_priv;
+ avr_common_t *avr = target->arch_info;
+ avrf_type_t *avr_info;
+ int i;
+ u32 device_id;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avrf_info->probed = 0;
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO( "device id = 0x%08x", device_id );
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ {
+ LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
+ }
+
+ for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
+ {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
+ {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+ break;
+ }
+ }
+
+ if (i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])))
+ {
+ // chip found
+ bank->base = 0x00000000;
+ bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
+ bank->num_sectors = avr_info->flash_page_num;
+ bank->sectors = malloc(sizeof(flash_sector_t) * avr_info->flash_page_num);
+
+ for (i = 0; i < avr_info->flash_page_num; i++)
+ {
+ bank->sectors[i].offset = i * avr_info->flash_page_size;
+ bank->sectors[i].size = avr_info->flash_page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ avrf_info->probed = 1;
+ return ERROR_OK;
+ }
+ else
+ {
+ // chip not supported
+ LOG_ERROR("0x%X is not support for avr", EXTRACT_PART(device_id));
+
+ avrf_info->probed = 1;
+ return ERROR_FAIL;
+ }
+}
+
+static int avrf_auto_probe(struct flash_bank_s *bank)
+{
+ avrf_flash_bank_t *avrf_info = bank->driver_priv;
+ if (avrf_info->probed)
+ return ERROR_OK;
+ return avrf_probe(bank);
+}
+
+static int avrf_protect_check(struct flash_bank_s *bank)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+ avrf_type_t *avr_info;
+ int i;
+ u32 device_id;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO( "device id = 0x%08x", device_id );
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ {
+ LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
+ }
+
+ for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
+ {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
+ {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+
+ return ERROR_OK;
+ }
+ }
+
+ if (i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])))
+ {
+ // chip found
+ snprintf(buf, buf_size, "%s - Rev: 0x%X", avr_info->name, EXTRACT_VER(device_id));
+ return ERROR_OK;
+ }
+ else
+ {
+ // chip not supported
+ snprintf(buf, buf_size, "Cannot identify target as a avr\n");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+}
+
+static int avrf_mass_erase(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ || (ERROR_OK != avr_jtagprg_chiperase(avr))
+ || (ERROR_OK != avr_jtagprg_leaveprogmode(avr)))
+ {
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ flash_bank_t *bank;
+ int i;
+
+ if (argc < 1)
+ {
+ command_print(cmd_ctx, "avr mass_erase <bank>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ if (avrf_mass_erase(bank) == ERROR_OK)
+ {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ {
+ bank->sectors[i].is_erased = 1;
+ }
+
+ command_print(cmd_ctx, "avr mass erase complete");
+ }
+ else
+ {
+ command_print(cmd_ctx, "avr mass erase failed");
+ }
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
Added: trunk/src/flash/avrf.h
===================================================================
--- trunk/src/flash/avrf.h 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/avrf.h 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,39 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef AVRF_H
+#define AVRF_H
+
+typedef struct avrf_type_s
+{
+ char name[15];
+ u16 chip_id;
+ int flash_page_size;
+ int flash_page_num;
+ int eeprom_page_size;
+ int eeprom_page_num;
+} avrf_type_t;
+
+typedef struct avrf_flash_bank_s
+{
+ int ppage_size;
+ int probed;
+} avrf_flash_bank_t;
+
+#endif /* AVRF_H */
Modified: trunk/src/flash/flash.c
===================================================================
--- trunk/src/flash/flash.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/flash.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -77,6 +77,7 @@
extern flash_driver_t lpc288x_flash;
extern flash_driver_t ocl_flash;
extern flash_driver_t pic32mx_flash;
+extern flash_driver_t avr_flash;
flash_driver_t *flash_drivers[] = {
&lpc2000_flash,
@@ -94,6 +95,7 @@
&lpc288x_flash,
&ocl_flash,
&pic32mx_flash,
+ &avr_flash,
NULL,
};
Modified: trunk/src/target/Makefile.am
===================================================================
--- trunk/src/target/Makefile.am 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/Makefile.am 2009-04-27 10:32:13 UTC (rev 1540)
@@ -13,11 +13,11 @@
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c arm_adi_v5.c \
etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
- mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
+ mips32_pracc.c mips32_dmaacc.c mips_ejtag.c avrt.c
noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h arm_adi_v5.h \
- etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
+ etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h avrt.h
nobase_dist_pkglib_DATA =
nobase_dist_pkglib_DATA += xscale/debug_handler.bin
Added: trunk/src/target/avrt.c
===================================================================
--- trunk/src/target/avrt.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/avrt.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,354 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "avrt.h"
+
+#include "register.h"
+#include "target.h"
+#include "log.h"
+#include "jtag.h"
+#include "binarybuffer.h"
+#include "time_support.h"
+#include "breakpoints.h"
+#include "fileio.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <errno.h>
+
+#define AVR_JTAG_INS_LEN 4
+
+/* cli handling */
+int avr_register_commands(struct command_context_s *cmd_ctx);
+
+/* forward declarations */
+int avr_target_create(struct target_s *target, Jim_Interp *interp);
+int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
+int avr_quit(void);
+
+int avr_arch_state(struct target_s *target);
+int avr_poll(target_t *target);
+int avr_halt(target_t *target);
+int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
+int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+
+int avr_assert_reset(target_t *target);
+int avr_deassert_reset(target_t *target);
+int avr_soft_reset_halt(struct target_s *target);
+
+/* IR and DR functions */
+int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
+int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
+
+int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
+int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti);
+int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
+int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
+int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
+int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
+int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
+int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
+int mcu_execute_queue(void);
+
+target_type_t avr_target =
+{
+ .name = "avr",
+
+ .poll = avr_poll,
+ .arch_state = avr_arch_state,
+
+ .target_request_data = NULL,
+
+ .halt = avr_halt,
+ .resume = avr_resume,
+ .step = avr_step,
+
+ .assert_reset = avr_assert_reset,
+ .deassert_reset = avr_deassert_reset,
+ .soft_reset_halt = avr_soft_reset_halt,
+/*
+ .get_gdb_reg_list = avr_get_gdb_reg_list,
+
+ .read_memory = avr_read_memory,
+ .write_memory = avr_write_memory,
+ .bulk_write_memory = avr_bulk_write_memory,
+ .checksum_memory = avr_checksum_memory,
+ .blank_check_memory = avr_blank_check_memory,
+
+ .run_algorithm = avr_run_algorithm,
+
+ .add_breakpoint = avr_add_breakpoint,
+ .remove_breakpoint = avr_remove_breakpoint,
+ .add_watchpoint = avr_add_watchpoint,
+ .remove_watchpoint = avr_remove_watchpoint,
+*/
+ .register_commands = avr_register_commands,
+ .target_create = avr_target_create,
+ .init_target = avr_init_target,
+ .quit = avr_quit,
+/*
+ .virt2phys = avr_virt2phys,
+ .mmu = avr_mmu
+*/
+};
+
+int avr_register_commands(struct command_context_s *cmd_ctx)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_target_create(struct target_s *target, Jim_Interp *interp)
+{
+ avr_common_t *avr = calloc(1, sizeof(avr_common_t));
+
+ avr->jtag_info.tap = target->tap;
+ target->arch_info = avr;
+
+ return ERROR_OK;
+}
+
+int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_quit(void)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_arch_state(struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_poll(target_t *target)
+{
+ if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
+ {
+ target->state = TARGET_HALTED;
+ }
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_halt(target_t *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_assert_reset(target_t *target)
+{
+ target->state = TARGET_RESET;
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_deassert_reset(target_t *target)
+{
+ target->state = TARGET_RUNNING;
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_soft_reset_halt(struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_jtag_senddat(jtag_tap_t *tap, u32* dr_in, u32 dr_out, int len)
+{
+ return mcu_write_dr_u32(tap, dr_in, dr_out, len, 1);
+}
+
+int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out)
+{
+ return mcu_write_ir_u8(tap, ir_in, ir_out, AVR_JTAG_INS_LEN, 1);
+}
+
+/* IR and DR functions */
+int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti)
+{
+ if (NULL == tap)
+ {
+ LOG_ERROR("invalid tap");
+ return ERROR_FAIL;
+ }
+ if (ir_len != tap->ir_length)
+ {
+ LOG_ERROR("invalid ir_len");
+ return ERROR_FAIL;
+ }
+
+ {
+ scan_field_t field[1];
+
+ field[0].tap = tap;
+ field[0].num_bits = tap->ir_length;
+ field[0].out_value = ir_out;
+ field[0].out_mask = NULL;
+ field[0].in_value = ir_in;
+ field[0].in_check_value = NULL;
+ field[0].in_check_mask = NULL;
+ field[0].in_handler = NULL;
+ field[0].in_handler_priv = NULL;
+ jtag_add_plain_ir_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
+ }
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti)
+{
+ if (NULL == tap)
+ {
+ LOG_ERROR("invalid tap");
+ return ERROR_FAIL;
+ }
+
+ {
+ scan_field_t field[1];
+
+ field[0].tap = tap;
+ field[0].num_bits = dr_len;
+ field[0].out_value = dr_out;
+ field[0].out_mask = NULL;
+ field[0].in_value = dr_in;
+ field[0].in_check_value = NULL;
+ field[0].in_check_mask = NULL;
+ field[0].in_handler = NULL;
+ field[0].in_handler_priv = NULL;
+ jtag_add_plain_dr_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
+ }
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 8)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 8");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, ir_in, &ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u8(jtag_tap_t *tap, u8 *dr_in, u8 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 8)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 8");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, dr_in, &dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 16)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 16");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u16(jtag_tap_t *tap, u16 *dr_in, u16 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 16)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 16");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 32)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 32");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u32(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 32)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 32");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_execute_queue(void)
+{
+ return jtag_execute_queue();
+}
Added: trunk/src/target/avrt.h
===================================================================
--- trunk/src/target/avrt.h 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/avrt.h 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,33 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef AVRT_H
+#define AVRT_H
+
+typedef struct mcu_jtag_s
+{
+ jtag_tap_t *tap;
+} mcu_jtag_t;
+
+typedef struct avr_common_s
+{
+ mcu_jtag_t jtag_info;
+} avr_common_t;
+
+#endif /* AVRT_H */
Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/target.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -105,6 +105,7 @@
extern target_type_t cortexm3_target;
extern target_type_t arm11_target;
extern target_type_t mips_m4k_target;
+extern target_type_t avr_target;
target_type_t *target_types[] =
{
@@ -119,6 +120,7 @@
&cortexm3_target,
&arm11_target,
&mips_m4k_target,
+ &avr_target,
NULL,
};
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 12:16:17
|
Author: oharboe
Date: 2009-04-27 12:16:16 +0200 (Mon, 27 Apr 2009)
New Revision: 1539
Added:
trunk/src/target/target/mega128.cfg
Log:
SimonQian <sim...@si...> AVR support
Added: trunk/src/target/target/mega128.cfg
===================================================================
--- trunk/src/target/target/mega128.cfg 2009-04-27 10:05:15 UTC (rev 1538)
+++ trunk/src/target/target/mega128.cfg 2009-04-27 10:16:16 UTC (rev 1539)
@@ -0,0 +1,42 @@
+# for avr
+
+ set _CHIPNAME avr
+ set _ENDIAN little
+
+# jtag speed
+jtag_khz 4500
+
+reset_config srst_only
+jtag_nsrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x8970203F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+flash bank avr 0 0 0 0 0
+
+#to use it, script will be like:
+#init
+#jtag_khz 4500
+#reset init
+#verify_ircapture disable
+#
+#halt
+#wait halt
+#poll
+#avr mass_erase 0
+#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
+#reset run
+#shutdown
+#
+# For more information about the configuration files, take a look at:
+# openocd.texi
|
|
From: <ml...@ma...> - 2009-04-27 12:05:17
|
Author: mlu
Date: 2009-04-27 12:05:15 +0200 (Mon, 27 Apr 2009)
New Revision: 1538
Removed:
trunk/src/target/cortex_swjdp.c
trunk/src/target/cortex_swjdp.h
Log:
Deleted depreciated files ( new versions are arm_adi_v5.c/h )
Deleted: trunk/src/target/cortex_swjdp.c
===================================================================
--- trunk/src/target/cortex_swjdp.c 2009-04-27 09:12:18 UTC (rev 1537)
+++ trunk/src/target/cortex_swjdp.c 2009-04-27 10:05:15 UTC (rev 1538)
@@ -1,1029 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2006 by Magnus Lundin *
- * lu...@ml... *
- * *
- * Copyright (C) 2008 by Spencer Oliver *
- * sp...@sp... *
- * *
- * Copyright (C) 2009 by Oyvind Harboe *
- * oyv...@zy... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-/***************************************************************************
- * *
- * CoreSight (Light?) SerialWireJtagDebugPort *
- * *
- * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
- * Cortex-M3(tm) TRM, ARM DDI 0337C *
- * *
-***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "replacements.h"
-
-#include "cortex_m3.h"
-#include "cortex_swjdp.h"
-#include "jtag.h"
-#include "log.h"
-#include "time_support.h"
-#include <stdlib.h>
-
-/*
- * Transaction Mode:
- * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
- * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
- * result checking until swjdp_end_transaction()
- * This must be done before using or deallocating any return variables.
- * swjdp->trans_mode == TRANS_MODE_ATOMIC
- * All reads and writes to the AHB bus are checked for valid completion, and return values
- * are immediatley available.
-*/
-
-/***************************************************************************
- * *
- * DPACC and APACC scanchain access through JTAG-DR *
- * *
-***************************************************************************/
-
-/* Scan out and in from target ordered u8 buffers */
-int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
-{
- scan_field_t fields[2];
- u8 out_addr_buf;
-
- jtag_add_end_state(TAP_IDLE);
- arm_jtag_set_instr(jtag_info, instr, NULL);
-
- fields[0].tap = jtag_info->tap;
- fields[0].num_bits = 3;
- buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
- fields[0].out_value = &out_addr_buf;
- fields[0].out_mask = NULL;
- fields[0].in_value = ack;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].tap = jtag_info->tap;
- fields[1].num_bits = 32;
- fields[1].out_value = outvalue;
- fields[1].out_mask = NULL;
- fields[1].in_value = invalue;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
-
- jtag_add_dr_scan(2, fields, TAP_INVALID);
-
- return ERROR_OK;
-}
-
-/* Scan out and in from host ordered u32 variables */
-int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
-{
- scan_field_t fields[2];
- u8 out_value_buf[4];
- u8 out_addr_buf;
-
- jtag_add_end_state(TAP_IDLE);
- arm_jtag_set_instr(jtag_info, instr, NULL);
-
- fields[0].tap = jtag_info->tap;
- fields[0].num_bits = 3;
- buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
- fields[0].out_value = &out_addr_buf;
- fields[0].out_mask = NULL;
- fields[0].in_value = ack;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].tap = jtag_info->tap;
- fields[1].num_bits = 32;
- buf_set_u32(out_value_buf, 0, 32, outvalue);
- fields[1].out_value = out_value_buf;
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- if (invalue)
- {
- fields[1].in_handler = arm_jtag_buf_to_u32;
- fields[1].in_handler_priv = invalue;
- }
- else
- {
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- }
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
-
- jtag_add_dr_scan(2, fields, TAP_INVALID);
-
- return ERROR_OK;
-}
-
-/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
-int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
-{
- swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
- if ((RnW == DPAP_READ) && (invalue != NULL))
- {
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
- }
-
- /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
- if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- {
- return swjdp_transaction_endcheck(swjdp);
- }
-
- return ERROR_OK;
-}
-
-int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
-{
- swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
- if ((RnW==DPAP_READ) && (invalue != NULL))
- {
- swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
- }
-
- /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
- if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- {
- return swjdp_transaction_endcheck(swjdp);
- }
-
- return ERROR_OK;
-}
-
-int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
-{
- int retval;
- u32 ctrlstat;
-
- /* too expensive to call keep_alive() here */
-
-#if 0
- /* Danger!!!! BROKEN!!!! */
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
- R956 introduced the check on return value here and now Michael Schwingen reports
- that this code no longer works....
-
- https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
- */
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- {
- LOG_ERROR("BUG: Why does this fail the first time????");
- }
- /* Why??? second time it works??? */
-#endif
-
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
- swjdp->ack = swjdp->ack & 0x7;
-
- if (swjdp->ack != 2)
- {
- long long then=timeval_ms();
- while (swjdp->ack != 2)
- {
- if (swjdp->ack == 1)
- {
- if ((timeval_ms()-then) > 1000)
- {
- LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
- else
- {
- LOG_WARNING("Invalid ACK in SWJDP transaction");
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- swjdp->ack = swjdp->ack & 0x7;
- }
- } else
- {
- /* common code path avoids fn to timeval_ms() */
- }
-
- /* Check for STICKYERR and STICKYORUN */
- if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
- {
- LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
- /* Check power to debug regions */
- if ((ctrlstat & 0xf0000000) != 0xf0000000)
- {
- ahbap_debugport_init(swjdp);
- }
- else
- {
- u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
-
- /* Print information about last AHBAP access */
- LOG_ERROR("AHBAP: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
- if (ctrlstat & SSTICKYORUN)
- LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
-
- if (ctrlstat & SSTICKYERR)
- LOG_ERROR("SWJ-DP STICKY ERROR");
-
- /* Clear Sticky Error Bits */
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
- LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
-
- /* Can we find out the reason for the error ?? */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
- ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
- ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
- ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
- LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
- }
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- return ERROR_OK;
-}
-
-/***************************************************************************
- * *
- * DP and AHB-AP register access through APACC and DPACC *
- * *
-***************************************************************************/
-
-int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
-{
- return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
-}
-
-int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
-{
- return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
-}
-
-int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
-{
- u32 select;
- select = (reg_addr & 0xFF0000F0);
-
- if (select != swjdp->dp_select_value)
- {
- swjdp_write_dpacc(swjdp, select, DP_SELECT);
- swjdp->dp_select_value = select;
- }
-
- return ERROR_OK;
-}
-
-int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
-{
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
-
- return ERROR_OK;
-}
-
-int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
-{
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
-
- return ERROR_OK;
-}
-int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
-{
- u8 out_value_buf[4];
-
- buf_set_u32(out_value_buf, 0, 32, value);
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
-
- return ERROR_OK;
-}
-
-int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
-{
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
-
- return ERROR_OK;
-}
-
-/***************************************************************************
- * *
- * AHB-AP access to memory and system registers on AHB bus *
- * *
-***************************************************************************/
-
-int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
-{
- csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
- if (csw != swjdp->ap_csw_value)
- {
- /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
- ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
- swjdp->ap_csw_value = csw;
- }
- if (tar != swjdp->ap_tar_value)
- {
- /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
- ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
- swjdp->ap_tar_value = tar;
- }
- if (csw & CSW_ADDRINC_MASK)
- {
- /* Do not cache TAR value when autoincrementing */
- swjdp->ap_tar_value = -1;
- }
- return ERROR_OK;
-}
-
-/*****************************************************************************
-* *
-* ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
-* *
-* Read a u32 value from memory or system register *
-* Functionally equivalent to target_read_u32(target, address, u32 *value), *
-* but with less overhead *
-*****************************************************************************/
-int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
-{
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
- ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
-
- return ERROR_OK;
-}
-
-int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
-{
- ahbap_read_system_u32(swjdp, address, value);
-
- return swjdp_transaction_endcheck(swjdp);
-}
-
-/*****************************************************************************
-* *
-* ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
-* *
-* Write a u32 value to memory or system register *
-* *
-*****************************************************************************/
-int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
-{
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
-
- return ERROR_OK;
-}
-
-int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
-{
- ahbap_write_system_u32(swjdp, address, value);
-
- return swjdp_transaction_endcheck(swjdp);
-}
-
-/*****************************************************************************
-* *
-* ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
-* *
-* Write a buffer in target order (little endian) *
-* *
-*****************************************************************************/
-int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
- u32 adr = address;
- u8* pBuffer = buffer;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- count >>= 2;
- wcount = count;
-
- /* if we have an unaligned access - reorder data */
- if (adr & 0x3u)
- {
- for (writecount = 0; writecount < count; writecount++)
- {
- int i;
- outvalue = *((u32*)pBuffer);
-
- for (i = 0; i < 4; i++ )
- {
- *((u8*)pBuffer + (adr & 0x3)) = outvalue;
- outvalue >>= 8;
- adr++;
- }
- pBuffer += 4;
- }
- }
-
- while (wcount > 0)
- {
- /* Adjust to write blocks within 4K aligned boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 2;
- if (wcount < blocksize)
- blocksize = wcount;
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
-
- for (writecount = 0; writecount < blocksize; writecount++)
- {
- ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
- }
-
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
- {
- wcount = wcount - blocksize;
- address = address + 4 * blocksize;
- buffer = buffer + 4 * blocksize;
- }
- else
- {
- errorcount++;
- }
-
- if (errorcount > 1)
- {
- LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- return retval;
-}
-
-int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
- int wcount, blocksize, writecount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count >> 1;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 1;
-
- if (wcount < blocksize)
- blocksize = wcount;
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
-
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
- writecount = blocksize;
-
- do
- {
- nbytes = MIN((writecount << 1), 4);
-
- if (nbytes < 4 )
- {
- if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- address += nbytes >> 1;
- }
- else
- {
- outvalue = *((u32*)buffer);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer + (address & 0x3)) = outvalue;
- outvalue >>= 8;
- address++;
- }
-
- outvalue = *((u32*)buffer);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- buffer += nbytes >> 1;
- writecount -= nbytes >> 1;
-
- } while (writecount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
- outvalue = *((u16*)buffer) << 8 * (address & 0x3);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
- retval = swjdp_transaction_endcheck(swjdp);
- count -= 2;
- address += 2;
- buffer += 2;
- }
-
- return retval;
-}
-
-int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
- int wcount, blocksize, writecount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address));
-
- if (wcount < blocksize)
- blocksize = wcount;
-
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
- writecount = blocksize;
-
- do
- {
- nbytes = MIN(writecount, 4);
-
- if (nbytes < 4 )
- {
- if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- address += nbytes;
- }
- else
- {
- outvalue = *((u32*)buffer);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer + (address & 0x3)) = outvalue;
- outvalue >>= 8;
- address++;
- }
-
- outvalue = *((u32*)buffer);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- buffer += nbytes;
- writecount -= nbytes;
-
- } while (writecount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
- outvalue = *((u8*)buffer) << 8 * (address & 0x3);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
- retval = swjdp_transaction_endcheck(swjdp);
- count--;
- address++;
- buffer++;
- }
-
- return retval;
-}
-
-/*********************************************************************************
-* *
-* ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
-* *
-* Read block fast in target order (little endian) into a buffer *
-* *
-**********************************************************************************/
-int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
- u32 adr = address;
- u8* pBuffer = buffer;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- count >>= 2;
- wcount = count;
-
- while (wcount > 0)
- {
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 2;
- if (wcount < blocksize)
- blocksize = wcount;
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
-
- /* Scan out first read */
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
- for (readcount = 0; readcount < blocksize - 1; readcount++)
- {
- /* Scan out read instruction and scan in previous value */
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
- }
-
- /* Scan in last value */
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
- {
- wcount = wcount - blocksize;
- address += 4 * blocksize;
- buffer += 4 * blocksize;
- }
- else
- {
- errorcount++;
- }
-
- if (errorcount > 1)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- /* if we have an unaligned access - reorder data */
- if (adr & 0x3u)
- {
- for (readcount = 0; readcount < count; readcount++)
- {
- int i;
- u32 data = *((u32*)pBuffer);
-
- for (i = 0; i < 4; i++ )
- {
- *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
- pBuffer++;
- adr++;
- }
- }
- }
-
- return retval;
-}
-
-int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue;
- int retval = ERROR_OK;
- int wcount, blocksize, readcount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count >> 1;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 1;
- if (wcount < blocksize)
- blocksize = wcount;
-
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
- readcount = blocksize;
-
- do
- {
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- nbytes = MIN((readcount << 1), 4);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- buffer++;
- address++;
- }
-
- readcount -= (nbytes >> 1);
- } while (readcount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue, i;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- retval = swjdp_transaction_endcheck(swjdp);
- if (address & 0x1)
- {
- for (i = 0; i < 2; i++ )
- {
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- buffer++;
- address++;
- }
- }
- else
- {
- *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
- address += 2;
- buffer += 2;
- }
- count -= 2;
- }
-
- return retval;
-}
-
-int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue;
- int retval = ERROR_OK;
- int wcount, blocksize, readcount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address));
-
- if (wcount < blocksize)
- blocksize = wcount;
-
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
- readcount = blocksize;
-
- do
- {
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- nbytes = MIN(readcount, 4);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- buffer++;
- address++;
- }
-
- readcount -= nbytes;
- } while (readcount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- retval = swjdp_transaction_endcheck(swjdp);
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- count--;
- address++;
- buffer++;
- }
-
- return retval;
-}
-
-int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
-{
- int retval;
- u32 dcrdr;
-
- /* because the DCB_DCRDR is used for the emulated dcc channel
- * we gave to save/restore the DCB_DCRDR when used */
-
- ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum );
-
- /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
-
- ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
- retval = swjdp_transaction_endcheck(swjdp);
- return retval;
-}
-
-int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
-{
- int retval;
- u32 dcrdr;
-
- /* because the DCB_DCRDR is used for the emulated dcc channel
- * we gave to save/restore the DCB_DCRDR when used */
-
- ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
-
- /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
-
- ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
- retval = swjdp_transaction_endcheck(swjdp);
- return retval;
-}
-
-int ahbap_debugport_init(swjdp_common_t *swjdp)
-{
- u32 idreg, romaddr, dummy;
- u32 ctrlstat;
- int cnt = 0;
- int retval;
-
- LOG_DEBUG(" ");
-
- swjdp->ap_csw_value = -1;
- swjdp->ap_tar_value = -1;
- swjdp->trans_mode = TRANS_MODE_ATOMIC;
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
- swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
-
- swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
-
- swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
- swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
- /* Check that we have debug power domains activated */
- while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
- {
- LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
- swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- alive_sleep(10);
- }
-
- while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
- {
- LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
- swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- alive_sleep(10);
- }
-
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
- /* With debug power on we can activate OVERRUN checking */
- swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
- swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
-
- ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
- ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
-
- LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
-
- return ERROR_OK;
-}
Deleted: trunk/src/target/cortex_swjdp.h
===================================================================
--- trunk/src/target/cortex_swjdp.h 2009-04-27 09:12:18 UTC (rev 1537)
+++ trunk/src/target/cortex_swjdp.h 2009-04-27 10:05:15 UTC (rev 1538)
@@ -1,133 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2006 by Magnus Lundin *
- * lu...@ml... *
- * *
- * Copyright (C) 2008 by Spencer Oliver *
- * sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifndef CORTEX_SWJDP_H
-#define CORTEX_SWJDP_H
-
-#include "target.h"
-#include "register.h"
-#include "arm_jtag.h"
-
-#define SWJDP_IR_DPACC 0xA
-#define SWJDP_IR_APACC 0xB
-
-#define DPAP_WRITE 0
-#define DPAP_READ 1
-#define DP_ZERO 0
-#define DP_CTRL_STAT 0x4
-#define DP_SELECT 0x8
-#define DP_RDBUFF 0xC
-
-#define CORUNDETECT (1<<0)
-#define SSTICKYORUN (1<<1)
-#define SSTICKYERR (1<<5)
-#define CDBGRSTREQ (1<<26)
-#define CDBGRSTACK (1<<27)
-#define CDBGPWRUPREQ (1<<28)
-#define CDBGPWRUPACK (1<<29)
-#define CSYSPWRUPREQ (1<<30)
-#define CSYSPWRUPACK (1<<31)
-
-#define AHBAP_CSW 0x00
-#define AHBAP_TAR 0x04
-#define AHBAP_DRW 0x0C
-#define AHBAP_BD0 0x10
-#define AHBAP_BD1 0x14
-#define AHBAP_BD2 0x18
-#define AHBAP_BD3 0x1C
-#define AHBAP_DBGROMA 0xF8
-#define AHBAP_IDR 0xFC
-
-#define CSW_8BIT 0
-#define CSW_16BIT 1
-#define CSW_32BIT 2
-
-#define CSW_ADDRINC_MASK (3<<4)
-#define CSW_ADDRINC_OFF 0
-#define CSW_ADDRINC_SINGLE (1<<4)
-#define CSW_ADDRINC_PACKED (2<<4)
-#define CSW_HPROT (1<<25)
-#define CSW_MASTER_DEBUG (1<<29)
-#define CSW_DBGSWENABLE (1<<31)
-
-/* transaction mode */
-#define TRANS_MODE_NONE 0
-/* Transaction waits for previous to complete */
-#define TRANS_MODE_ATOMIC 1
-/* Freerunning transactions with delays and overrun checking */
-#define TRANS_MODE_COMPOSITE 2
-
-typedef struct swjdp_reg_s
-{
- int addr;
- arm_jtag_t *jtag_info;
-} swjdp_reg_t;
-
-typedef struct swjdp_common_s
-{
- arm_jtag_t *jtag_info;
- /* Control config */
- u32 dp_ctrl_stat;
- /* Register select cache */
- u32 dp_select_value;
- u32 ap_csw_value;
- u32 ap_tar_value;
- /* information about current pending SWjDP-AHBAP transaction */
- u8 trans_mode;
- u8 trans_rw;
- u8 ack;
-} swjdp_common_t;
-
-/* Internal functions used in the module, partial transactions, use with caution */
-extern int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
-/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
-extern int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
-/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr); */
-extern int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
-extern int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
-
-/* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
-extern int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
-extern int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value);
-extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
-
-/* External interface, complete atomic operations */
-/* Host endian word transfer of single memory and system registers */
-extern int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
-extern int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
-
-/* Host endian word transfers of processor core registers */
-extern int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum);
-extern int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum);
-
-extern int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-
-extern int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-
-/* Initialisation of the debug system, power domains and registers */
-extern int ahbap_debugport_init(swjdp_common_t *swjdp);
-
-#endif
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 11:12:21
|
Author: oharboe
Date: 2009-04-27 11:12:18 +0200 (Mon, 27 Apr 2009)
New Revision: 1537
Modified:
trunk/src/jtag/jtag.c
Log:
Some devices such as AVR will return 0xffffffff instead of the TDI
data at the end of the chain. Added kludge to handle this.
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-04-27 08:29:28 UTC (rev 1536)
+++ trunk/src/jtag/jtag.c 2009-04-27 09:12:18 UTC (rev 1537)
@@ -1531,7 +1531,9 @@
u32 part;
u32 version;
- if (idcode == 0x000000FF)
+ /* some devices, such as AVR will output all 1's instead of TDI
+ input value at end of chain. */
+ if ((idcode == 0x000000FF)||(idcode == 0xFFFFFFFF))
{
int unexpected=0;
/* End of chain (invalid manufacturer ID)
@@ -1548,7 +1550,7 @@
for (bit_count += 32; bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;bit_count += 32)
{
idcode = buf_get_u32(idcode_buffer, bit_count, 32);
- if (unexpected||(idcode != 0x000000FF))
+ if (unexpected||((idcode != 0x000000FF)&&(idcode != 0xFFFFFFFF)))
{
LOG_WARNING("Unexpected idcode after end of chain! %d 0x%08x", bit_count, idcode);
unexpected = 1;
@@ -3306,7 +3308,7 @@
tap_state_t last_state;
- // set startstate (and possibly last, if tap_bits == 0)
+ // set startstate (and possibly last, if tap_bits == 0)
last_state = next_state;
DEBUG_JTAG_IO("TAP/SM: START state: %s", tap_state_name(next_state));
|
|
From: <ml...@ma...> - 2009-04-27 10:29:30
|
Author: mlu
Date: 2009-04-27 10:29:28 +0200 (Mon, 27 Apr 2009)
New Revision: 1536
Modified:
trunk/src/target/Makefile.am
trunk/src/target/armv7m.c
trunk/src/target/armv7m.h
trunk/src/target/cortex_m3.c
trunk/src/target/cortex_m3.h
Log:
Changed armv7m and cortexm3 to use nev arm_adi_v5 instead of cortex_swjdp.
Added support for accessport ROM table identification, dap command.
Modified: trunk/src/target/Makefile.am
===================================================================
--- trunk/src/target/Makefile.am 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/Makefile.am 2009-04-27 08:29:28 UTC (rev 1536)
@@ -11,12 +11,12 @@
noinst_LIBRARIES = libtarget.a
libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
- arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \
+ arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c arm_adi_v5.c \
etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
- arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
+ arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h arm_adi_v5.h \
etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
nobase_dist_pkglib_DATA =
Modified: trunk/src/target/armv7m.c
===================================================================
--- trunk/src/target/armv7m.c 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/armv7m.c 2009-04-27 08:29:28 UTC (rev 1536)
@@ -550,6 +550,12 @@
int armv7m_register_commands(struct command_context_s *cmd_ctx)
{
+ command_t *arm_adi_v5_dap_cmd;
+
+ arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "select a different AP [num] (default 0)");
+
return ERROR_OK;
}
@@ -695,3 +701,45 @@
return ERROR_OK;
}
+
+int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 apsel, apid;
+ int retval;
+
+ apsel = 0;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ dap_ap_select(swjdp, apsel);
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid);
+
+ return retval;
+}
+
+int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ int retval;
+ u32 apsel;
+
+ apsel = 0;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ retval = dap_info_command(cmd_ctx, swjdp, apsel);
+
+ return retval;
+}
+
Modified: trunk/src/target/armv7m.h
===================================================================
--- trunk/src/target/armv7m.h 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/armv7m.h 2009-04-27 08:29:28 UTC (rev 1536)
@@ -29,6 +29,7 @@
#include "register.h"
#include "target.h"
#include "arm_jtag.h"
+#include "arm_adi_v5.h"
/* define for enabling armv7 gdb workarounds */
#if 1
@@ -78,6 +79,8 @@
reg_cache_t *core_cache;
enum armv7m_mode core_mode;
int exception_number;
+ swjdp_common_t swjdp_info;
+
/* Direct processor core register read and writes */
int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/cortex_m3.c 2009-04-27 08:29:28 UTC (rev 1536)
@@ -22,6 +22,10 @@
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * *
+ * *
+ * Cortex-M3(tm) TRM, ARM DDI 0337C *
+ * *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
@@ -101,19 +105,70 @@
.quit = cortex_m3_quit
};
+int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
+{
+ int retval;
+ u32 dcrdr;
+
+ /* because the DCB_DCRDR is used for the emulated dcc channel
+ * we gave to save/restore the DCB_DCRDR when used */
+
+ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum );
+
+ /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+
+ mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ return retval;
+}
+
+int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
+{
+ int retval;
+ u32 dcrdr;
+
+ /* because the DCB_DCRDR is used for the emulated dcc channel
+ * we gave to save/restore the DCB_DCRDR when used */
+
+ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
+
+ mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ return retval;
+}
+
+
int cortex_m3_write_debug_halt_mask(target_t *target, u32 mask_on, u32 mask_off)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
/* create new register mask */
cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
- return ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
+ return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
}
int cortex_m3_clear_halt(target_t *target)
@@ -121,15 +176,15 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
- ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
- ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+ mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
return ERROR_OK;
@@ -140,7 +195,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 dhcsr_save;
/* backup dhcsr reg */
@@ -148,8 +203,8 @@
/* mask interrupts if not done already */
if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
- ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
- ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
LOG_DEBUG(" ");
/* restore dhcsr reg */
@@ -163,17 +218,16 @@
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 savedram;
int retvalue;
- ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
- ahbap_write_system_u32(swjdp, 0x20000000, opcode);
- ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
+ mem_ap_read_u32(swjdp, 0x20000000, &savedram);
+ mem_ap_write_u32(swjdp, 0x20000000, opcode);
+ cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15);
cortex_m3_single_step_core(target);
armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
- retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram);
+ retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram);
return retvalue;
}
@@ -200,28 +254,28 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
- ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
/* this regsiter is used for emulated dcc channel */
- ahbap_write_system_u32(swjdp, DCB_DCRDR, 0);
+ mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
/* Enable debug requests */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
/* clear any interrupt masking */
cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
/* Enable trace and dwt */
- ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
+ mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
/* Monitor bus faults */
- ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
+ mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
/* Enable FPB */
target_write_u32(target, FP_CTRL, 3);
@@ -245,7 +299,7 @@
armv7m_invalidate_core_regs(target);
/* make sure we have latest dhcsr flags */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
return ERROR_OK;
}
@@ -283,36 +337,35 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
- ahbap_read_system_u32(swjdp, NVIC_SHCSR, &shcsr);
+ mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
switch (armv7m->exception_number)
{
case 2: /* NMI */
break;
case 3: /* Hard Fault */
- ahbap_read_system_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
if (except_sr & 0x40000000)
{
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &cfsr);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
}
break;
case 4: /* Memory Management */
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
- ahbap_read_system_u32(swjdp, NVIC_MMFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
break;
case 5: /* Bus Fault */
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
- ahbap_read_system_u32(swjdp, NVIC_BFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
break;
case 6: /* Usage Fault */
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
- ahbap_read_system_u32(swjdp, NVIC_DFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
break;
case 14: /* PendSV */
break;
@@ -337,14 +390,14 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
LOG_DEBUG(" ");
if (armv7m->pre_debug_entry)
armv7m->pre_debug_entry(target);
cortex_m3_clear_halt(target);
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
return retval;
@@ -417,10 +470,10 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
/* Read from Debug Halting Control and Status Register */
- retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
{
target->state = TARGET_UNKNOWN;
@@ -430,7 +483,7 @@
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
/* check if still in reset */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
@@ -476,7 +529,7 @@
#if 0
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
- ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
#endif
@@ -530,15 +583,15 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 dcb_dhcsr = 0;
int retval, timeout = 0;
/* Enter debug state on reset, cf. end_reset_event() */
- ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
/* Request a reset */
- ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
+ mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
target->state = TARGET_RESET;
/* registers are now invalid */
@@ -546,10 +599,10 @@
while (timeout < 100)
{
- retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK)
{
- ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
{
LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
@@ -657,7 +710,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
breakpoint_t *breakpoint = NULL;
if (target->state != TARGET_HALTED)
@@ -683,7 +736,7 @@
/* set step and clear halt */
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
@@ -704,7 +757,7 @@
{
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
@@ -717,17 +770,17 @@
}
/* Enable debug requests */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
- ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
+ mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
if (!target->reset_halt)
{
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
- ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
/* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
@@ -736,12 +789,12 @@
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
/* Enter debug state on reset, cf. end_reset_event() */
- ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
+ mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
}
else
{
/* Enter debug state on reset, cf. end_reset_event() */
- ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
}
/* following hack is to handle luminary reset
@@ -789,14 +842,14 @@
else
{
/* this causes the luminary device to reset using the watchdog */
- ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+ mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
{
/* I do not know why this is necessary, but it fixes strange effects
* (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
u32 tmp;
- ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+ mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
}
}
@@ -1179,13 +1232,12 @@
int retval;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
/* read a normal core register */
- retval = ahbap_read_coreregister_u32(swjdp, value, num);
+ retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
if (retval != ERROR_OK)
{
@@ -1197,7 +1249,7 @@
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
{
/* read other registers */
- ahbap_read_coreregister_u32(swjdp, value, 20);
+ cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
switch (num)
{
@@ -1235,8 +1287,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
@@ -1251,7 +1302,7 @@
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
- retval = ahbap_write_coreregister_u32(swjdp, value, num);
+ retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
if (retval != ERROR_OK)
{
LOG_ERROR("JTAG failure %i", retval);
@@ -1264,7 +1315,7 @@
{
/* write other registers */
- ahbap_read_coreregister_u32(swjdp, ®, 20);
+ cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
switch (num)
{
@@ -1285,7 +1336,7 @@
break;
}
- ahbap_write_coreregister_u32(swjdp, reg, 20);
+ cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
LOG_DEBUG("write special reg %i value 0x%x ", num, value);
}
@@ -1301,8 +1352,7 @@
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
@@ -1314,13 +1364,13 @@
switch (size)
{
case 4:
- retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
+ retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
+ retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
+ retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
break;
default:
LOG_ERROR("BUG: we shouldn't get here");
@@ -1334,8 +1384,7 @@
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
@@ -1345,13 +1394,13 @@
switch (size)
{
case 4:
- retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
+ retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
+ retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
+ retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
break;
default:
LOG_ERROR("BUG: we shouldn't get here");
@@ -1386,7 +1435,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
@@ -1451,7 +1500,7 @@
{
u16 dcrdr;
- ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (u8)dcrdr;
*value = (u8)(dcrdr >> 8);
@@ -1462,7 +1511,7 @@
if (dcrdr & (1 << 0))
{
dcrdr = 0;
- ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
}
return ERROR_OK;
@@ -1471,8 +1520,7 @@
int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
{
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u8 data;
u8 ctrl;
u32 i;
@@ -1492,8 +1540,7 @@
if (!target->type->examined)
return ERROR_OK;
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
if (!target->dbg_msg_enabled)
return ERROR_OK;
@@ -1534,10 +1581,10 @@
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
- cortex_m3->swjdp_info.dp_select_value = -1;
- cortex_m3->swjdp_info.ap_csw_value = -1;
- cortex_m3->swjdp_info.ap_tar_value = -1;
- cortex_m3->swjdp_info.jtag_info = &cortex_m3->jtag_info;
+ armv7m->swjdp_info.dp_select_value = -1;
+ armv7m->swjdp_info.ap_csw_value = -1;
+ armv7m->swjdp_info.ap_tar_value = -1;
+ armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
/* initialize arch-specific breakpoint handling */
Modified: trunk/src/target/cortex_m3.h
===================================================================
--- trunk/src/target/cortex_m3.h 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/cortex_m3.h 2009-04-27 08:29:28 UTC (rev 1536)
@@ -29,7 +29,7 @@
#include "register.h"
#include "target.h"
#include "armv7m.h"
-#include "cortex_swjdp.h"
+//#include "arm_adi_v5.h"
extern char* cortex_m3_state_strings[];
@@ -162,7 +162,7 @@
u32 *intsetenable;
armv7m_common_t armv7m;
- swjdp_common_t swjdp_info;
+// swjdp_common_t swjdp_info;
void *arch_info;
} cortex_m3_common_t;
@@ -188,7 +188,7 @@
int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
+//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
#endif /* CORTEX_M3_H */
|
|
From: <ml...@ma...> - 2009-04-27 10:21:38
|
Author: mlu
Date: 2009-04-27 10:21:35 +0200 (Mon, 27 Apr 2009)
New Revision: 1535
Added:
trunk/src/target/arm_adi_v5.c
trunk/src/target/arm_adi_v5.h
Log:
Added arm_adi_v5.c/h, to replace cortex_swjdp.c/h. Better conformance to ARM Debug Interface rev 5 documentation and remoed code specific to the Cortex-M3 targets.
Added: trunk/src/target/arm_adi_v5.c
===================================================================
--- trunk/src/target/arm_adi_v5.c 2009-04-27 05:40:52 UTC (rev 1534)
+++ trunk/src/target/arm_adi_v5.c 2009-04-27 08:21:35 UTC (rev 1535)
@@ -0,0 +1,1121 @@
+/***************************************************************************
+ * Copyright (C) 2006 by Magnus Lundin *
+ * lu...@ml... *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * sp...@sp... *
+ * *
+ * Copyright (C) 2009 by Oyvind Harboe *
+ * oyv...@zy... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+/***************************************************************************
+ * *
+ * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
+ * *
+ * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
+ * *
+ * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
+ * Cortex-M3(tm) TRM, ARM DDI 0337C *
+ * *
+***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "arm_adi_v5.h"
+#include "jtag.h"
+#include "log.h"
+#include "time_support.h"
+#include <stdlib.h>
+
+/*
+ * Transaction Mode:
+ * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+ * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
+ * result checking until swjdp_end_transaction()
+ * This must be done before using or deallocating any return variables.
+ * swjdp->trans_mode == TRANS_MODE_ATOMIC
+ * All reads and writes to the AHB bus are checked for valid completion, and return values
+ * are immediatley available.
+*/
+
+/***************************************************************************
+ * *
+ * DPACC and APACC scanchain access through JTAG-DP *
+ * *
+***************************************************************************/
+
+/* Scan out and in from target ordered u8 buffers */
+int adi_jtag_dp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
+{
+ scan_field_t fields[2];
+ u8 out_addr_buf;
+
+ jtag_add_end_state(TAP_IDLE);
+ arm_jtag_set_instr(jtag_info, instr, NULL);
+
+ fields[0].tap = jtag_info->tap;
+ fields[0].num_bits = 3;
+ buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
+ fields[0].out_value = &out_addr_buf;
+ fields[0].out_mask = NULL;
+ fields[0].in_value = ack;
+ fields[0].in_check_value = NULL;
+ fields[0].in_check_mask = NULL;
+ fields[0].in_handler = NULL;
+ fields[0].in_handler_priv = NULL;
+
+ fields[1].tap = jtag_info->tap;
+ fields[1].num_bits = 32;
+ fields[1].out_value = outvalue;
+ fields[1].out_mask = NULL;
+ fields[1].in_value = invalue;
+ fields[1].in_handler = NULL;
+ fields[1].in_handler_priv = NULL;
+ fields[1].in_check_value = NULL;
+ fields[1].in_check_mask = NULL;
+
+ jtag_add_dr_scan(2, fields, TAP_INVALID);
+
+ return ERROR_OK;
+}
+
+/* Scan out and in from host ordered u32 variables */
+int adi_jtag_dp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
+{
+ scan_field_t fields[2];
+ u8 out_value_buf[4];
+ u8 out_addr_buf;
+
+ jtag_add_end_state(TAP_IDLE);
+ arm_jtag_set_instr(jtag_info, instr, NULL);
+
+ fields[0].tap = jtag_info->tap;
+ fields[0].num_bits = 3;
+ buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
+ fields[0].out_value = &out_addr_buf;
+ fields[0].out_mask = NULL;
+ fields[0].in_value = ack;
+ fields[0].in_check_value = NULL;
+ fields[0].in_check_mask = NULL;
+ fields[0].in_handler = NULL;
+ fields[0].in_handler_priv = NULL;
+
+ fields[1].tap = jtag_info->tap;
+ fields[1].num_bits = 32;
+ buf_set_u32(out_value_buf, 0, 32, outvalue);
+ fields[1].out_value = out_value_buf;
+ fields[1].out_mask = NULL;
+ fields[1].in_value = NULL;
+ if (invalue)
+ {
+ fields[1].in_handler = arm_jtag_buf_to_u32;
+ fields[1].in_handler_priv = invalue;
+ }
+ else
+ {
+ fields[1].in_handler = NULL;
+ fields[1].in_handler_priv = NULL;
+ }
+ fields[1].in_check_value = NULL;
+ fields[1].in_check_mask = NULL;
+
+ jtag_add_dr_scan(2, fields, TAP_INVALID);
+
+ return ERROR_OK;
+}
+
+/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
+int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
+{
+ adi_jtag_dp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
+ if ((RnW == DPAP_READ) && (invalue != NULL))
+ {
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+ }
+
+ /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
+ if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
+ {
+ return swjdp_transaction_endcheck(swjdp);
+ }
+
+ return ERROR_OK;
+}
+
+int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
+{
+ adi_jtag_dp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
+ if ((RnW==DPAP_READ) && (invalue != NULL))
+ {
+ adi_jtag_dp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+ }
+
+ /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
+ if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
+ {
+ return swjdp_transaction_endcheck(swjdp);
+ }
+
+ return ERROR_OK;
+}
+
+int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
+{
+ int retval;
+ u32 ctrlstat;
+
+ /* too expensive to call keep_alive() here */
+
+#if 0
+ /* Danger!!!! BROKEN!!!! */
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
+ R956 introduced the check on return value here and now Michael Schwingen reports
+ that this code no longer works....
+
+ https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
+ */
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ {
+ LOG_ERROR("BUG: Why does this fail the first time????");
+ }
+ /* Why??? second time it works??? */
+#endif
+
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+
+ swjdp->ack = swjdp->ack & 0x7;
+
+ if (swjdp->ack != 2)
+ {
+ long long then=timeval_ms();
+ while (swjdp->ack != 2)
+ {
+ if (swjdp->ack == 1)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+ else
+ {
+ LOG_WARNING("Invalid ACK in SWJDP transaction");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ swjdp->ack = swjdp->ack & 0x7;
+ }
+ } else
+ {
+ /* common code path avoids fn to timeval_ms() */
+ }
+
+ /* Check for STICKYERR and STICKYORUN */
+ if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
+ {
+ LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
+ /* Check power to debug regions */
+ if ((ctrlstat & 0xf0000000) != 0xf0000000)
+ {
+ ahbap_debugport_init(swjdp);
+ }
+ else
+ {
+ u32 mem_ap_csw;
+
+ /* Print information about last AHBAP access */
+ LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+ if (ctrlstat & SSTICKYORUN)
+ LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
+
+ if (ctrlstat & SSTICKYERR)
+ LOG_ERROR("SWJ-DP STICKY ERROR");
+
+ /* Clear Sticky Error Bits */
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+
+ LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
+
+ dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ LOG_ERROR("Read MEM_AP_CSW 0x%x", mem_ap_csw);
+
+ }
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+/***************************************************************************
+ * *
+ * DP and MEM-AP register access through APACC and DPACC *
+ * *
+***************************************************************************/
+
+int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
+{
+ return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
+}
+
+int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
+{
+ return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
+}
+
+int dap_ap_select(swjdp_common_t *swjdp,u8 apsel)
+{
+ u32 select;
+ select = (apsel<<24) & 0xFF000000;
+
+ if (select != swjdp->apsel)
+ {
+ swjdp->apsel = select;
+ /* Switchin AP invalidates cached values */
+ swjdp->dp_select_value = -1;
+ swjdp->ap_csw_value = -1;
+ swjdp->ap_tar_value = -1;
+ }
+
+ return ERROR_OK;
+}
+
+int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
+{
+ u32 select;
+ select = (ap_reg & 0x000000F0);
+
+ if (select != swjdp->dp_select_value)
+ {
+ dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
+ swjdp->dp_select_value = select;
+ }
+
+ return ERROR_OK;
+}
+
+int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
+{
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
+
+ return ERROR_OK;
+}
+
+int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
+{
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
+
+ return ERROR_OK;
+}
+int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
+{
+ u8 out_value_buf[4];
+
+ buf_set_u32(out_value_buf, 0, 32, value);
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
+
+ return ERROR_OK;
+}
+
+int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
+{
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
+
+ return ERROR_OK;
+}
+
+/***************************************************************************
+ * *
+ * AHB-AP access to memory and system registers on AHB bus *
+ * *
+***************************************************************************/
+
+int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
+{
+ csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
+ if (csw != swjdp->ap_csw_value)
+ {
+ /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
+ dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
+ swjdp->ap_csw_value = csw;
+ }
+ if (tar != swjdp->ap_tar_value)
+ {
+ /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
+ dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
+ swjdp->ap_tar_value = tar;
+ }
+ if (csw & CSW_ADDRINC_MASK)
+ {
+ /* Do not cache TAR value when autoincrementing */
+ swjdp->ap_tar_value = -1;
+ }
+ return ERROR_OK;
+}
+
+/*****************************************************************************
+* *
+* mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
+* *
+* Read a u32 value from memory or system register *
+* Functionally equivalent to target_read_u32(target, address, u32 *value), *
+* but with less overhead *
+*****************************************************************************/
+int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
+{
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+ dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
+
+ return ERROR_OK;
+}
+
+int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
+{
+ mem_ap_read_u32(swjdp, address, value);
+
+ return swjdp_transaction_endcheck(swjdp);
+}
+
+/*****************************************************************************
+* *
+* mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
+* *
+* Write a u32 value to memory or memory mapped register *
+* *
+*****************************************************************************/
+int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value)
+{
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
+
+ return ERROR_OK;
+}
+
+int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
+{
+ mem_ap_write_u32(swjdp, address, value);
+
+ return swjdp_transaction_endcheck(swjdp);
+}
+
+/*****************************************************************************
+* *
+* mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
+* *
+* Write a buffer in target order (little endian) *
+* *
+*****************************************************************************/
+int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
+ u32 adr = address;
+ u8* pBuffer = buffer;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ count >>= 2;
+ wcount = count;
+
+ /* if we have an unaligned access - reorder data */
+ if (adr & 0x3u)
+ {
+ for (writecount = 0; writecount < count; writecount++)
+ {
+ int i;
+ outvalue = *((u32*)pBuffer);
+
+ for (i = 0; i < 4; i++ )
+ {
+ *((u8*)pBuffer + (adr & 0x3)) = outvalue;
+ outvalue >>= 8;
+ adr++;
+ }
+ pBuffer += 4;
+ }
+ }
+
+ while (wcount > 0)
+ {
+ /* Adjust to write blocks within 4K aligned boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 2;
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+
+ for (writecount = 0; writecount < blocksize; writecount++)
+ {
+ dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
+ }
+
+ if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ {
+ wcount = wcount - blocksize;
+ address = address + 4 * blocksize;
+ buffer = buffer + 4 * blocksize;
+ }
+ else
+ {
+ errorcount++;
+ }
+
+ if (errorcount > 1)
+ {
+ LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, writecount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count >> 1;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 1;
+
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ writecount = blocksize;
+
+ do
+ {
+ nbytes = MIN((writecount << 1), 4);
+
+ if (nbytes < 4 )
+ {
+ if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ address += nbytes >> 1;
+ }
+ else
+ {
+ outvalue = *((u32*)buffer);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer + (address & 0x3)) = outvalue;
+ outvalue >>= 8;
+ address++;
+ }
+
+ outvalue = *((u32*)buffer);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ buffer += nbytes >> 1;
+ writecount -= nbytes >> 1;
+
+ } while (writecount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ outvalue = *((u16*)buffer) << 8 * (address & 0x3);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ count -= 2;
+ address += 2;
+ buffer += 2;
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, writecount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address));
+
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ writecount = blocksize;
+
+ do
+ {
+ nbytes = MIN(writecount, 4);
+
+ if (nbytes < 4 )
+ {
+ if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ address += nbytes;
+ }
+ else
+ {
+ outvalue = *((u32*)buffer);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer + (address & 0x3)) = outvalue;
+ outvalue >>= 8;
+ address++;
+ }
+
+ outvalue = *((u32*)buffer);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ buffer += nbytes;
+ writecount -= nbytes;
+
+ } while (writecount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ outvalue = *((u8*)buffer) << 8 * (address & 0x3);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ count--;
+ address++;
+ buffer++;
+ }
+
+ return retval;
+}
+
+/*********************************************************************************
+* *
+* mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
+* *
+* Read block fast in target order (little endian) into a buffer *
+* *
+**********************************************************************************/
+int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
+ u32 adr = address;
+ u8* pBuffer = buffer;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ count >>= 2;
+ wcount = count;
+
+ while (wcount > 0)
+ {
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 2;
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+
+ /* Scan out first read */
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
+ for (readcount = 0; readcount < blocksize - 1; readcount++)
+ {
+ /* Scan out read instruction and scan in previous value */
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
+ }
+
+ /* Scan in last value */
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
+ if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ {
+ wcount = wcount - blocksize;
+ address += 4 * blocksize;
+ buffer += 4 * blocksize;
+ }
+ else
+ {
+ errorcount++;
+ }
+
+ if (errorcount > 1)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ /* if we have an unaligned access - reorder data */
+ if (adr & 0x3u)
+ {
+ for (readcount = 0; readcount < count; readcount++)
+ {
+ int i;
+ u32 data = *((u32*)pBuffer);
+
+ for (i = 0; i < 4; i++ )
+ {
+ *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
+ pBuffer++;
+ adr++;
+ }
+ }
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, readcount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count >> 1;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 1;
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+ readcount = blocksize;
+
+ do
+ {
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ nbytes = MIN((readcount << 1), 4);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ buffer++;
+ address++;
+ }
+
+ readcount -= (nbytes >> 1);
+ } while (readcount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue, i;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ if (address & 0x1)
+ {
+ for (i = 0; i < 2; i++ )
+ {
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ buffer++;
+ address++;
+ }
+ }
+ else
+ {
+ *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
+ address += 2;
+ buffer += 2;
+ }
+ count -= 2;
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, readcount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address));
+
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ readcount = blocksize;
+
+ do
+ {
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ nbytes = MIN(readcount, 4);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ buffer++;
+ address++;
+ }
+
+ readcount -= nbytes;
+ } while (readcount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ count--;
+ address++;
+ buffer++;
+ }
+
+ return retval;
+}
+
+int ahbap_debugport_init(swjdp_common_t *swjdp)
+{
+ u32 idreg, romaddr, dummy;
+ u32 ctrlstat;
+ int cnt = 0;
+ int retval;
+
+ LOG_DEBUG(" ");
+
+ swjdp->apsel = 0;
+ swjdp->ap_csw_value = -1;
+ swjdp->ap_tar_value = -1;
+ swjdp->trans_mode = TRANS_MODE_ATOMIC;
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+ dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+
+ swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+
+ dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
+ dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+
+ /* Check that we have debug power domains activated */
+ while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
+ {
+ LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
+ dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ alive_sleep(10);
+ }
+
+ while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
+ {
+ LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
+ dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ alive_sleep(10);
+ }
+
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+ /* With debug power on we can activate OVERRUN checking */
+ swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+ dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+
+ dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
+ dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
+
+ LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
+
+ return ERROR_OK;
+}
+
+
+char * class_description[16] ={
+ "Reserved",
+ "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
+ "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
+
+int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
+{
+
+ u32 dbgbase,apid;
+ int romtable_present = 0;
+ u8 mem_ap;
+ u32 apselold;
+
+ apselold = swjdp->apsel;
+ dap_ap_select(swjdp, apsel);
+ dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase);
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ swjdp_transaction_endcheck(swjdp);
+ /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
+ mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
+ command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
+ if (apid)
+ {
+ switch (apid&0x0F)
+ {
+ case 0:
+ command_print(cmd_ctx, "\tType is jtag-ap");
+ break;
+ case 1:
+ command_print(cmd_ctx, "\tType is mem-ap AHB");
+ break;
+ case 2:
+ command_print(cmd_ctx, "\tType is mem-ap APB");
+ break;
+ default:
+ command_print(cmd_ctx, "\tUnknown AP-type");
+ break;
+ }
+ command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
+ }
+ else
+ {
+ command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
+ }
+
+ romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF));
+ if (romtable_present)
+ {
+ u32 cid0,cid1,cid2,cid3,memtype,romentry;
+ u16 entry_offset;
+ /* bit 16 of apid indicates a memory access port */
+ if (dbgbase&0x02)
+ {
+ command_print(cmd_ctx, "\tValid ROM table present");
+ }
+ else
+ {
+ command_print(cmd_ctx, "\tROM table in legacy format" );
+ }
+ /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
+ swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
+ if (memtype&0x01)
+ {
+ command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
+ }
+ else
+ {
+ command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
+ }
+
+ /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
+ entry_offset = 0;
+ do
+ {
+ mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
+ command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
+ if (romentry&0x01)
+ {
+ u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
+ u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
+ component_start = component_base - 0x1000*(c_pid4>>4);
+ command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
+ command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
+ command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
+ command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
+ /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
+ }
+ else
+ {
+ if (romentry)
+ command_print(cmd_ctx, "\t\tComponent not present");
+ else
+ command_print(cmd_ctx, "\t\tEnd of ROM table");
+ }
+ entry_offset += 4;
+ } while (romentry>0);
+ }
+ else
+ {
+ command_print(cmd_ctx, "\tNo ROM table present");
+ }
+ dap_ap_select(swjdp, apselold);
+
+ return ERROR_OK;
+}
+
Added: trunk/src/target/arm_adi_v5.h
===================================================================
--- trunk/src/target/arm_adi_v5.h 2009-04-27 05:40:52 UTC (rev 1534)
+++ trunk/src/target/arm_adi_v5.h 2009-04-27 08:21:35 UTC (rev 1535)
@@ -0,0 +1,142 @@
+/***************************************************************************
+ * Copyright (C) 2006 by Magnus Lundin *
+ * lu...@ml... *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * sp...@sp... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef ARM_ADI_V5_H
+#define ARM_ADI_V5_H
+
+#include "target.h"
+#include "register.h"
+#include "arm_jtag.h"
+
+#define SWJDP_IR_DPACC 0xA
+#define SWJDP_IR_APACC 0xB
+
+#define DPAP_WRITE 0
+#define DPAP_READ 1
+#define DP_ZERO 0
+#define DP_CTRL_STAT 0x4
+#define DP_SELECT 0x8
+#define DP_RDBUFF 0xC
+
+#define CORUNDETECT (1<<0)
+#define SSTICKYORUN (1<<1)
+#define SSTICKYERR (1<<5)
+#define CDBGRSTREQ (1<<26)
+#define CDBGRSTACK (1<<27)
+#define CDBGPWRUPREQ (1<<28)
+#define CDBGPWRUPACK (1<<29)
+#define CSYSPWRUPREQ (1<<30)
+#define CSYSPWRUPACK (1<<31)
+
+#define AP_REG_CSW 0x00
+#define AP_REG_TAR 0x04
+#define AP_REG_DRW 0x0C
+#define AP_REG_BD0 0x10
+#define AP_REG_BD1 0x14
+#define AP_REG_BD2 0x18
+#define AP_REG_BD3 0x1C
+#define AP_REG_DBGROMA 0xF8
+#define AP_REG_IDR 0xFC
+
+#define CSW_8BIT 0
+#define CSW_16BIT 1
+#define CSW_32BIT 2
+
+#define CSW_ADDRINC_MASK (3<<4)
+#define CSW_ADDRINC_OFF 0
+#define CSW_ADDRINC_SINGLE (1<<4)
+#define CSW_ADDRINC_PACKED (2<<4)
+#define CSW_HPROT (1<<25)
+#define CSW_MASTER_DEBUG (1<<29)
+#define CSW_DBGSWENABLE (1<<31)
+
+/* transaction mode */
+#define TRANS_MODE_NONE 0
+/* Transaction waits for previous to complete */
+#define TRANS_MODE_ATOMIC 1
+/* Freerunning transactions with delays and overrun checking */
+#define TRANS_MODE_COMPOSITE 2
+
+typedef struct swjdp_reg_s
+{
+ int addr;
+ arm_jtag_t *jtag_info;
+} swjdp_reg_t;
+
+typedef struct swjdp_common_s
+{
+ arm_jtag_t *jtag_info;
+ /* Control config */
+ u32 dp_ctrl_stat;
+ /* Support for several AP's in one DAP */
+ u32 apsel;
+ /* Register select cache */
+ u32 dp_select_value;
+ u32 ap_csw_value;
+ u32 ap_tar_value;
+ /* information about current pending SWjDP-AHBAP transaction */
+ u8 trans_mode;
+ u8 trans_rw;
+ u8 ack;
+} swjdp_common_t;
+
+/* Internal functions used in the module, partial transactions, use with caution */
+extern int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
+/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
+extern int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
+/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr); */
+extern int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar);
+extern int dap_ap_select(swjdp_common_t *swjdp,u8 apsel);
+
+extern int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
+extern int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value);
+extern int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
+extern int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value);
+
+/* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
+extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
+
+/* MEM-AP memory mapped bus single u32 register transfers, without endcheck */
+extern int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
+extern int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value);
+
+/* MEM-AP memory mapped bus transfers, single registers, complete transactions */
+extern int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
+extern int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
+
+/* MEM-AP memory mapped bus block transfers */
+extern int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+
+/* Initialisation of the debug system, power domains and registers */
+extern int ahbap_debugport_init(swjdp_common_t *swjdp);
+
+extern int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel);
+/* Commands for user dap access */
+extern int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+extern int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+#endif
|
|
From: <oh...@ma...> - 2009-04-27 07:40:57
|
Author: oharboe
Date: 2009-04-27 07:40:52 +0200 (Mon, 27 Apr 2009)
New Revision: 1534
Modified:
trunk/src/flash/mflash.c
Log:
Philippe Vachon <phi...@co...> 64 bit host fixes
Modified: trunk/src/flash/mflash.c
===================================================================
--- trunk/src/flash/mflash.c 2009-04-27 05:30:15 UTC (rev 1533)
+++ trunk/src/flash/mflash.c 2009-04-27 05:40:52 UTC (rev 1534)
@@ -473,14 +473,16 @@
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
- LOG_DEBUG("sect num : %u buff : 0x%8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : 0x%0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_read_sects(buff_ptr, sect_num, 256);
sect_num += 256;
buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
}
if (residue) {
- LOG_DEBUG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : %0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_read_sects(buff_ptr, sect_num, residue);
}
@@ -542,14 +544,16 @@
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
- LOG_DEBUG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : %0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_write_sects(buff_ptr, sect_num, 256);
sect_num += 256;
buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
}
if (residue) {
- LOG_DEBUG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : %0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_write_sects(buff_ptr, sect_num, residue);
}
|
|
From: <oh...@ma...> - 2009-04-27 07:30:19
|
Author: oharboe
Date: 2009-04-27 07:30:15 +0200 (Mon, 27 Apr 2009)
New Revision: 1533
Modified:
trunk/configure.in
Log:
Zach Welch <zw...@su...> add -Wcast-align and -Wbad-function-cast
Modified: trunk/configure.in
===================================================================
--- trunk/configure.in 2009-04-27 05:29:30 UTC (rev 1532)
+++ trunk/configure.in 2009-04-27 05:30:15 UTC (rev 1533)
@@ -776,6 +776,8 @@
GCC_WARNINGS="-Wall -Wstrict-prototypes -Wformat-security"
if test "${gcc_wextra}" = yes; then
GCC_WARNINGS="${GCC_WARNINGS} -Wextra -Wno-unused-parameter"
+ GCC_WARNINGS="${GCC_WARNINGS} -Wbad-function-cast"
+ GCC_WARNINGS="${GCC_WARNINGS} -Wcast-align"
fi
if test "${gcc_werror}" = yes; then
GCC_WARNINGS="${GCC_WARNINGS} -Werror"
|
|
From: <oh...@ma...> - 2009-04-27 07:29:36
|
Author: oharboe Date: 2009-04-27 07:29:30 +0200 (Mon, 27 Apr 2009) New Revision: 1532 Modified: trunk/src/helper/jim.c trunk/src/target/oocd_trace.c Log: Zach Welch <zw...@su...> wrap _GNU_SOURCE defines Modified: trunk/src/helper/jim.c =================================================================== --- trunk/src/helper/jim.c 2009-04-26 20:05:08 UTC (rev 1531) +++ trunk/src/helper/jim.c 2009-04-27 05:29:30 UTC (rev 1532) @@ -49,7 +49,9 @@ #define JIM_DYNLIB /* Dynamic library support for UNIX and WIN32 */ #endif /* JIM_ANSIC */ +#ifndef _GNU_SOURCE #define _GNU_SOURCE /* for vasprintf() */ +#endif #include <stdio.h> #include <stdlib.h> #include <string.h> Modified: trunk/src/target/oocd_trace.c =================================================================== --- trunk/src/target/oocd_trace.c 2009-04-26 20:05:08 UTC (rev 1531) +++ trunk/src/target/oocd_trace.c 2009-04-27 05:29:30 UTC (rev 1532) @@ -21,7 +21,9 @@ #include "config.h" #endif +#ifndef _GNU_SOURCE #define _GNU_SOURCE +#endif #include <string.h> #include <errno.h> |
|
From: <oh...@ma...> - 2009-04-26 22:05:10
|
Author: oharboe Date: 2009-04-26 22:05:08 +0200 (Sun, 26 Apr 2009) New Revision: 1531 Modified: trunk/src/target/board/ti_beagleboard.cfg trunk/src/target/target/omap3530.cfg Log: Zach Welch <zw...@su...> fix typo Modified: trunk/src/target/board/ti_beagleboard.cfg =================================================================== --- trunk/src/target/board/ti_beagleboard.cfg 2009-04-26 20:03:41 UTC (rev 1530) +++ trunk/src/target/board/ti_beagleboard.cfg 2009-04-26 20:05:08 UTC (rev 1531) @@ -7,5 +7,5 @@ runtest 10 jtag_reset 0 0 -endstate IDLE +endstate RUN/IDLE Modified: trunk/src/target/target/omap3530.cfg =================================================================== --- trunk/src/target/target/omap3530.cfg 2009-04-26 20:03:41 UTC (rev 1530) +++ trunk/src/target/target/omap3530.cfg 2009-04-26 20:05:08 UTC (rev 1531) @@ -32,8 +32,8 @@ irscan omap3.jrc 7 -endstate IRPAUSE drscan omap3.jrc 8 0x89 -endstate DRPAUSE irscan omap3.jrc 2 -endstate IRPAUSE - drscan omap3.jrc 32 0xa3002108 -endstate IDLE - irscan omap3.jrc 0x3F -endstate IDLE + drscan omap3.jrc 32 0xa3002108 -endstate RUN/IDLE + irscan omap3.jrc 0x3F -endstate RUN/IDLE runtest 10 puts "Cortex-A8 @ OMAP3 enabled" } |
|
From: <oh...@ma...> - 2009-04-26 22:03:44
|
Author: oharboe
Date: 2009-04-26 22:03:41 +0200 (Sun, 26 Apr 2009)
New Revision: 1530
Added:
trunk/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg
Log:
R.Doss <do...@gm...> AT91SAM9260
Added: trunk/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg
===================================================================
--- trunk/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg 2009-04-26 20:02:15 UTC (rev 1529)
+++ trunk/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg 2009-04-26 20:03:41 UTC (rev 1530)
@@ -0,0 +1,127 @@
+
+
+
+jtag_khz 4
+
+
+######################################
+# Target: Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst
+
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+$_TARGETNAME invoke-event halted
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+
+scan_chain
+$_TARGETNAME configure -event reset-deassert-post {at91sam_init}
+
+
+# Flash configuration
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+
+
+proc at91sam_init { } {
+
+ # at reset chip runs at 32khz
+ jtag_khz 8
+ halt
+ mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
+ mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+
+ mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
+ sleep 20 # wait 20 ms
+ mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
+ sleep 10 # wait 10 ms
+ mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
+ sleep 20 # wait 20 ms
+ mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
+ sleep 10 # wait 10 ms
+ mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
+ sleep 10 # wait 10 ms
+
+ # Now run at anything fast... ie: 10mhz!
+ jtag_khz 10000 # Increase JTAG Speed to 6 MHz
+ arm7_9 dcc_downloads enable # Enable faster DCC downloads
+
+ mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+ mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
+ mww 0xffffec08 0x00160016 # SMC_CYCLE0
+ mww 0xffffec0c 0x00161003 # SMC_MODE0
+
+ flash probe 0 # Identify flash bank 0
+
+ mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
+
+ mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+
+ mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+ #mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
+
+ mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+ mww 0x20000000 0
+ mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0x20000000 0
+ mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
+}
+
+
+
|
|
From: <oh...@ma...> - 2009-04-26 22:02:18
|
Author: oharboe
Date: 2009-04-26 22:02:15 +0200 (Sun, 26 Apr 2009)
New Revision: 1529
Modified:
trunk/src/jtag/jtag.h
Log:
Zach Welch <zw...@su...> add TAP_SCAN_BYTES macro
Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h 2009-04-25 02:53:07 UTC (rev 1528)
+++ trunk/src/jtag/jtag.h 2009-04-26 20:02:15 UTC (rev 1529)
@@ -237,7 +237,7 @@
typedef int (*in_handler_t)(u8* in_value, void* priv, struct scan_field_s* field);
/// @brief calculates number of bytes required to hold @a n TAP scan bits
-#define TAP_SCAN_BYTES(n) (((n) / 8) + !!((n) % 8))
+#define TAP_SCAN_BYTES(n) CEIL(n, 8)
typedef struct scan_field_s
{
|
|
From: <ml...@ma...> - 2009-04-25 04:53:21
|
Author: mlu
Date: 2009-04-25 04:53:07 +0200 (Sat, 25 Apr 2009)
New Revision: 1528
Modified:
trunk/src/jtag/ft2232.c
Log:
Corrected statement order
Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c 2009-04-25 00:58:49 UTC (rev 1527)
+++ trunk/src/jtag/ft2232.c 2009-04-25 02:53:07 UTC (rev 1528)
@@ -1590,13 +1590,13 @@
if (ft2232_execute_command(cmd) != ERROR_OK)
retval = ERROR_JTAG_QUEUE_FAILED;
/* Start reading input before FT2232 TX buffer fills up */
- if (ft2232_expect_read > 280)
+ cmd = cmd->next;
+ if (ft2232_expect_read > 256)
{
if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
retval = ERROR_JTAG_QUEUE_FAILED;
first_unsent = cmd;
}
- cmd = cmd->next;
}
if (require_send > 0)
|
|
From: <ml...@ma...> - 2009-04-25 02:58:57
|
Author: mlu
Date: 2009-04-25 02:58:49 +0200 (Sat, 25 Apr 2009)
New Revision: 1527
Modified:
trunk/src/jtag/ft2232.c
Log:
Fix ft2232 TX buffer overflow
Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c 2009-04-25 00:54:21 UTC (rev 1526)
+++ trunk/src/jtag/ft2232.c 2009-04-25 00:58:49 UTC (rev 1527)
@@ -1589,6 +1589,13 @@
{
if (ft2232_execute_command(cmd) != ERROR_OK)
retval = ERROR_JTAG_QUEUE_FAILED;
+ /* Start reading input before FT2232 TX buffer fills up */
+ if (ft2232_expect_read > 280)
+ {
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
+ first_unsent = cmd;
+ }
cmd = cmd->next;
}
|
|
From: <ml...@ma...> - 2009-04-25 02:54:36
|
Author: mlu
Date: 2009-04-25 02:54:21 +0200 (Sat, 25 Apr 2009)
New Revision: 1526
Modified:
trunk/src/jtag/ft2232.c
Log:
Break ft2232_execute_quie into smaller functions, follows restructure of jlink.c
Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c 2009-04-24 18:10:04 UTC (rev 1525)
+++ trunk/src/jtag/ft2232.c 2009-04-25 00:54:21 UTC (rev 1526)
@@ -423,8 +423,8 @@
int scan_size;
enum scan_type type;
int retval;
- u32 bytes_written;
- u32 bytes_read;
+ u32 bytes_written=0;
+ u32 bytes_read=0;
#ifdef _DEBUG_USB_IO_
struct timeval start, inter, inter2, end;
@@ -1267,246 +1267,328 @@
LOG_DEBUG("trst: %i, srst: %i, high_output: 0x%2.2x, high_direction: 0x%2.2x", trst, srst, high_output, high_direction);
}
-static int ft2232_execute_queue()
+static int ft2232_execute_end_state(jtag_command_t *cmd)
{
- jtag_command_t* cmd = jtag_command_queue; /* currently processed command */
- u8* buffer;
- int scan_size; /* size of IR or DR scan */
- enum scan_type type;
- int i;
- int predicted_size = 0;
- int retval;
+ int retval;
+ retval = ERROR_OK;
- first_unsent = cmd; /* next command that has to be sent */
- require_send = 0;
+ DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
- /* return ERROR_OK, unless ft2232_send_and_recv reports a failed check
- * that wasn't handled by a caller-provided error handler
- */
- retval = ERROR_OK;
+ if (cmd->cmd.end_state->end_state != TAP_INVALID)
+ ft2232_end_state(cmd->cmd.end_state->end_state);
- ft2232_buffer_size = 0;
- ft2232_expect_read = 0;
+ return retval;
+}
- /* blink, if the current layout has that feature */
- if (layout->blink)
- layout->blink();
- while (cmd)
+static int ft2232_execute_runtest(jtag_command_t *cmd)
+{
+ int retval;
+ int i;
+ int predicted_size = 0;
+ retval = ERROR_OK;
+
+ DEBUG_JTAG_IO("runtest %i cycles, end in %i",
+ cmd->cmd.runtest->num_cycles,
+ cmd->cmd.runtest->end_state);
+ /* only send the maximum buffer size that FT2232C can handle */
+ predicted_size = 0;
+ if (tap_get_state() != TAP_IDLE)
+ predicted_size += 3;
+ predicted_size += 3 * CEIL(cmd->cmd.runtest->num_cycles, 7);
+ if ( (cmd->cmd.runtest->end_state != TAP_INVALID) && (cmd->cmd.runtest->end_state != TAP_IDLE) )
+ predicted_size += 3;
+ if ( (cmd->cmd.runtest->end_state == TAP_INVALID) && (tap_get_end_state() != TAP_IDLE) )
+ predicted_size += 3;
+ if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
{
- switch (cmd->type)
- {
- case JTAG_END_STATE:
- if (cmd->cmd.end_state->end_state != TAP_INVALID)
- ft2232_end_state(cmd->cmd.end_state->end_state);
- break;
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
+ require_send = 0;
+ first_unsent = cmd;
+ }
+ if (tap_get_state() != TAP_IDLE)
+ {
+ /* command "Clock Data to TMS/CS Pin (no Read)" */
+ BUFFER_ADD = 0x4b;
+ BUFFER_ADD = 0x6; /* scan 7 bits */
- case JTAG_RESET:
- /* only send the maximum buffer size that FT2232C can handle */
- predicted_size = 3;
- if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
- {
- if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
- retval = ERROR_JTAG_QUEUE_FAILED;
- require_send = 0;
- first_unsent = cmd;
- }
+ /* TMS data bits */
+ BUFFER_ADD = tap_get_tms_path(tap_get_state(), TAP_IDLE);
+ tap_set_state(TAP_IDLE);
+ require_send = 1;
+ }
+ i = cmd->cmd.runtest->num_cycles;
+ while (i > 0)
+ {
+ /* command "Clock Data to TMS/CS Pin (no Read)" */
+ BUFFER_ADD = 0x4b;
- if ( (cmd->cmd.reset->trst == 1) || ( cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST) ) )
- {
- tap_set_state(TAP_RESET);
- }
- layout->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
- require_send = 1;
+ /* scan 7 bits */
+ BUFFER_ADD = (i > 7) ? 6 : (i - 1);
+ /* TMS data bits */
+ BUFFER_ADD = 0x0;
+ tap_set_state(TAP_IDLE);
+ i -= (i > 7) ? 7 : i;
+ /* LOG_DEBUG("added TMS scan (no read)"); */
+ }
+
+ if (cmd->cmd.runtest->end_state != TAP_INVALID)
+ ft2232_end_state(cmd->cmd.runtest->end_state);
+
+ if ( tap_get_state() != tap_get_end_state() )
+ {
+ /* command "Clock Data to TMS/CS Pin (no Read)" */
+ BUFFER_ADD = 0x4b;
+ /* scan 7 bit */
+ BUFFER_ADD = 0x6;
+ /* TMS data bits */
+ BUFFER_ADD = tap_get_tms_path( tap_get_state(), tap_get_end_state() );
+ tap_set_state( tap_get_end_state() );
+ /* LOG_DEBUG("added TMS scan (no read)"); */
+ }
+ require_send = 1;
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG("trst: %i, srst: %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
+ LOG_DEBUG( "runtest: %i, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name( tap_get_end_state() ) );
#endif
- break;
- case JTAG_RUNTEST:
- /* only send the maximum buffer size that FT2232C can handle */
- predicted_size = 0;
- if (tap_get_state() != TAP_IDLE)
- predicted_size += 3;
- predicted_size += 3 * CEIL(cmd->cmd.runtest->num_cycles, 7);
- if ( (cmd->cmd.runtest->end_state != TAP_INVALID) && (cmd->cmd.runtest->end_state != TAP_IDLE) )
- predicted_size += 3;
- if ( (cmd->cmd.runtest->end_state == TAP_INVALID) && (tap_get_end_state() != TAP_IDLE) )
- predicted_size += 3;
- if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
- {
- if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
- retval = ERROR_JTAG_QUEUE_FAILED;
- require_send = 0;
- first_unsent = cmd;
- }
- if (tap_get_state() != TAP_IDLE)
- {
- /* command "Clock Data to TMS/CS Pin (no Read)" */
- BUFFER_ADD = 0x4b;
- BUFFER_ADD = 0x6; /* scan 7 bits */
+ return retval;
+}
- /* TMS data bits */
- BUFFER_ADD = tap_get_tms_path(tap_get_state(), TAP_IDLE);
- tap_set_state(TAP_IDLE);
- require_send = 1;
- }
- i = cmd->cmd.runtest->num_cycles;
- while (i > 0)
- {
- /* command "Clock Data to TMS/CS Pin (no Read)" */
- BUFFER_ADD = 0x4b;
+static int ft2232_execute_statemove(jtag_command_t *cmd)
+{
+ int retval;
+ int predicted_size = 0;
+ retval = ERROR_OK;
- /* scan 7 bits */
- BUFFER_ADD = (i > 7) ? 6 : (i - 1);
+ DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
- /* TMS data bits */
- BUFFER_ADD = 0x0;
- tap_set_state(TAP_IDLE);
- i -= (i > 7) ? 7 : i;
- /* LOG_DEBUG("added TMS scan (no read)"); */
- }
+ /* only send the maximum buffer size that FT2232C can handle */
+ predicted_size = 3;
+ if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
+ {
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
+ require_send = 0;
+ first_unsent = cmd;
+ }
+ if (cmd->cmd.statemove->end_state != TAP_INVALID)
+ ft2232_end_state(cmd->cmd.statemove->end_state);
- if (cmd->cmd.runtest->end_state != TAP_INVALID)
- ft2232_end_state(cmd->cmd.runtest->end_state);
+ /* command "Clock Data to TMS/CS Pin (no Read)" */
+ BUFFER_ADD = 0x4b;
- if ( tap_get_state() != tap_get_end_state() )
- {
- /* command "Clock Data to TMS/CS Pin (no Read)" */
- BUFFER_ADD = 0x4b;
- /* scan 7 bit */
- BUFFER_ADD = 0x6;
- /* TMS data bits */
- BUFFER_ADD = tap_get_tms_path( tap_get_state(), tap_get_end_state() );
- tap_set_state( tap_get_end_state() );
- /* LOG_DEBUG("added TMS scan (no read)"); */
- }
- require_send = 1;
+ BUFFER_ADD = 0x6; /* scan 7 bits */
+
+ /* TMS data bits */
+ BUFFER_ADD = tap_get_tms_path( tap_get_state(), tap_get_end_state() );
+ /* LOG_DEBUG("added TMS scan (no read)"); */
+ tap_set_state( tap_get_end_state() );
+ require_send = 1;
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG( "runtest: %i, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name( tap_get_end_state() ) );
+ LOG_DEBUG( "statemove: %s", tap_state_name( tap_get_end_state() ) );
#endif
- break;
+
+ return retval;
+}
- case JTAG_STATEMOVE:
- /* only send the maximum buffer size that FT2232C can handle */
- predicted_size = 3;
- if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
- {
- if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
- retval = ERROR_JTAG_QUEUE_FAILED;
- require_send = 0;
- first_unsent = cmd;
- }
- if (cmd->cmd.statemove->end_state != TAP_INVALID)
- ft2232_end_state(cmd->cmd.statemove->end_state);
+static int ft2232_execute_pathmove(jtag_command_t *cmd)
+{
+ int retval;
+ int predicted_size = 0;
+ retval = ERROR_OK;
- /* command "Clock Data to TMS/CS Pin (no Read)" */
- BUFFER_ADD = 0x4b;
-
- BUFFER_ADD = 0x6; /* scan 7 bits */
-
- /* TMS data bits */
- BUFFER_ADD = tap_get_tms_path( tap_get_state(), tap_get_end_state() );
- /* LOG_DEBUG("added TMS scan (no read)"); */
- tap_set_state( tap_get_end_state() );
- require_send = 1;
+ DEBUG_JTAG_IO("pathmove: %i states, end in %i",
+ cmd->cmd.pathmove->num_states,
+ cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]);
+ /* only send the maximum buffer size that FT2232C can handle */
+ predicted_size = 3 * CEIL(cmd->cmd.pathmove->num_states, 7);
+ if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
+ {
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
+ require_send = 0;
+ first_unsent = cmd;
+ }
+ ft2232_add_pathmove(cmd->cmd.pathmove);
+ require_send = 1;
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG( "statemove: %s", tap_state_name( tap_get_end_state() ) );
+ LOG_DEBUG( "pathmove: %i states, end in %s", cmd->cmd.pathmove->num_states,
+ tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]) );
#endif
- break;
+ return retval;
+}
- case JTAG_PATHMOVE:
- /* only send the maximum buffer size that FT2232C can handle */
- predicted_size = 3 * CEIL(cmd->cmd.pathmove->num_states, 7);
- if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
- {
- if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
- retval = ERROR_JTAG_QUEUE_FAILED;
- require_send = 0;
- first_unsent = cmd;
- }
- ft2232_add_pathmove(cmd->cmd.pathmove);
- require_send = 1;
+static int ft2232_execute_scan(jtag_command_t *cmd)
+{
+ int retval;
+ u8* buffer;
+ int scan_size; /* size of IR or DR scan */
+ enum scan_type type;
+ int predicted_size = 0;
+ retval = ERROR_OK;
+
+ scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
+ type = jtag_scan_type(cmd->cmd.scan);
+ predicted_size = ft2232_predict_scan_out(scan_size, type);
+ if ( (predicted_size + 1) > FT2232_BUFFER_SIZE )
+ {
+ LOG_DEBUG("oversized ft2232 scan (predicted_size > FT2232_BUFFER_SIZE)");
+ /* unsent commands before this */
+ if (first_unsent != cmd)
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
+
+ /* current command */
+ if (cmd->cmd.scan->end_state != TAP_INVALID)
+ ft2232_end_state(cmd->cmd.scan->end_state);
+ ft2232_large_scan(cmd->cmd.scan, type, buffer, scan_size);
+ require_send = 0;
+ first_unsent = cmd->next;
+ if (buffer)
+ free(buffer);
+ return retval;
+ }
+ else if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
+ {
+ LOG_DEBUG("ft2232 buffer size reached, sending queued commands (first_unsent: %p, cmd: %p)",
+ first_unsent,
+ cmd);
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
+ require_send = 0;
+ first_unsent = cmd;
+ }
+ ft2232_expect_read += ft2232_predict_scan_in(scan_size, type);
+ /* LOG_DEBUG("new read size: %i", ft2232_expect_read); */
+ if (cmd->cmd.scan->end_state != TAP_INVALID)
+ ft2232_end_state(cmd->cmd.scan->end_state);
+ ft2232_add_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
+ require_send = 1;
+ if (buffer)
+ free(buffer);
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG( "pathmove: %i states, end in %s", cmd->cmd.pathmove->num_states,
- tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]) );
+ LOG_DEBUG( "%s scan, %i bits, end in %s", (cmd->cmd.scan->ir_scan) ? "IR" : "DR", scan_size,
+ tap_state_name( tap_get_end_state() ) );
#endif
- break;
+ return retval;
- case JTAG_SCAN:
- scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
- type = jtag_scan_type(cmd->cmd.scan);
- predicted_size = ft2232_predict_scan_out(scan_size, type);
- if ( (predicted_size + 1) > FT2232_BUFFER_SIZE )
- {
- LOG_DEBUG("oversized ft2232 scan (predicted_size > FT2232_BUFFER_SIZE)");
- /* unsent commands before this */
- if (first_unsent != cmd)
- if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
- retval = ERROR_JTAG_QUEUE_FAILED;
+}
- /* current command */
- if (cmd->cmd.scan->end_state != TAP_INVALID)
- ft2232_end_state(cmd->cmd.scan->end_state);
- ft2232_large_scan(cmd->cmd.scan, type, buffer, scan_size);
- require_send = 0;
- first_unsent = cmd->next;
- if (buffer)
- free(buffer);
- break;
- }
- else if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
- {
- LOG_DEBUG("ft2232 buffer size reached, sending queued commands (first_unsent: %p, cmd: %p)",
- first_unsent,
- cmd);
- if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
- retval = ERROR_JTAG_QUEUE_FAILED;
- require_send = 0;
- first_unsent = cmd;
- }
- ft2232_expect_read += ft2232_predict_scan_in(scan_size, type);
- /* LOG_DEBUG("new read size: %i", ft2232_expect_read); */
- if (cmd->cmd.scan->end_state != TAP_INVALID)
- ft2232_end_state(cmd->cmd.scan->end_state);
- ft2232_add_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
- require_send = 1;
- if (buffer)
- free(buffer);
+static int ft2232_execute_reset(jtag_command_t *cmd)
+{
+ int retval;
+ int predicted_size = 0;
+ retval = ERROR_OK;
+
+ DEBUG_JTAG_IO("reset trst: %i srst %i",
+ cmd->cmd.reset->trst, cmd->cmd.reset->srst);
+
+ /* only send the maximum buffer size that FT2232C can handle */
+ predicted_size = 3;
+ if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
+ {
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
+ require_send = 0;
+ first_unsent = cmd;
+ }
+
+ if ( (cmd->cmd.reset->trst == 1) || ( cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST) ) )
+ {
+ tap_set_state(TAP_RESET);
+ }
+ layout->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
+ require_send = 1;
+
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG( "%s scan, %i bits, end in %s", (cmd->cmd.scan->ir_scan) ? "IR" : "DR", scan_size,
- tap_state_name( tap_get_end_state() ) );
+ LOG_DEBUG("trst: %i, srst: %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
#endif
- break;
+ return retval;
+}
- case JTAG_SLEEP:
- if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
+static int ft2232_execute_sleep(jtag_command_t *cmd)
+{
+ int retval;
+ retval = ERROR_OK;
+
+ DEBUG_JTAG_IO("sleep %i", cmd->cmd.sleep->us);
+
+ if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
retval = ERROR_JTAG_QUEUE_FAILED;
- first_unsent = cmd->next;
- jtag_sleep(cmd->cmd.sleep->us);
+ first_unsent = cmd->next;
+ jtag_sleep(cmd->cmd.sleep->us);
#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG( "sleep %i usec while in %s", cmd->cmd.sleep->us, tap_state_name( tap_get_state() ) );
#endif
- break;
- case JTAG_STABLECLOCKS:
+ return retval;
+}
- /* this is only allowed while in a stable state. A check for a stable
- * state was done in jtag_add_clocks()
- */
- if (ft2232_stableclocks(cmd->cmd.stableclocks->num_cycles, cmd) != ERROR_OK)
- retval = ERROR_JTAG_QUEUE_FAILED;
+static int ft2232_execute_stableclocks(jtag_command_t *cmd)
+{
+ int retval;
+ retval = ERROR_OK;
+
+ /* this is only allowed while in a stable state. A check for a stable
+ * state was done in jtag_add_clocks()
+ */
+ if (ft2232_stableclocks(cmd->cmd.stableclocks->num_cycles, cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG( "clocks %i while in %s", cmd->cmd.stableclocks->num_cycles, tap_state_name( tap_get_state() ) );
+ LOG_DEBUG( "clocks %i while in %s", cmd->cmd.stableclocks->num_cycles, tap_state_name( tap_get_state() ) );
#endif
- break;
+ return retval;
+}
+
+static int ft2232_execute_command(jtag_command_t *cmd)
+{
+ int retval;
+ retval = ERROR_OK;
+
+ switch (cmd->type)
+ {
+ case JTAG_END_STATE: retval = ft2232_execute_end_state(cmd); break;
+ case JTAG_RESET: retval = ft2232_execute_reset(cmd); break;
+ case JTAG_RUNTEST: retval = ft2232_execute_runtest(cmd); break;
+ case JTAG_STATEMOVE: retval = ft2232_execute_statemove(cmd); break;
+ case JTAG_PATHMOVE: retval = ft2232_execute_pathmove(cmd); break;
+ case JTAG_SCAN: retval = ft2232_execute_scan(cmd); break;
+ case JTAG_SLEEP: retval = ft2232_execute_sleep(cmd); break;
+ case JTAG_STABLECLOCKS: retval = ft2232_execute_stableclocks(cmd); break;
default:
LOG_ERROR("BUG: unknown JTAG command type encountered");
- exit(-1);
- }
+ exit(-1);
+ }
+ return retval;
+}
+static int ft2232_execute_queue()
+{
+ jtag_command_t* cmd = jtag_command_queue; /* currently processed command */
+ int retval;
+
+ first_unsent = cmd; /* next command that has to be sent */
+ require_send = 0;
+
+ /* return ERROR_OK, unless ft2232_send_and_recv reports a failed check
+ * that wasn't handled by a caller-provided error handler
+ */
+ retval = ERROR_OK;
+
+ ft2232_buffer_size = 0;
+ ft2232_expect_read = 0;
+
+ /* blink, if the current layout has that feature */
+ if (layout->blink)
+ layout->blink();
+
+ while (cmd)
+ {
+ if (ft2232_execute_command(cmd) != ERROR_OK)
+ retval = ERROR_JTAG_QUEUE_FAILED;
cmd = cmd->next;
}
|
|
From: <oh...@ma...> - 2009-04-24 20:10:08
|
Author: oharboe
Date: 2009-04-24 20:10:04 +0200 (Fri, 24 Apr 2009)
New Revision: 1525
Modified:
trunk/src/jtag/jlink.c
trunk/src/jtag/jtag.c
trunk/src/jtag/jtag.h
Log:
add jtag_debug_state_machine
Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c 2009-04-24 16:24:55 UTC (rev 1524)
+++ trunk/src/jtag/jlink.c 2009-04-24 18:10:04 UTC (rev 1525)
@@ -114,6 +114,8 @@
static void jlink_debug_buffer(u8 *buffer, int length);
#endif
+static enum tap_state jlink_last_state = TAP_RESET;
+
static jlink_jtag_t* jlink_jtag_handle;
/***************************************************************************/
@@ -681,6 +683,9 @@
memcpy(usb_out_buffer + 4, tms_buffer, byte_length);
memcpy(usb_out_buffer + 4 + byte_length, tdi_buffer, byte_length);
+ jlink_last_state = jtag_debug_state_machine(tms_buffer, tdi_buffer,
+ tap_length, jlink_last_state);
+
result = jlink_usb_message(jlink_jtag_handle, 4 + 2 * byte_length, byte_length);
if (result != byte_length)
{
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-04-24 16:24:55 UTC (rev 1524)
+++ trunk/src/jtag/jtag.c 2009-04-24 18:10:04 UTC (rev 1525)
@@ -3283,4 +3283,89 @@
return TAP_INVALID;
}
+#ifdef _DEBUG_JTAG_IO_
+
+#define JTAG_DEBUG_STATE_APPEND(buf, len, bit) \
+ do { buf[len] = bit ? '1' : '0'; } while(0)
+#define JTAG_DEBUG_STATE_PRINT(a, b, astr, bstr) \
+ DEBUG_JTAG_IO("TAP/SM: %9s -> %5s\tTMS: %s\tTDI: %s", \
+ tap_state_name(a), tap_state_name(b), astr, bstr)
+
+tap_state_t jtag_debug_state_machine(const void *tms_buf, const void *tdi_buf,
+ unsigned tap_bits, tap_state_t next_state)
+{
+ const u8 *tms_buffer;
+ const u8 *tdi_buffer;
+ unsigned tap_bytes;
+ unsigned cur_byte;
+ unsigned cur_bit;
+
+ unsigned tap_out_bits;
+ char tms_str[33];
+ char tdi_str[33];
+
+ tap_state_t last_state;
+
+ // set startstate (and possibly last, if tap_bits == 0)
+ last_state = next_state;
+ DEBUG_JTAG_IO("TAP/SM: START state: %s", tap_state_name(next_state));
+
+ tms_buffer = (const u8 *)tms_buf;
+ tdi_buffer = (const u8 *)tdi_buf;
+
+ tap_bytes = TAP_SCAN_BYTES(tap_bits);
+ DEBUG_JTAG_IO("TAP/SM: TMS bits: %u (bytes: %u)", tap_bits, tap_bytes);
+
+ tap_out_bits = 0;
+ for(cur_byte = 0; cur_byte < tap_bytes; cur_byte++)
+ {
+ for(cur_bit = 0; cur_bit < 8; cur_bit++)
+ {
+ // make sure we do not run off the end of the buffers
+ unsigned tap_bit = cur_byte * 8 + cur_bit;
+ if (tap_bit == tap_bits)
+ break;
+
+ // check and save TMS bit
+ tap_bit = !!(tms_buffer[cur_byte] & (1 << cur_bit));
+ JTAG_DEBUG_STATE_APPEND(tms_str, tap_out_bits, tap_bit);
+
+ // use TMS bit to find the next TAP state
+ next_state = tap_state_transition(last_state, tap_bit);
+
+ // check and store TDI bit
+ tap_bit = !!(tdi_buffer[cur_byte] & (1 << cur_bit));
+ JTAG_DEBUG_STATE_APPEND(tdi_str, tap_out_bits, tap_bit);
+
+ // increment TAP bits
+ tap_out_bits++;
+
+ // Only show TDO bits on state transitions, or
+ // after some number of bits in the same state.
+ if ((next_state == last_state) && (tap_out_bits < 32))
+ continue;
+
+ // terminate strings and display state transition
+ tms_str[tap_out_bits] = tdi_str[tap_out_bits] = 0;
+ JTAG_DEBUG_STATE_PRINT(last_state, next_state, tms_str, tdi_str);
+
+ // reset state
+ last_state = next_state;
+ tap_out_bits = 0;
+ }
+ }
+
+ if (tap_out_bits)
+ {
+ // terminate strings and display state transition
+ tms_str[tap_out_bits] = tdi_str[tap_out_bits] = 0;
+ JTAG_DEBUG_STATE_PRINT(last_state, next_state, tms_str, tdi_str);
+ }
+
+ DEBUG_JTAG_IO("TAP/SM: FINAL state: %s", tap_state_name(next_state));
+
+ return next_state;
+}
+#endif // _DEBUG_JTAG_IO_
+
/*-----</Cable Helper API>--------------------------------------*/
Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h 2009-04-24 16:24:55 UTC (rev 1524)
+++ trunk/src/jtag/jtag.h 2009-04-24 18:10:04 UTC (rev 1525)
@@ -206,6 +206,25 @@
*/
const char* tap_state_name(tap_state_t state);
+#ifdef _DEBUG_JTAG_IO_
+/**
+ * @brief Prints verbose TAP state transitions for the given TMS/TDI buffers.
+ * @param tms_buf must points to a buffer containing the TMS bitstream.
+ * @param tdi_buf must points to a buffer containing the TDI bitstream.
+ * @param tap_len must specify the length of the TMS/TDI bitstreams.
+ * @param start_tap_state must specify the current TAP state.
+ * @returns the final TAP state; pass as @a start_tap_state in following call.
+ */
+tap_state_t jtag_debug_state_machine(const void *tms_buf, const void *tdi_buf,
+ unsigned tap_len, tap_state_t start_tap_state);
+#else
+static inline tap_state_t jtag_debug_state_machine(const void *tms_buf,
+ const void *tdi_buf, unsigned tap_len, tap_state_t start_tap_state)
+{
+ return start_tap_state;
+}
+#endif // _DEBUG_JTAG_IO_
+
/*-----</Cable Helper API>------------------------------------------*/
|
|
From: <oh...@ma...> - 2009-04-24 18:24:59
|
Author: oharboe
Date: 2009-04-24 18:24:55 +0200 (Fri, 24 Apr 2009)
New Revision: 1524
Modified:
trunk/src/jtag/jlink.c
trunk/src/jtag/jtag.h
Log:
Zach Welch <zw...@su...> add TAP_SCAN_BYTES macro (1 of 2)
Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c 2009-04-24 16:14:21 UTC (rev 1523)
+++ trunk/src/jtag/jlink.c 2009-04-24 16:24:55 UTC (rev 1524)
@@ -672,7 +672,7 @@
return ERROR_OK;
// number of full bytes (plus one if some would be left over)
- byte_length = tap_length / 8 + !!(tap_length % 8);
+ byte_length = TAP_SCAN_BYTES(tap_length);
usb_out_buffer[0] = EMU_CMD_HW_JTAG3;
usb_out_buffer[1] = 0;
Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h 2009-04-24 16:14:21 UTC (rev 1523)
+++ trunk/src/jtag/jtag.h 2009-04-24 16:24:55 UTC (rev 1524)
@@ -217,6 +217,9 @@
struct scan_field_s;
typedef int (*in_handler_t)(u8* in_value, void* priv, struct scan_field_s* field);
+/// @brief calculates number of bytes required to hold @a n TAP scan bits
+#define TAP_SCAN_BYTES(n) (((n) / 8) + !!((n) % 8))
+
typedef struct scan_field_s
{
jtag_tap_t* tap; /* tap pointer this instruction refers to */
|
|
From: <oh...@ma...> - 2009-04-24 18:14:25
|
Author: oharboe Date: 2009-04-24 18:14:21 +0200 (Fri, 24 Apr 2009) New Revision: 1523 Modified: trunk/bootstrap Log: Zach Welch <zw...@su...> add --enable-maintainer-mode reminder Modified: trunk/bootstrap =================================================================== --- trunk/bootstrap 2009-04-24 12:12:36 UTC (rev 1522) +++ trunk/bootstrap 2009-04-24 16:14:21 UTC (rev 1523) @@ -2,3 +2,7 @@ && autoheader \ && automake --foreign --add-missing --copy \ && autoconf + +# AM_MAINTAINER_MODE requires SVN users provide --enable-maintainer-mode +# otherwise the documentation will fail to build due to missing version.texi +echo "Bootstrap complete; you can './configure --enable-maintainer-mode ....'" |
|
From: oharboe at B. <oh...@ma...> - 2009-04-24 14:12:36
|
Author: oharboe
Date: 2009-04-24 14:12:36 +0200 (Fri, 24 Apr 2009)
New Revision: 1522
Modified:
trunk/contrib/openocd.udev
Log:
Uwe Hermann <uw...@he...> Update udev file
Modified: trunk/contrib/openocd.udev
===================================================================
--- trunk/contrib/openocd.udev 2009-04-24 11:05:21 UTC (rev 1521)
+++ trunk/contrib/openocd.udev 2009-04-24 12:12:36 UTC (rev 1522)
@@ -1,28 +1,56 @@
-BUS!="usb", ACTION!="add", SUBSYSTEM!=="usb_device", GOTO="openocd_rules_end"
-
-# Olimex ARM-USB-OCD
-SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0003", MODE="664", GROUP="plugdev"
-
-# Olimex ARM-USB-OCD-TINY
-SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0004", MODE="664", GROUP="plugdev"
-
-# USBprog with OpenOCD firmware
-SYSFS{idVendor}=="1781", SYSFS{idProduct}=="0c63", MODE="664", GROUP="plugdev"
-
-# Amontec JTAGkey
-SYSFS{idVendor}=="0403", SYSFS{idProduct}=="cff8", MODE="664", GROUP="plugdev"
-
-# Amontec JTAGkey-HiSpeed
-SYSFS{idVendor}=="0fbb", SYSFS{idProduct}=="1000", MODE="664", GROUP="plugdev"
-
-# IAR J-Link USB
-SYSFS{idVendor}=="1366", SYSFS{idProduct}=="0101", MODE="664", GROUP="plugdev"
-
-# Raisonance RLink
-SYSFS{idVendor}=="138e", SYSFS{idProduct}=="9000", MODE="664", GROUP="plugdev"
-
-# Olimex ARM-JTAG-EW
-SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="001e", MODE="664", GROUP="plugdev"
-
-LABEL="openocd_rules_end"
-
+BUS!="usb", ACTION!="add", SUBSYSTEM!=="usb_device", GOTO="openocd_rules_end"
+
+# Olimex ARM-USB-OCD
+SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0003", MODE="664", GROUP="plugdev"
+
+# Olimex ARM-USB-OCD-TINY
+SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0004", MODE="664", GROUP="plugdev"
+
+# Olimex ARM-JTAG-EW
+SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="001e", MODE="664", GROUP="plugdev"
+
+# USBprog with OpenOCD firmware
+SYSFS{idVendor}=="1781", SYSFS{idProduct}=="0c63", MODE="664", GROUP="plugdev"
+
+# Amontec JTAGkey and JTAGkey-tiny
+SYSFS{idVendor}=="0403", SYSFS{idProduct}=="cff8", MODE="664", GROUP="plugdev"
+
+# Amontec JTAGkey-HiSpeed
+SYSFS{idVendor}=="0fbb", SYSFS{idProduct}=="1000", MODE="664", GROUP="plugdev"
+
+# Axiom AXM-0432 Link (Symphony SoundBite?)
+# Calao Systems USB-A9260-C01
+# TinCanTools Flyswatter
+# OOCD-Link
+# Marvell Sheevaplug (early development versions)
+SYSFS{idVendor}=="0403", SYSFS{idProduct}=="6010", MODE="664", GROUP="plugdev"
+
+# Calao Systems USB-A9260-C02
+SYSFS{idVendor}=="0403", SYSFS{idProduct}=="6001", MODE="664", GROUP="plugdev"
+
+# IAR J-Link USB
+SYSFS{idVendor}=="1366", SYSFS{idProduct}=="0101", MODE="664", GROUP="plugdev"
+
+# Raisonance RLink
+SYSFS{idVendor}=="138e", SYSFS{idProduct}=="9000", MODE="664", GROUP="plugdev"
+
+# Hitex STR9-comStick
+SYSFS{idVendor}=="0640", SYSFS{idProduct}=="002c", MODE="664", GROUP="plugdev"
+
+# Hitex STM32-PerformanceStick
+SYSFS{idVendor}=="0640", SYSFS{idProduct}=="002d", MODE="664", GROUP="plugdev"
+
+# Luminary Micro Stellaris/LM3S811
+SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bcd9", MODE="664", GROUP="plugdev"
+
+# Xverve Signalyzer Tool (DT-USB-ST)
+SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bca0", MODE="664", GROUP="plugdev"
+
+# egnite Turtelizer 2
+SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bdc8", MODE="664", GROUP="plugdev"
+
+# Marvell Sheevaplug
+SYSFS{idVendor}=="9e88", SYSFS{idProduct}=="9e8f", MODE="664", GROUP="plugdev"
+
+LABEL="openocd_rules_end"
+
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-24 13:05:23
|
Author: oharboe
Date: 2009-04-24 13:05:21 +0200 (Fri, 24 Apr 2009)
New Revision: 1521
Modified:
trunk/src/jtag/jlink.c
Log:
Zach Welch <zw...@su...> use memcpy
Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c 2009-04-24 06:04:40 UTC (rev 1520)
+++ trunk/src/jtag/jlink.c 2009-04-24 11:05:21 UTC (rev 1521)
@@ -665,8 +665,6 @@
static int jlink_tap_execute(void)
{
int byte_length;
- int tms_offset;
- int tdi_offset;
int i;
int result;
@@ -680,21 +678,10 @@
usb_out_buffer[1] = 0;
usb_out_buffer[2] = (tap_length >> 0) & 0xff;
usb_out_buffer[3] = (tap_length >> 8) & 0xff;
+ memcpy(usb_out_buffer + 4, tms_buffer, byte_length);
+ memcpy(usb_out_buffer + 4 + byte_length, tdi_buffer, byte_length);
- tms_offset = 4;
- for (i = 0; i < byte_length; i++)
- {
- usb_out_buffer[tms_offset + i] = tms_buffer[i];
- }
-
- tdi_offset = tms_offset + byte_length;
- for (i = 0; i < byte_length; i++)
- {
- usb_out_buffer[tdi_offset + i] = tdi_buffer[i];
- }
-
result = jlink_usb_message(jlink_jtag_handle, 4 + 2 * byte_length, byte_length);
-
if (result != byte_length)
{
LOG_ERROR("jlink_tap_execute, wrong result %d (expected %d)",
@@ -702,8 +689,7 @@
return ERROR_JTAG_QUEUE_FAILED;
}
- for (i = 0; i < byte_length; i++)
- tdo_buffer[i] = usb_in_buffer[i];
+ memcpy(tdo_buffer, usb_in_buffer, byte_length);
for (i = 0; i < pending_scan_results_length; i++)
{
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-24 08:04:45
|
Author: oharboe Date: 2009-04-24 08:04:40 +0200 (Fri, 24 Apr 2009) New Revision: 1520 Modified: trunk/src/target/interface/sheevaplug.cfg Log: Nicolas Pitre <ni...@ca...> update SheevaPlug interface cfg file Modified: trunk/src/target/interface/sheevaplug.cfg =================================================================== --- trunk/src/target/interface/sheevaplug.cfg 2009-04-24 06:02:02 UTC (rev 1519) +++ trunk/src/target/interface/sheevaplug.cfg 2009-04-24 06:04:40 UTC (rev 1520) @@ -6,7 +6,7 @@ interface ft2232 ft2232_layout sheevaplug -ft2232_vid_pid 0x0403 0x6010 -# TODO: Add ft2232_device_desc? +ft2232_vid_pid 0x9e88 0x9e8f +ft2232_device_desc "SheevaPlug JTAGKey FT2232D B" jtag_khz 3000 |
|
From: oharboe at B. <oh...@ma...> - 2009-04-24 08:02:10
|
Author: oharboe Date: 2009-04-24 08:02:02 +0200 (Fri, 24 Apr 2009) New Revision: 1519 Modified: trunk/src/target/board/olimex_stm32_h103.cfg trunk/src/target/board/stm32f10x_128k_eval.cfg Log: Uwe Hermann <uw...@he...> drop unecessary BSTAPIDs Modified: trunk/src/target/board/olimex_stm32_h103.cfg =================================================================== --- trunk/src/target/board/olimex_stm32_h103.cfg 2009-04-24 02:13:02 UTC (rev 1518) +++ trunk/src/target/board/olimex_stm32_h103.cfg 2009-04-24 06:02:02 UTC (rev 1519) @@ -4,7 +4,5 @@ # http://olimex.com/dev/stm32-h103.html # -set BSTAPID 0x16410041 - source [find target/stm32.cfg] Modified: trunk/src/target/board/stm32f10x_128k_eval.cfg =================================================================== --- trunk/src/target/board/stm32f10x_128k_eval.cfg 2009-04-24 02:13:02 UTC (rev 1518) +++ trunk/src/target/board/stm32f10x_128k_eval.cfg 2009-04-24 06:02:02 UTC (rev 1519) @@ -1,6 +1,4 @@ # This is an STM32 eval board with a single STM32F103VBT6 chip on it. -# My test board has a "Rev1" tap id. -set BSTAPID 0x16410041 source [find target/stm32.cfg] |
