openocd-commit Mailing List for OpenOCD - Open On-Chip Debugger (Page 216)

The Open On-Chip Debugger

Brought to you by: dail, gowinex, ntfreak

openocd-commit — OpenOCD commit maling list - read only

You can subscribe to this list here.

2008	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec (75)
2009	Jan (70)	Feb (20)	Mar (52)	Apr (149)	May (387)	Jun (466)	Jul (133)	Aug (87)	Sep (122)	Oct (140)	Nov (185)	Dec (105)
2010	Jan (85)	Feb (45)	Mar (75)	Apr (17)	May (41)	Jun (52)	Jul (33)	Aug (29)	Sep (36)	Oct (15)	Nov (26)	Dec (34)
2011	Jan (26)	Feb (25)	Mar (26)	Apr (29)	May (20)	Jun (27)	Jul (15)	Aug (32)	Sep (13)	Oct (64)	Nov (60)	Dec (10)
2012	Jan (64)	Feb (63)	Mar (39)	Apr (43)	May (54)	Jun (11)	Jul (30)	Aug (45)	Sep (11)	Oct (70)	Nov (24)	Dec (23)
2013	Jan (17)	Feb (8)	Mar (35)	Apr (40)	May (20)	Jun (24)	Jul (36)	Aug (25)	Sep (42)	Oct (40)	Nov (9)	Dec (21)
2014	Jan (29)	Feb (24)	Mar (60)	Apr (22)	May (22)	Jun (46)	Jul (11)	Aug (23)	Sep (26)	Oct (10)	Nov (14)	Dec (2)
2015	Jan (28)	Feb (47)	Mar (33)	Apr (58)	May (5)	Jun (1)	Jul	Aug (8)	Sep (12)	Oct (25)	Nov (58)	Dec (21)
2016	Jan (12)	Feb (40)	Mar (2)	Apr (1)	May (67)	Jun (2)	Jul (5)	Aug (36)	Sep	Oct (24)	Nov (17)	Dec (50)
2017	Jan (14)	Feb (16)	Mar (2)	Apr (35)	May (14)	Jun (16)	Jul (3)	Aug (3)	Sep	Oct (19)	Nov	Dec (16)
2018	Jan (55)	Feb (11)	Mar (34)	Apr (14)	May (4)	Jun (20)	Jul (39)	Aug (16)	Sep (17)	Oct (16)	Nov (20)	Dec (30)
2019	Jan (29)	Feb (24)	Mar (37)	Apr (26)	May (19)	Jun (21)	Jul (2)	Aug (3)	Sep (9)	Oct (12)	Nov (12)	Dec (12)
2020	Jan (47)	Feb (36)	Mar (54)	Apr (44)	May (37)	Jun (19)	Jul (32)	Aug (13)	Sep (16)	Oct (24)	Nov (32)	Dec (11)
2021	Jan (14)	Feb (5)	Mar (40)	Apr (32)	May (42)	Jun (31)	Jul (29)	Aug (47)	Sep (38)	Oct (17)	Nov (74)	Dec (33)
2022	Jan (11)	Feb (15)	Mar (40)	Apr (21)	May (39)	Jun (44)	Jul (19)	Aug (46)	Sep (79)	Oct (35)	Nov (21)	Dec (15)
2023	Jan (56)	Feb (13)	Mar (43)	Apr (28)	May (60)	Jun (15)	Jul (29)	Aug (28)	Sep (32)	Oct (21)	Nov (42)	Dec (39)
2024	Jan (35)	Feb (17)	Mar (28)	Apr (7)	May (14)	Jun (35)	Jul (30)	Aug (35)	Sep (30)	Oct (28)	Nov (38)	Dec (18)
2025	Jan (21)	Feb (28)	Mar (36)	Apr (35)	May (34)	Jun (58)	Jul (9)	Aug (37)	Sep	Oct	Nov	Dec

Flat | Threaded

<< < 1 .. 214 215 216 217 218 .. 289 > >> (Page 216 of 289)

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-523-g5c4a73d

From: Øyvind H. <go...@us...> - 2009-11-22 13:50:29

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  5c4a73d0d89989b7fbe260ed4fa00a8259e01b03 (commit)
      from  700a60ec573e9cfdbcac3c1c30ee5e94aeddfa6a (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 5c4a73d0d89989b7fbe260ed4fa00a8259e01b03
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Wed Nov 18 11:08:33 2009 +0100

    zy1000: un-break uart command after command handler refactoring
    
    Switched it to jim command to insulate it from command refactoring.
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/ecosboard.c b/src/ecosboard.c
index 120b3f9..58520c3 100644
--- a/src/ecosboard.c
+++ b/src/ecosboard.c
@@ -845,21 +845,25 @@ void startUart(void)
 	cyg_thread_resume(zylinjtag_uart_thread_handle);
 }
 
-int handle_uart_command(struct command_context *cmd_ctx, char *cmd,
-		char **args, int argc)
+static int zylinjtag_Jim_Command_uart(Jim_Interp *interp, int argc,
+		Jim_Obj * const *argv)
 {
 	static int current_baud = 38400;
-	if (argc == 0)
+	if (argc == 1)
 	{
 		command_print(cmd_ctx, "%d", current_baud);
-		return ERROR_OK;
+		return JIM_OK;
 	}
-	else if (argc != 1)
+	else if (argc != 2)
 	{
-		return ERROR_INVALID_ARGUMENTS;
+		return JIM_ERR;
 	}
 
-	current_baud = atol(args[0]);
+	long new_baudrate;
+	if (Jim_GetLong(interp, argv[1], &new_baudrate) != JIM_OK)
+		return JIM_ERR;
+
+	current_baud = new_baudrate;
 
 	int baud;
 	switch (current_baud)
@@ -898,7 +902,7 @@ int handle_uart_command(struct command_context *cmd_ctx, char *cmd,
 	if (err != ENOERR)
 	{
 		LOG_ERROR("Could not open serial port\n");
-		return ERROR_FAIL;
+		return JIM_ERR;
 	}
 
 	err = cyg_io_get_config(serial_handle,
@@ -907,8 +911,8 @@ int handle_uart_command(struct command_context *cmd_ctx, char *cmd,
 			&len);
 	if (err != ENOERR)
 	{
-		command_print(cmd_ctx, "Failed to get serial port settings %d", err);
-		return ERROR_OK;
+		LOG_ERROR("Failed to get serial port settings %d", err);
+		return JIM_ERR;
 	}
 	buf.baud = baud;
 
@@ -916,11 +920,11 @@ int handle_uart_command(struct command_context *cmd_ctx, char *cmd,
 			&len);
 	if (err != ENOERR)
 	{
-		command_print(cmd_ctx, "Failed to set serial port settings %d", err);
-		return ERROR_OK;
+		LOG_ERROR("Failed to set serial port settings %d", err);
+		return JIM_ERR;
 	}
 
-	return ERROR_OK;
+	return JIM_OK;
 }
 
 bool logAllToSerial = false;
@@ -1091,8 +1095,8 @@ int main(int argc, char *argv[])
 			COMMAND_ANY, NULL);
 #endif
 
-	register_command(cmd_ctx, NULL, "uart", handle_uart_command, COMMAND_ANY,
-			"uart <baud>  - forward uart on port 5555");
+	Jim_CreateCommand(interp, "uart", zylinjtag_Jim_Command_uart, NULL, NULL);
+
 
 	int errVal;
 	errVal = log_init(cmd_ctx);

-----------------------------------------------------------------------

Summary of changes:
 src/ecosboard.c |   34 +++++++++++++++++++---------------
 1 files changed, 19 insertions(+), 15 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-522-g700a60e

From: Øyvind H. <go...@us...> - 2009-11-22 13:42:52

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  700a60ec573e9cfdbcac3c1c30ee5e94aeddfa6a (commit)
       via  964c3639e2464b18d72f16fa175fee9beb843b36 (commit)
       via  31da0003dc6d307faa8fd66eb23319bd5e9ab7dd (commit)
       via  808e53368c2c1daee3f6a5eb59038b990534f1ac (commit)
      from  d1fbcc35899f6071d097b8dfb76ab3125c3c4fac (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 700a60ec573e9cfdbcac3c1c30ee5e94aeddfa6a
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Sat Nov 21 23:29:58 2009 +0100

    embedded: reduce stack usage
    
    Allocate working structures on stack to avoid issues with
    path lengths + reduce stack usage.
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/helper/configuration.c b/src/helper/configuration.c
index 2ea5da4..007246c 100644
--- a/src/helper/configuration.c
+++ b/src/helper/configuration.c
@@ -61,21 +61,23 @@ char *find_file(const char *file)
 	char **search_dirs = script_search_dirs;
 	char *dir;
 	char const *mode="r";
-	char full_path[1024];
+	char *full_path;
 
 	/* Check absolute and relative to current working dir first.
 	 * This keeps full_path reporting belowing working. */
-	snprintf(full_path, 1024, "%s", file);
+	full_path = alloc_printf("%s", file);
 	fp = fopen(full_path, mode);
 
 	while (!fp)
 	{
+		free(full_path);
+		full_path = NULL;
 		dir = *search_dirs++;
 
 		if (!dir)
 			break;
 
-		snprintf(full_path, 1024, "%s/%s", dir, file);
+		full_path = alloc_printf("%s/%s", dir, file);
 		fp = fopen(full_path, mode);
 	}
 
@@ -83,8 +85,11 @@ char *find_file(const char *file)
 	{
 		fclose(fp);
 		LOG_DEBUG("found %s", full_path);
-		return strdup(full_path);
+		return full_path;
 	}
+
+	free(full_path);
+
 	return NULL;
 }
 

commit 964c3639e2464b18d72f16fa175fee9beb843b36
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Sat Nov 21 23:25:46 2009 +0100

    embedded: do not allocate large temporary structures on stack
    
    With -O3 when inlining aggressively the total stack usage will
    be the sum of many fn's, which can easily get out of hand.
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/target/image.c b/src/target/image.c
index 76c8cc9..ca7123a 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -147,18 +147,16 @@ static int identify_image_type(struct image *image, const char *type_string, con
 	return ERROR_OK;
 }
 
-static int image_ihex_buffer_complete(struct image *image)
+static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, struct imageection *section)
 {
 	struct image_ihex *ihex = image->type_private;
 	struct fileio *fileio = &ihex->fileio;
 	uint32_t full_address = 0x0;
 	uint32_t cooked_bytes;
 	int i;
-	char lpszLine[1023];
 
 	/* we can't determine the number of sections that we'll have to create ahead of time,
 	 * so we locally hold them until parsing is finished */
-	struct imageection section[IMAGE_MAX_SECTIONS];
 
 	ihex->buffer = malloc(fileio->size >> 1);
 	cooked_bytes = 0x0;
@@ -357,6 +355,35 @@ static int image_ihex_buffer_complete(struct image *image)
 	return ERROR_IMAGE_FORMAT_ERROR;
 }
 
+/**
+ * Allocate memory dynamically instead of on the stack. This
+ * is important w/embedded hosts.
+ */
+static int image_ihex_buffer_complete(struct image *image)
+{
+	char *lpszLine = malloc(1023);
+	if (lpszLine == NULL)
+	{
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+	struct imageection *section = malloc(sizeof(struct imageection) * IMAGE_MAX_SECTIONS);
+	if (section == NULL)
+	{
+		free(lpszLine);
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+	int retval;
+
+	retval = image_ihex_buffer_complete_inner(image, lpszLine, section);
+
+	free(section);
+	free(lpszLine);
+
+	return retval;
+}
+
 static int image_elf_read_headers(struct image *image)
 {
 	struct image_elf *elf = image->type_private;
@@ -499,18 +526,16 @@ static int image_elf_read_section(struct image *image, int section, uint32_t off
 	return ERROR_OK;
 }
 
-static int image_mot_buffer_complete(struct image *image)
+static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, struct imageection *section)
 {
 	struct image_mot *mot = image->type_private;
 	struct fileio *fileio = &mot->fileio;
 	uint32_t full_address = 0x0;
 	uint32_t cooked_bytes;
 	int i;
-	char lpszLine[1023];
 
 	/* we can't determine the number of sections that we'll have to create ahead of time,
 	 * so we locally hold them until parsing is finished */
-	struct imageection section[IMAGE_MAX_SECTIONS];
 
 	mot->buffer = malloc(fileio->size >> 1);
 	cooked_bytes = 0x0;
@@ -669,6 +694,36 @@ static int image_mot_buffer_complete(struct image *image)
 	return ERROR_IMAGE_FORMAT_ERROR;
 }
 
+/**
+ * Allocate memory dynamically instead of on the stack. This
+ * is important w/embedded hosts.
+ */
+static int image_mot_buffer_complete(struct image *image)
+{
+	char *lpszLine = malloc(1023);
+	if (lpszLine == NULL)
+	{
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+	struct imageection *section = malloc(sizeof(struct imageection) * IMAGE_MAX_SECTIONS);
+	if (section == NULL)
+	{
+		free(lpszLine);
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+	int retval;
+
+	retval = image_mot_buffer_complete_inner(image, lpszLine, section);
+
+	free(section);
+	free(lpszLine);
+
+	return retval;
+}
+
+
 int image_open(struct image *image, const char *url, const char *type_string)
 {
 	int retval = ERROR_OK;

commit 31da0003dc6d307faa8fd66eb23319bd5e9ab7dd
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Sat Nov 21 23:45:36 2009 +0100

    embedded: save stack
    
    and also do not recaluate the crc32_table upon
    every invocation.
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/target/image.c b/src/target/image.c
index 8774c25..76c8cc9 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -1023,17 +1023,23 @@ int image_calculate_checksum(uint8_t* buffer, uint32_t nbytes, uint32_t* checksu
 	uint32_t crc = 0xffffffff;
 	LOG_DEBUG("Calculating checksum");
 
-	uint32_t crc32_table[256];
+	static uint32_t crc32_table[256];
 
-	/* Initialize the CRC table and the decoding table.  */
-	int i, j;
-	unsigned int c;
-	for (i = 0; i < 256; i++)
+	static bool first_init = false;
+	if (!first_init)
 	{
-		/* as per gdb */
-		for (c = i << 24, j = 8; j > 0; --j)
-			c = c & 0x80000000 ? (c << 1) ^ 0x04c11db7 : (c << 1);
-		crc32_table[i] = c;
+		/* Initialize the CRC table and the decoding table.  */
+		int i, j;
+		unsigned int c;
+		for (i = 0; i < 256; i++)
+		{
+			/* as per gdb */
+			for (c = i << 24, j = 8; j > 0; --j)
+				c = c & 0x80000000 ? (c << 1) ^ 0x04c11db7 : (c << 1);
+			crc32_table[i] = c;
+		}
+
+		first_init = true;
 	}
 
 	while (nbytes > 0)

commit 808e53368c2c1daee3f6a5eb59038b990534f1ac
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Sun Nov 22 13:16:48 2009 +0100

    zy1000: fix breakage in command parsing code for power command
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 28515c7..8b5b753 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -235,7 +235,7 @@ COMMAND_HANDLER(handle_power_command)
 		// fall through
 	}
 	case 0:
-		command_print(cmd_ctx, "Target power %s", savePower ? "on" : "off");
+		LOG_INFO("Target power %s", savePower ? "on" : "off");
 		break;
 	default:
 		return ERROR_INVALID_ARGUMENTS;

-----------------------------------------------------------------------

Summary of changes:
 src/helper/configuration.c |   13 ++++--
 src/jtag/zy1000/zy1000.c   |    2 +-
 src/target/image.c         |   91 ++++++++++++++++++++++++++++++++++++-------
 3 files changed, 86 insertions(+), 20 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-518-gd1fbcc3

From: Øyvind H. <go...@us...> - 2009-11-22 13:37:13

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d1fbcc35899f6071d097b8dfb76ab3125c3c4fac (commit)
      from  dd9894f481d127266c201d7075ecbdd34b034124 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit d1fbcc35899f6071d097b8dfb76ab3125c3c4fac
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Sun Nov 22 13:24:45 2009 +0100

    build: fix breakage in building bin2char
    
    bin2char build relied on $(builddir) which is not defined
    for arm-elf X builds at least.
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/Makefile.am b/src/Makefile.am
index 8f96b05..913118f 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -112,7 +112,7 @@ BUILT_SOURCES = startup.tcl
 startup.tcl: $(STARTUP_TCL_SRCS)
 	cat $^ > $@
 
-BIN2C = $(builddir)/helper/bin2char$(EXEEXT_FOR_BUILD)
+BIN2C = $(top_builddir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
 
 # Convert .tcl to cfile
 startup_tcl.c: startup.tcl $(BIN2C)

-----------------------------------------------------------------------

Summary of changes:
 src/Makefile.am |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-517-gdd9894f

From: David B. <dbr...@us...> - 2009-11-22 12:42:33

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  dd9894f481d127266c201d7075ecbdd34b034124 (commit)
       via  ff810723e051ed1f86cffcb565ade6b4d1fc50c8 (commit)
       via  5706fd7860ea01c591ecf74880a5a5e04e6df22e (commit)
       via  60a2d85af1afbc207ae5fb9dafdbe4c8b49ad5bb (commit)
      from  b58239e4c03c440ac89b36c9de917224a8439332 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit dd9894f481d127266c201d7075ecbdd34b034124
Author: David Brownell <dbr...@us...>
Date:   Sun Nov 22 03:41:14 2009 -0800

    ARM: arm_set_cpsr() handles T and J bits
    
    Have arm_set_cpsr() handle the two core state flags, updating
    the CPU state.  This eliminates code in various debug_entry()
    paths, and marginally improves handling of the J bit.
    
    Catch and comment a few holes in the handling of the J bit on
    ARM926ejs cores ... it's unlikely our users will care about
    Jazelle mode, but we can at least warn of Impending Doom.  If
    anyone does use it, these breadcrumbs may help them to find
    the right path through the code.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index ac7e488..3aa77ea 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -354,7 +354,6 @@ static int arm720t_soft_reset_halt(struct target *target)
 	cpsr |= 0xd3;
 	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 9580f62..19fe98d 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1223,6 +1223,8 @@ int arm7_9_soft_reset_halt(struct target *target)
 		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 	}
 
+	/* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
+
 	/* all register content is now invalid */
 	register_cache_invalidate(armv4_5->core_cache);
 
@@ -1234,7 +1236,6 @@ int arm7_9_soft_reset_halt(struct target *target)
 	cpsr |= 0xd3;
 	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
@@ -1334,7 +1335,7 @@ static int arm7_9_debug_entry(struct target *target)
 	uint32_t context[16];
 	uint32_t* context_p[16];
 	uint32_t r0_thumb, pc_thumb;
-	uint32_t cpsr;
+	uint32_t cpsr, cpsr_mask = 0;
 	int retval;
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
@@ -1379,11 +1380,21 @@ static int arm7_9_debug_entry(struct target *target)
 		LOG_DEBUG("target entered debug from Thumb state");
 		/* Entered debug from Thumb mode */
 		armv4_5->core_state = ARMV4_5_STATE_THUMB;
+		cpsr_mask = 1 << 5;
 		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
-		LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
-	}
-	else
-	{
+		LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
+			", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
+	} else if (buf_get_u32(dbg_stat->value, 5, 1)) {
+		/* \todo Get some vaguely correct handling of Jazelle, if
+		 * anyone ever uses it and full info becomes available.
+		 * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
+		 * B.7.3 for the reverse.  That'd be the bare minimum...
+		 */
+		LOG_DEBUG("target entered debug from Jazelle state");
+		armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+		cpsr_mask = 1 << 24;
+		LOG_ERROR("Jazelle debug entry -- BROKEN!");
+	} else {
 		LOG_DEBUG("target entered debug from ARM state");
 		/* Entered debug from ARM mode */
 		armv4_5->core_state = ARMV4_5_STATE_ARM;
@@ -1399,11 +1410,10 @@ static int arm7_9_debug_entry(struct target *target)
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 		return retval;
 
-	/* if the core has been executing in Thumb state, set the T bit */
-	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
-		cpsr |= 0x20;
-
-	arm_set_cpsr(armv4_5, cpsr);
+	/* Sync our CPSR copy with J or T bits EICE reported, but
+	 * which we then erased by putting the core into ARM mode.
+	 */
+	arm_set_cpsr(armv4_5, cpsr | cpsr_mask);
 
 	if (!is_arm_mode(armv4_5->core_mode))
 	{
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 739df3e..8a03554 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -603,7 +603,6 @@ int arm920t_soft_reset_halt(struct target *target)
 	cpsr |= 0xd3;
 	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 7ecc782..aa29989 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -572,7 +572,6 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	cpsr |= 0xd3;
 	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 3156c66..22e1186 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -372,6 +372,24 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 	arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS)
 			? NULL
 			: arm->core_cache->reg_list + arm->map[16];
+
+	/* Older ARMs won't have the J bit */
+	enum armv4_5_state state;
+
+	if (cpsr & (1 << 5)) {	/* T */
+		if (cpsr & (1 << 24)) {	/* J */
+			LOG_WARNING("ThumbEE -- incomplete support");
+			state = ARM_STATE_THUMB_EE;
+		} else
+			state = ARMV4_5_STATE_THUMB;
+	} else {
+		if (cpsr & (1 << 24)) {	/* J */
+			LOG_ERROR("Jazelle state handling is BROKEN!");
+			state = ARMV4_5_STATE_JAZELLE;
+		} else
+			state = ARMV4_5_STATE_ARM;
+	}
+	arm->core_state = state;
 }
 
 /**
@@ -481,49 +499,27 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 	/* Except for CPSR, the "reg" command exposes a writeback model
 	 * for the register cache.
 	 */
-	buf_set_u32(reg->value, 0, 32, value);
-	reg->dirty = 1;
-	reg->valid = 1;
+	if (reg == armv4_5_target->cpsr) {
+		arm_set_cpsr(armv4_5_target, value);
 
-	if (reg == armv4_5_target->cpsr)
-	{
-		/* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */
-		if (value & 0x20)
-		{
-			/* T bit should be set */
-			if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
-			{
-				/* change state to Thumb */
-				LOG_DEBUG("changing to Thumb state");
-				armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
-			}
-		}
-		else
-		{
-			/* T bit should be cleared */
-			if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
-			{
-				/* change state to ARM */
-				LOG_DEBUG("changing to ARM state");
-				armv4_5_target->core_state = ARMV4_5_STATE_ARM;
-			}
-		}
-
-		/* REVISIT Why only update core for mode change, not also
-		 * for state changes?  Possibly older cores need to stay
-		 * in ARM mode during halt mode debug, not execute Thumb;
-		 * v6/v7a/v7r seem to do that automatically...
+		/* Older cores need help to be in ARM mode during halt
+		 * mode debug, so we clear the J and T bits if we flush.
+		 * For newer cores (v6/v7a/v7r) we don't need that, but
+		 * it won't hurt since CPSR is always flushed anyway.
 		 */
-
-		if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
-		{
+		if (armv4_5_target->core_mode !=
+				(enum armv4_5_mode)(value & 0x1f)) {
 			LOG_DEBUG("changing ARM core mode to '%s'",
 					arm_mode_name(value & 0x1f));
+			value &= ~((1 << 24) | (1 << 5));
 			armv4_5_target->write_core_reg(target, reg,
 					16, ARMV4_5_MODE_ANY, value);
-			arm_set_cpsr(armv4_5_target, value);
 		}
+	} else {
+		buf_set_u32(reg->value, 0, 32, value);
+		reg->valid = 1;
 	}
+	reg->dirty = 1;
 
 	return ERROR_OK;
 }
@@ -1240,7 +1236,6 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
 
 	armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
 	arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* core_type may be overridden by subtype logic */
 	armv4_5->core_type = ARMV4_5_MODE_ANY;
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 71de3b7..fa26b6a 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -650,29 +650,6 @@ static int cortex_a8_debug_entry(struct target *target)
 
 	arm_set_cpsr(armv4_5, cpsr);
 
-	i = (cpsr >> 5) & 1;	/* T */
-	i |= (cpsr >> 23) & 1;	/* J << 1 */
-	switch (i) {
-	case 0:	/* J = 0, T = 0 */
-		armv4_5->core_state = ARMV4_5_STATE_ARM;
-		break;
-	case 1:	/* J = 0, T = 1 */
-		armv4_5->core_state = ARMV4_5_STATE_THUMB;
-		break;
-	case 2:	/* J = 1, T = 0 */
-		LOG_WARNING("Jazelle state -- not handled");
-		armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
-		break;
-	case 3:	/* J = 1, T = 1 */
-		/* ThumbEE is very much like Thumb, but some of the
-		 * instructions are different.  Single stepping and
-		 * breakpoints need updating...
-		 */
-		LOG_WARNING("ThumbEE -- incomplete support");
-		armv4_5->core_state = ARM_STATE_THUMB_EE;
-		break;
-	}
-
 	/* update cache */
 	for (i = 0; i <= ARM_PC; i++)
 	{
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 659caec..e8a3e49 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -960,12 +960,6 @@ static int xscale_debug_entry(struct target *target)
 	LOG_DEBUG("target entered debug state in %s mode",
 			 arm_mode_name(armv4_5->core_mode));
 
-	if (buffer[9] & 0x20)
-		armv4_5->core_state = ARMV4_5_STATE_THUMB;
-	else
-		armv4_5->core_state = ARMV4_5_STATE_ARM;
-
-
 	/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
 	if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
 	{

commit ff810723e051ed1f86cffcb565ade6b4d1fc50c8
Author: David Brownell <dbr...@us...>
Date:   Sun Nov 22 03:38:34 2009 -0800

    ARM: define two register utilities
    
    Define arm_reg_current() ... returning handle to a given register,
    and encapsulating the current mode's register shadowing.  It's got
    one current use, for reporting the current register set to GDB.
    This will let later patches clean up much ARMV4_5_CORE_REG_MODE()
    nastiness, saving a bit of code.
    
    Define and use arm_set_cpsr() ... initially it updates the cached
    CPSR and sets up state used by arm_reg_current(), plus any SPSR
    handle.   (Later: can also set up for T and J bits.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 4768f82..ac7e488 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -347,18 +347,20 @@ static int arm720t_soft_reset_halt(struct target *target)
 	target->state = TARGET_HALTED;
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	uint32_t cpsr;
+
+	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+	cpsr &= ~0xff;
+	cpsr |= 0xd3;
+	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->cpsr->valid = 1;
+	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 	armv4_5->core_cache->reg_list[15].dirty = 1;
 	armv4_5->core_cache->reg_list[15].valid = 1;
 
-	armv4_5->core_mode = ARMV4_5_MODE_SVC;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
-
 	arm720t_disable_mmu_caches(target, 1, 1, 1);
 	arm720t->armv4_5_mmu.mmu_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 7ca807a..9580f62 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1227,18 +1227,20 @@ int arm7_9_soft_reset_halt(struct target *target)
 	register_cache_invalidate(armv4_5->core_cache);
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	uint32_t cpsr;
+
+	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+	cpsr &= ~0xff;
+	cpsr |= 0xd3;
+	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->cpsr->valid = 1;
+	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 	armv4_5->core_cache->reg_list[15].dirty = 1;
 	armv4_5->core_cache->reg_list[15].valid = 1;
 
-	armv4_5->core_mode = ARMV4_5_MODE_SVC;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
-
 	/* reset registers */
 	for (i = 0; i <= 14; i++)
 	{
@@ -1401,11 +1403,7 @@ static int arm7_9_debug_entry(struct target *target)
 	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 		cpsr |= 0x20;
 
-	buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
-	armv4_5->cpsr->dirty = 0;
-	armv4_5->cpsr->valid = 1;
-
-	armv4_5->core_mode = cpsr & 0x1f;
+	arm_set_cpsr(armv4_5, cpsr);
 
 	if (!is_arm_mode(armv4_5->core_mode))
 	{
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 9cd491f..739df3e 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -596,18 +596,20 @@ int arm920t_soft_reset_halt(struct target *target)
 	target->state = TARGET_HALTED;
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	uint32_t cpsr;
+
+	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+	cpsr &= ~0xff;
+	cpsr |= 0xd3;
+	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->cpsr->valid = 1;
+	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 	armv4_5->core_cache->reg_list[15].dirty = 1;
 	armv4_5->core_cache->reg_list[15].valid = 1;
 
-	armv4_5->core_mode = ARMV4_5_MODE_SVC;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
-
 	arm920t_disable_mmu_caches(target, 1, 1, 1);
 	arm920t->armv4_5_mmu.mmu_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 44afb2c..7ecc782 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -565,18 +565,20 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	target->state = TARGET_HALTED;
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	uint32_t cpsr;
+
+	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+	cpsr &= ~0xff;
+	cpsr |= 0xd3;
+	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
-	armv4_5->cpsr->valid = 1;
+	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 	armv4_5->core_cache->reg_list[15].dirty = 1;
 	armv4_5->core_cache->reg_list[15].valid = 1;
 
-	armv4_5->core_mode = ARMV4_5_MODE_SVC;
-	armv4_5->core_state = ARMV4_5_STATE_ARM;
-
 	arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 01d3bc3..3156c66 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -245,6 +245,10 @@ static const struct {
 	unsigned cookie;
 	enum armv4_5_mode mode;
 } arm_core_regs[] = {
+	/* IMPORTANT:  we guarantee that the first eight cached registers
+	 * correspond to r0..r7, and the fifteenth to PC, so that callers
+	 * don't need to map them.
+	 */
 	{ .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
 	{ .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
 	{ .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
@@ -255,7 +259,8 @@ static const struct {
 	{ .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
 
 	/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
-	 * them as MODE_ANY creates special cases.
+	 * them as MODE_ANY creates special cases.  (ANY means
+	 * "not mapped" elsewhere; here it's "everything but FIQ".)
 	 */
 	{ .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
 	{ .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
@@ -267,6 +272,7 @@ static const struct {
 	{ .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
 	{ .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
 
+	/* guaranteed to be at index 15 */
 	{ .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
 
 	{ .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
@@ -333,6 +339,73 @@ const int armv4_5_core_reg_map[8][17] =
 	}
 };
 
+/**
+ * Configures host-side ARM records to reflect the specified CPSR.
+ * Later, code can use arm_reg_current() to map register numbers
+ * according to how they are exposed by this mode.
+ */
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
+{
+	enum armv4_5_mode mode = cpsr & 0x1f;
+	int num;
+
+	/* NOTE:  this may be called very early, before the register
+	 * cache is set up.  We can't defend against many errors, in
+	 * particular against CPSRs that aren't valid *here* ...
+	 */
+	if (arm->cpsr) {
+		buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
+		arm->cpsr->valid = 1;
+		arm->cpsr->dirty = 0;
+	}
+
+	arm->core_mode = mode;
+
+	/* mode_to_number() warned; set up a somewhat-sane mapping */
+	num = armv4_5_mode_to_number(mode);
+	if (num < 0) {
+		mode = ARMV4_5_MODE_USR;
+		num = 0;
+	}
+
+	arm->map = &armv4_5_core_reg_map[num][0];
+	arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS)
+			? NULL
+			: arm->core_cache->reg_list + arm->map[16];
+}
+
+/**
+ * Returns handle to the register currently mapped to a given number.
+ * Someone must have called arm_set_cpsr() before.
+ *
+ * \param arm This core's state and registers are used.
+ * \param regnum From 0..15 corresponding to R0..R14 and PC.
+ *	Note that R0..R7 don't require mapping; you may access those
+ *	as the first eight entries in the register cache.  Likewise
+ *	R15 (PC) doesn't need mapping; you may also access it directly.
+ *	However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
+ *	CPSR (arm->cpsr) is also not mapped.
+ */
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
+{
+	struct reg *r;
+
+	if (regnum > 16)
+		return NULL;
+
+	r = arm->core_cache->reg_list + arm->map[regnum];
+
+	/* e.g. invalid CPSR said "secure monitor" mode on a core
+	 * that doesn't support it...
+	 */
+	if (!r) {
+		LOG_ERROR("Invalid CPSR mode");
+		r = arm->core_cache->reg_list + regnum;
+	}
+
+	return r;
+}
+
 static const uint8_t arm_gdb_dummy_fp_value[12];
 
 /**
@@ -446,10 +519,9 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 		{
 			LOG_DEBUG("changing ARM core mode to '%s'",
 					arm_mode_name(value & 0x1f));
-			armv4_5_target->core_mode = value & 0x1f;
 			armv4_5_target->write_core_reg(target, reg,
 					16, ARMV4_5_MODE_ANY, value);
-			reg->dirty = 0;
+			arm_set_cpsr(armv4_5_target, value);
 		}
 	}
 
@@ -752,14 +824,10 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
 	*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 
 	for (i = 0; i < 16; i++)
-	{
-		(*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
-	}
+		(*reg_list)[i] = arm_reg_current(armv4_5, i);
 
 	for (i = 16; i < 24; i++)
-	{
 		(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
-	}
 
 	(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 	(*reg_list)[25] = armv4_5->cpsr;
@@ -805,7 +873,6 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 	struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
 	enum armv4_5_state core_state = armv4_5->core_state;
-	enum armv4_5_mode core_mode = armv4_5->core_mode;
 	uint32_t context[17];
 	uint32_t cpsr;
 	int exit_breakpoint_size = 0;
@@ -835,6 +902,9 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 		return ERROR_FAIL;
 	}
 
+	/* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
+	 * they'll be restored later.
+	 */
 	for (i = 0; i <= 16; i++)
 	{
 		struct reg *r;
@@ -952,6 +1022,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 		}
 	}
 
+	/* restore everything we saved before (17 or 18 registers) */
 	for (i = 0; i <= 16; i++)
 	{
 		uint32_t regvalue;
@@ -964,12 +1035,11 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
 		}
 	}
-	buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
-	armv4_5->cpsr->valid = 1;
+
+	arm_set_cpsr(armv4_5, cpsr);
 	armv4_5->cpsr->dirty = 1;
 
 	armv4_5->core_state = core_state;
-	armv4_5->core_mode = core_mode;
 
 	return retval;
 }
@@ -1169,8 +1239,8 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
 	target->arch_info = armv4_5;
 
 	armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
+	arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
 	armv4_5->core_state = ARMV4_5_STATE_ARM;
-	armv4_5->core_mode = ARMV4_5_MODE_USR;
 
 	/* core_type may be overridden by subtype logic */
 	armv4_5->core_type = ARMV4_5_MODE_ANY;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5bce30b..a9599c8 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -85,6 +85,11 @@ struct arm
 	/** Handle to the CPSR; valid in all core modes. */
 	struct reg *cpsr;
 
+	/** Handle to the SPSR; valid only in core modes with an SPSR. */
+	struct reg *spsr;
+
+	const int *map;
+
 	/**
 	 * Indicates what registers are in the ARM state core register set.
 	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
@@ -161,6 +166,9 @@ int arm_checksum_memory(struct target *target,
 int arm_blank_check_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *blank);
 
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;
 
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 2463209..71de3b7 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -648,7 +648,7 @@ static int cortex_a8_debug_entry(struct target *target)
 	dap_ap_select(swjdp, swjdp_debugap);
 	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
-	armv4_5->core_mode = cpsr & 0x1F;
+	arm_set_cpsr(armv4_5, cpsr);
 
 	i = (cpsr >> 5) & 1;	/* T */
 	i |= (cpsr >> 23) & 1;	/* J << 1 */
@@ -674,11 +674,6 @@ static int cortex_a8_debug_entry(struct target *target)
 	}
 
 	/* update cache */
-	reg = armv4_5->cpsr;
-	buf_set_u32(reg->value, 0, 32, cpsr);
-	reg->valid = 1;
-	reg->dirty = 0;
-
 	for (i = 0; i <= ARM_PC; i++)
 	{
 		reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 3ed7bf0..659caec 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -948,12 +948,9 @@ static int xscale_debug_entry(struct target *target)
 		LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
 	}
 
-	buf_set_u32(armv4_5->cpsr->value, 0, 32, buffer[9]);
-	armv4_5->cpsr->dirty = 1;
-	armv4_5->cpsr->valid = 1;
+	arm_set_cpsr(armv4_5, buffer[9]);
 	LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 
-	armv4_5->core_mode = buffer[9] & 0x1f;
 	if (!is_arm_mode(armv4_5->core_mode))
 	{
 		target->state = TARGET_UNKNOWN;

commit 5706fd7860ea01c591ecf74880a5a5e04e6df22e
Author: David Brownell <dbr...@us...>
Date:   Sun Nov 22 03:37:21 2009 -0800

    ARM: simplify CPSR handling
    
    Stash a pointer to the CPSR in the "struct arm", to help get rid
    of the (common) references to its index in the register cache.
    
    This removes almost all references to CPSR offsets outside of the
    toplevel ARM code ... except a pair related to the current ARM11
    "simulator" logic (which should be removable soonish).
    
    This is a net minor code shrink of a few hundred bytes of object
    code, and also makes the code more readable.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index a6c7cc7..4768f82 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -240,7 +240,7 @@ static int arm720t_arch_state(struct target *target)
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 			 state[arm720t->armv4_5_mmu.mmu_enabled],
 			 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
@@ -347,9 +347,9 @@ static int arm720t_soft_reset_halt(struct target *target)
 	target->state = TARGET_HALTED;
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	armv4_5->cpsr->dirty = 1;
+	armv4_5->cpsr->valid = 1;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 3a32764..7ca807a 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1227,9 +1227,9 @@ int arm7_9_soft_reset_halt(struct target *target)
 	register_cache_invalidate(armv4_5->core_cache);
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	armv4_5->cpsr->dirty = 1;
+	armv4_5->cpsr->valid = 1;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
@@ -1401,9 +1401,9 @@ static int arm7_9_debug_entry(struct target *target)
 	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 		cpsr |= 0x20;
 
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+	buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
+	armv4_5->cpsr->dirty = 0;
+	armv4_5->cpsr->valid = 1;
 
 	armv4_5->core_mode = cpsr & 0x1f;
 
@@ -1520,7 +1520,8 @@ int arm7_9_full_context(struct target *target)
 			uint32_t tmp_cpsr;
 
 			/* change processor mode (and mask T bit) */
-			tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+			tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
+					& 0xe0;
 			tmp_cpsr |= armv4_5_number_to_mode(i);
 			tmp_cpsr &= ~0x20;
 			arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -1551,7 +1552,9 @@ int arm7_9_full_context(struct target *target)
 	}
 
 	/* restore processor mode (mask T bit) */
-	arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+	arm7_9->write_xpsr_im8(target,
+			buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
+			0, 0);
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
@@ -1645,7 +1648,8 @@ int arm7_9_restore_context(struct target *target)
 				uint32_t tmp_cpsr;
 
 				/* change processor mode (mask T bit) */
-				tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+				tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
+						0, 8) & 0xe0;
 				tmp_cpsr |= armv4_5_number_to_mode(i);
 				tmp_cpsr &= ~0x20;
 				arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -1687,24 +1691,27 @@ int arm7_9_restore_context(struct target *target)
 		}
 	}
 
-	if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
+	if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
 	{
 		/* restore processor mode (mask T bit) */
 		uint32_t tmp_cpsr;
 
-		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+		tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
 		tmp_cpsr |= armv4_5_number_to_mode(i);
 		tmp_cpsr &= ~0x20;
 		LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
 	}
-	else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
+	else if (armv4_5->cpsr->dirty)
 	{
 		/* CPSR has been changed, full restore necessary (mask T bit) */
-		LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-		arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
-		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
-		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+		LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+				buf_get_u32(armv4_5->cpsr->value, 0, 32));
+		arm7_9->write_xpsr(target,
+				buf_get_u32(armv4_5->cpsr->value, 0, 32)
+					& ~0x20, 0);
+		armv4_5->cpsr->dirty = 0;
+		armv4_5->cpsr->valid = 1;
 	}
 
 	/* restore PC */
@@ -2106,7 +2113,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
 		uint32_t tmp_cpsr;
 
 		/* change processor mode (mask T bit) */
-		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+		tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
 		tmp_cpsr |= mode;
 		tmp_cpsr &= ~0x20;
 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -2140,7 +2147,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
 			&& (mode != armv4_5->core_mode)
 			&& (areg->mode != ARMV4_5_MODE_ANY))	{
 		/* restore processor mode (mask T bit) */
-		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+		arm7_9->write_xpsr_im8(target,
+				buf_get_u32(armv4_5->cpsr->value, 0, 8)
+					& ~0x20, 0, 0);
 	}
 
 	return ERROR_OK;
@@ -2165,7 +2174,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
 		uint32_t tmp_cpsr;
 
 		/* change processor mode (mask T bit) */
-		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+		tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
 		tmp_cpsr |= mode;
 		tmp_cpsr &= ~0x20;
 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -2199,7 +2208,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
 			&& (mode != armv4_5->core_mode)
 			&& (areg->mode != ARMV4_5_MODE_ANY))	{
 		/* restore processor mode (mask T bit) */
-		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+		arm7_9->write_xpsr_im8(target,
+				buf_get_u32(armv4_5->cpsr->value, 0, 8)
+					& ~0x20, 0, 0);
 	}
 
 	return jtag_execute_queue();
@@ -2372,7 +2383,9 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
 	{
 		LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
-		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+		arm7_9->write_xpsr_im8(target,
+				buf_get_u32(armv4_5->cpsr->value, 0, 8)
+					& ~0x20, 0, 0);
 
 		return ERROR_TARGET_DATA_ABORT;
 	}
@@ -2555,7 +2568,9 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 	{
 		LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
-		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+		arm7_9->write_xpsr_im8(target,
+				buf_get_u32(armv4_5->cpsr->value, 0, 8)
+					& ~0x20, 0, 0);
 
 		return ERROR_TARGET_DATA_ABORT;
 	}
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 29f7917..9cd491f 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -452,7 +452,7 @@ int arm920t_arch_state(struct target *target)
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 			 state[arm920t->armv4_5_mmu.mmu_enabled],
 			 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
@@ -596,9 +596,9 @@ int arm920t_soft_reset_halt(struct target *target)
 	target->state = TARGET_HALTED;
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	armv4_5->cpsr->dirty = 1;
+	armv4_5->cpsr->valid = 1;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 27eb752..44afb2c 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -510,7 +510,7 @@ int arm926ejs_arch_state(struct target *target)
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
 			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 			 state[arm926ejs->armv4_5_mmu.mmu_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
@@ -565,9 +565,9 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	target->state = TARGET_HALTED;
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+	buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+	armv4_5->cpsr->dirty = 1;
+	armv4_5->cpsr->valid = 1;
 
 	/* start fetching from 0x0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 31163b4..23cc556 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -821,7 +821,7 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
 {
 	struct arm *armv4_5 = (struct arm *)sim->user_data;
 
-	return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
+	return buf_get_u32(armv4_5->cpsr->value, pos, bits);
 }
 
 static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 71c7299..01d3bc3 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -36,6 +36,17 @@
 #include "register.h"
 
 
+/* offsets into armv4_5 core register cache */
+enum {
+//	ARMV4_5_CPSR = 31,
+	ARMV4_5_SPSR_FIQ = 32,
+	ARMV4_5_SPSR_IRQ = 33,
+	ARMV4_5_SPSR_SVC = 34,
+	ARMV4_5_SPSR_ABT = 35,
+	ARMV4_5_SPSR_UND = 36,
+	ARM_SPSR_MON = 39,
+};
+
 static const uint8_t arm_usr_indices[17] = {
 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
 };
@@ -214,7 +225,7 @@ char* armv4_5_state_strings[] =
  *
  * NOTE:  offsets in this table are coupled to the arm_mode_data
  * table above, the armv4_5_core_reg_map array below, and also to
- * the ARMV4_5_*PSR* symols.
+ * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
  */
 static const struct {
 	/* The name is used for e.g. the "regs" command. */
@@ -401,7 +412,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 	reg->dirty = 1;
 	reg->valid = 1;
 
-	if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
+	if (reg == armv4_5_target->cpsr)
 	{
 		/* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */
 		if (value & 0x20)
@@ -493,6 +504,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		cache->num_regs++;
 	}
 
+	armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
 	armv4_5_common->core_cache = cache;
 	return cache;
 }
@@ -511,7 +523,7 @@ int armv4_5_arch_state(struct target *target)
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 
 	return ERROR_OK;
@@ -750,7 +762,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
 	}
 
 	(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
-	(*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
+	(*reg_list)[25] = armv4_5->cpsr;
 
 	return ERROR_OK;
 }
@@ -834,7 +846,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 					armv4_5_algorithm_info->core_mode);
 		context[i] = buf_get_u32(r->value, 0, 32);
 	}
-	cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
+	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 
 	for (i = 0; i < num_mem_params; i++)
 	{
@@ -878,10 +890,12 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 
 	if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
 	{
-		LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
-		buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
-		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+		LOG_DEBUG("setting core_mode: 0x%2.2x",
+				armv4_5_algorithm_info->core_mode);
+		buf_set_u32(armv4_5->cpsr->value, 0, 5,
+				armv4_5_algorithm_info->core_mode);
+		armv4_5->cpsr->dirty = 1;
+		armv4_5->cpsr->valid = 1;
 	}
 
 	/* terminate using a hardware or (ARMv5+) software breakpoint */
@@ -950,9 +964,9 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
 		}
 	}
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+	buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
+	armv4_5->cpsr->valid = 1;
+	armv4_5->cpsr->dirty = 1;
 
 	armv4_5->core_state = core_state;
 	armv4_5->core_mode = core_mode;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index c8fc558..5bce30b 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -62,17 +62,8 @@ extern const int armv4_5_core_reg_map[8][17];
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
 
-/* offsets into armv4_5 core register cache */
-enum
-{
-	ARMV4_5_CPSR = 31,
-	ARMV4_5_SPSR_FIQ = 32,
-	ARMV4_5_SPSR_IRQ = 33,
-	ARMV4_5_SPSR_SVC = 34,
-	ARMV4_5_SPSR_ABT = 35,
-	ARMV4_5_SPSR_UND = 36,
-	ARM_SPSR_MON = 39,
-};
+/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
+enum { ARMV4_5_CPSR = 31, };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
@@ -91,6 +82,9 @@ struct arm
 	int common_magic;
 	struct reg_cache *core_cache;
 
+	/** Handle to the CPSR; valid in all core modes. */
+	struct reg *cpsr;
+
 	/**
 	 * Indicates what registers are in the ARM state core register set.
 	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index ea883c1..63f95b8 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -74,8 +74,7 @@ int armv7a_arch_state(struct target *target)
 		 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 				target->debug_reason)->name,
 		 arm_mode_name(armv4_5->core_mode),
-		 buf_get_u32(armv4_5->core_cache
-				->reg_list[ARMV4_5_CPSR].value, 0, 32),
+		 buf_get_u32(armv4_5->cpsr->value, 0, 32),
 		 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 		 state[armv7a->armv4_5_mmu.mmu_enabled],
 		 state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 635cd40..51f7b45 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -30,16 +30,6 @@ enum
 	ARM_CPSR = 16
 }
 ;
-/* offsets into armv4_5 core register cache */
-enum
-{
-	ARMV7A_CPSR = 31,
-	ARMV7A_SPSR_FIQ = 32,
-	ARMV7A_SPSR_IRQ = 33,
-	ARMV7A_SPSR_SVC = 34,
-	ARMV7A_SPSR_ABT = 35,
-	ARMV7A_SPSR_UND = 36
-};
 
 #define ARMV7_COMMON_MAGIC 0x0A450999
 
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index c6a46c5..2463209 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -674,7 +674,7 @@ static int cortex_a8_debug_entry(struct target *target)
 	}
 
 	/* update cache */
-	reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
+	reg = armv4_5->cpsr;
 	buf_set_u32(reg->value, 0, 32, cpsr);
 	reg->valid = 1;
 	reg->dirty = 0;
@@ -879,7 +879,7 @@ static int cortex_a8_restore_context(struct target *target)
 		for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
 			struct arm_reg *reg;
 
-			if (!r->dirty || i == ARMV4_5_CPSR)
+			if (!r->dirty || r == armv7a->armv4_5_common.cpsr)
 				continue;
 			reg = r->arch_info;
 
@@ -915,7 +915,7 @@ static int cortex_a8_restore_context(struct target *target)
 	} while (flushed);
 
 	/* now flush CPSR if needed ... */
-	r = cache->reg_list + ARMV4_5_CPSR;
+	r = armv7a->armv4_5_common.cpsr;
 	if (flush_cpsr || r->dirty) {
 		value = buf_get_u32(r->value, 0, 32);
 		cortex_a8_dap_write_coreregister_u32(target, value, 16);
@@ -1027,7 +1027,6 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
 	uint32_t value;
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
 	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
@@ -1043,7 +1042,7 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr_r = cache->reg_list + ARMV4_5_CPSR;
+			cpsr_r = armv4_5->cpsr;
 			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
 			cortex_a8_write_core_reg(target, cpsr_r,
 					16, ARMV4_5_MODE_ANY, mode);
@@ -1083,7 +1082,6 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
 {
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
 	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
@@ -1099,7 +1097,7 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr_r = cache->reg_list + ARMV4_5_CPSR;
+			cpsr_r = armv4_5->cpsr;
 			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
 			cortex_a8_write_core_reg(target, cpsr_r,
 					16, ARMV4_5_MODE_ANY, mode);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index c908fd7..3ed7bf0 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -858,7 +858,7 @@ static int xscale_arch_state(struct target *target)
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 			 state[xscale->armv4_5_mmu.mmu_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
@@ -948,9 +948,9 @@ static int xscale_debug_entry(struct target *target)
 		LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
 	}
 
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+	buf_set_u32(armv4_5->cpsr->value, 0, 32, buffer[9]);
+	armv4_5->cpsr->dirty = 1;
+	armv4_5->cpsr->valid = 1;
 	LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 
 	armv4_5->core_mode = buffer[9] & 0x1f;
@@ -1260,8 +1260,10 @@ static int xscale_resume(struct target *target, int current,
 				xscale_send_u32(target, 0x30);
 
 			/* send CPSR */
-			xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-			LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+			xscale_send_u32(target,
+				buf_get_u32(armv4_5->cpsr->value, 0, 32));
+			LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+				buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
 			for (i = 7; i >= 0; i--)
 			{
@@ -1303,8 +1305,9 @@ static int xscale_resume(struct target *target, int current,
 		xscale_send_u32(target, 0x30);
 
 	/* send CPSR */
-	xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+	xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
+	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+			buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
 	for (i = 7; i >= 0; i--)
 	{
@@ -1381,9 +1384,12 @@ static int xscale_step_inner(struct target *target, int current,
 			return retval;
 
 	/* send CPSR */
-	if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
+	retval = xscale_send_u32(target,
+			buf_get_u32(armv4_5->cpsr->value, 0, 32));
+	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+			buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
 	for (i = 7; i >= 0; i--)
 	{

commit 60a2d85af1afbc207ae5fb9dafdbe4c8b49ad5bb
Author: David Brownell <dbr...@us...>
Date:   Sun Nov 22 03:36:24 2009 -0800

    ARM11: remove disabled register hooks
    
    Minor cleanup of ARM11 register handling:  remove disabled
    register hooks.  This should all be handled by shared code,
    and this stuff is just clutter.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 58b5d54..9c42705 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -115,52 +115,8 @@ static const struct arm11_reg_defs arm11_reg_defs[] =
 	{"lr",	14,	14,	ARM11_REGISTER_CORE},
 	{"pc",	15,	15,	ARM11_REGISTER_CORE},
 
-#if ARM11_REGCACHE_FREGS
-	{"f0",	0,	16,	ARM11_REGISTER_FX},
-	{"f1",	1,	17,	ARM11_REGISTER_FX},
-	{"f2",	2,	18,	ARM11_REGISTER_FX},
-	{"f3",	3,	19,	ARM11_REGISTER_FX},
-	{"f4",	4,	20,	ARM11_REGISTER_FX},
-	{"f5",	5,	21,	ARM11_REGISTER_FX},
-	{"f6",	6,	22,	ARM11_REGISTER_FX},
-	{"f7",	7,	23,	ARM11_REGISTER_FX},
-	{"fps",	0,	24,	ARM11_REGISTER_FPS},
-#endif
-
 	{"cpsr",	0,	25,	ARM11_REGISTER_CPSR},
 
-#if ARM11_REGCACHE_MODEREGS
-	{"r8_fiq",	8,	-1,	ARM11_REGISTER_FIQ},
-	{"r9_fiq",	9,	-1,	ARM11_REGISTER_FIQ},
-	{"r10_fiq",	10,	-1,	ARM11_REGISTER_FIQ},
-	{"r11_fiq",	11,	-1,	ARM11_REGISTER_FIQ},
-	{"r12_fiq",	12,	-1,	ARM11_REGISTER_FIQ},
-	{"r13_fiq",	13,	-1,	ARM11_REGISTER_FIQ},
-	{"r14_fiq",	14,	-1,	ARM11_REGISTER_FIQ},
-	{"spsr_fiq", 0,	-1,	ARM11_REGISTER_SPSR_FIQ},
-
-	{"r13_svc",	13,	-1,	ARM11_REGISTER_SVC},
-	{"r14_svc",	14,	-1,	ARM11_REGISTER_SVC},
-	{"spsr_svc", 0,	-1,	ARM11_REGISTER_SPSR_SVC},
-
-	{"r13_abt",	13,	-1,	ARM11_REGISTER_ABT},
-	{"r14_abt",	14,	-1,	ARM11_REGISTER_ABT},
-	{"spsr_abt", 0,	-1,	ARM11_REGISTER_SPSR_ABT},
-
-	{"r13_irq",	13,	-1,	ARM11_REGISTER_IRQ},
-	{"r14_irq",	14,	-1,	ARM11_REGISTER_IRQ},
-	{"spsr_irq", 0,	-1,	ARM11_REGISTER_SPSR_IRQ},
-
-	{"r13_und",	13,	-1,	ARM11_REGISTER_UND},
-	{"r14_und",	14,	-1,	ARM11_REGISTER_UND},
-	{"spsr_und", 0,	-1,	ARM11_REGISTER_SPSR_UND},
-
-	/* ARM1176 only */
-	{"r13_mon",	13,	-1,	ARM11_REGISTER_MON},
-	{"r14_mon",	14,	-1,	ARM11_REGISTER_MON},
-	{"spsr_mon", 0,	-1,	ARM11_REGISTER_SPSR_MON},
-#endif
-
 	/* Debug Registers */
 	{"dscr",	0,	-1,	ARM11_REGISTER_DSCR},
 	{"wdtr",	0,	-1,	ARM11_REGISTER_WDTR},
@@ -191,52 +147,8 @@ enum arm11_regcache_ids
 	ARM11_RC_R15,
 	ARM11_RC_PC			= ARM11_RC_R15,
 
-#if ARM11_REGCACHE_FREGS
-	ARM11_RC_F0,
-	ARM11_RC_FX			= ARM11_RC_F0,
-	ARM11_RC_F1,
-	ARM11_RC_F2,
-	ARM11_RC_F3,
-	ARM11_RC_F4,
-	ARM11_RC_F5,
-	ARM11_RC_F6,
-	ARM11_RC_F7,
-	ARM11_RC_FPS,
-#endif
-
 	ARM11_RC_CPSR,
 
-#if ARM11_REGCACHE_MODEREGS
-	ARM11_RC_R8_FIQ,
-	ARM11_RC_R9_FIQ,
-	ARM11_RC_R10_FIQ,
-	ARM11_RC_R11_FIQ,
-	ARM11_RC_R12_FIQ,
-	ARM11_RC_R13_FIQ,
-	ARM11_RC_R14_FIQ,
-	ARM11_RC_SPSR_FIQ,
-
-	ARM11_RC_R13_SVC,
-	ARM11_RC_R14_SVC,
-	ARM11_RC_SPSR_SVC,
-
-	ARM11_RC_R13_ABT,
-	ARM11_RC_R14_ABT,
-	ARM11_RC_SPSR_ABT,
-
-	ARM11_RC_R13_IRQ,
-	ARM11_RC_R14_IRQ,
-	ARM11_RC_SPSR_IRQ,
-
-	ARM11_RC_R13_UND,
-	ARM11_RC_R14_UND,
-	ARM11_RC_SPSR_UND,
-
-	ARM11_RC_R13_MON,
-	ARM11_RC_R14_MON,
-	ARM11_RC_SPSR_MON,
-#endif
-
 	ARM11_RC_DSCR,
 	ARM11_RC_WDTR,
 	ARM11_RC_RDTR,
@@ -244,6 +156,7 @@ enum arm11_regcache_ids
 	ARM11_RC_MAX,
 };
 
+/* GDB expects ARMs to give R0..R15, CPSR, and 7 FPA dummies */
 #define ARM11_GDB_REGISTER_COUNT	26
 
 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 809c23f..79f4b6b 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -37,12 +37,9 @@
 #define ZU		"%Iu"
 #endif
 
-#define ARM11_REGCACHE_MODEREGS		0
-#define ARM11_REGCACHE_FREGS		0
 
-#define ARM11_REGCACHE_COUNT		(20 +					\
-					 23 * ARM11_REGCACHE_MODEREGS +			\
-					  9 * ARM11_REGCACHE_FREGS)
+/* TEMPORARY -- till we switch to the shared infrastructure */
+#define ARM11_REGCACHE_COUNT		20
 
 #define ARM11_TAP_DEFAULT			TAP_INVALID
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11.c         |   89 +--------------------
 src/target/arm11.h         |    7 +-
 src/target/arm720t.c       |   15 ++--
 src/target/arm7_9_common.c |   95 +++++++++++++--------
 src/target/arm920t.c       |   15 ++--
 src/target/arm926ejs.c     |   15 ++--
 src/target/arm_simulator.c |    2 +-
 src/target/armv4_5.c       |  193 +++++++++++++++++++++++++++++++-------------
 src/target/armv4_5.h       |   24 +++---
 src/target/armv7a.c        |    3 +-
 src/target/armv7a.h        |   10 ---
 src/target/cortex_a8.c     |   40 +--------
 src/target/xscale.c        |   31 +++----
 13 files changed, 256 insertions(+), 283 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-513-gb58239e

From: Zach W. <zw...@us...> - 2009-11-21 19:38:26

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  b58239e4c03c440ac89b36c9de917224a8439332 (commit)
       via  c46c2d77e63264a9f0187a477b77032d0ce6fcfa (commit)
      from  425e43d9d1f09a4de86eae89c91924ec98ef2de0 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit b58239e4c03c440ac89b36c9de917224a8439332
Author: Zachary T Welch <zw...@su...>
Date:   Sat Nov 21 10:20:56 2009 -0800

    jtag: remove useless forward declarations
    
    Removes some more useless forward declarations from a few JTAG drivers.
    Moves interface and bit-bang structure defitions below their callbacks.

diff --git a/src/jtag/arm-jtag-ew.c b/src/jtag/arm-jtag-ew.c
index 18b353a..46dacc6 100644
--- a/src/jtag/arm-jtag-ew.c
+++ b/src/jtag/arm-jtag-ew.c
@@ -55,14 +55,6 @@
 static uint8_t usb_in_buffer[ARMJTAGEW_IN_BUFFER_SIZE];
 static uint8_t usb_out_buffer[ARMJTAGEW_OUT_BUFFER_SIZE];
 
-/* External interface functions */
-static int armjtagew_execute_queue(void);
-static int armjtagew_speed(int speed);
-static int armjtagew_khz(int khz, int *jtag_speed);
-static int armjtagew_register_commands(struct command_context *cmd_ctx);
-static int armjtagew_init(void);
-static int armjtagew_quit(void);
-
 /* Queue command functions */
 static void armjtagew_end_state(tap_state_t state);
 static void armjtagew_state_move(void);
@@ -105,18 +97,6 @@ static struct armjtagew* armjtagew_handle;
 /***************************************************************************/
 /* External interface implementation */
 
-struct jtag_interface armjtagew_interface =
-{
-	.name = "arm-jtag-ew",
-	.execute_queue = armjtagew_execute_queue,
-	.speed = armjtagew_speed,
-	.khz = armjtagew_khz,
-	.register_commands = armjtagew_register_commands,
-	.init = armjtagew_init,
-	.quit = armjtagew_quit
-};
-
-
 static int armjtagew_execute_queue(void)
 {
 	struct jtag_command *cmd = jtag_command_queue;
@@ -529,6 +509,16 @@ static int armjtagew_register_commands(struct command_context *cmd_ctx)
 	return ERROR_OK;
 }
 
+struct jtag_interface armjtagew_interface = {
+		.name = "arm-jtag-ew",
+		.execute_queue = &armjtagew_execute_queue,
+		.speed = &armjtagew_speed,
+		.khz = &armjtagew_khz,
+		.register_commands = &armjtagew_register_commands,
+		.init = &armjtagew_init,
+		.quit = &armjtagew_quit,
+	};
+
 /***************************************************************************/
 /* ARM-JTAG-EW tap functions */
 
diff --git a/src/jtag/dummy.c b/src/jtag/dummy.c
index 324ea7e..0516790 100644
--- a/src/jtag/dummy.c
+++ b/src/jtag/dummy.c
@@ -35,45 +35,6 @@ static int clock_count;         /* count clocks in any stable state, only stable
 static uint32_t dummy_data;
 
 
-static int dummy_speed(int speed);
-static int dummy_register_commands(struct command_context *cmd_ctx);
-static int dummy_init(void);
-static int dummy_quit(void);
-static int dummy_khz(int khz, int *jtag_speed);
-static int dummy_speed_div(int speed, int *khz);
-
-
-/* The dummy driver is used to easily check the code path
- * where the target is unresponsive.
- */
-struct jtag_interface dummy_interface =
-{
-	.name = "dummy",
-
-	.execute_queue = bitbang_execute_queue,
-
-	.speed = dummy_speed,
-	.register_commands = dummy_register_commands,
-	.khz = dummy_khz,
-	.speed_div = dummy_speed_div,
-
-	.init = dummy_init,
-	.quit = dummy_quit,
-};
-
-static int dummy_read(void);
-static void dummy_write(int tck, int tms, int tdi);
-static void dummy_reset(int trst, int srst);
-static void dummy_led(int on);
-
-static struct bitbang_interface dummy_bitbang =
-{
-	.read = dummy_read,
-	.write = dummy_write,
-	.reset = dummy_reset,
-	.blink = dummy_led
-};
-
 static int dummy_read(void)
 {
 	int data = 1 & dummy_data;
@@ -129,6 +90,18 @@ static void dummy_reset(int trst, int srst)
 	LOG_DEBUG("reset to: %s", tap_state_name(dummy_state));
 }
 
+static void dummy_led(int on)
+{
+}
+
+static struct bitbang_interface dummy_bitbang = {
+		.read = &dummy_read,
+		.write = &dummy_write,
+		.reset = &dummy_reset,
+		.blink = &dummy_led,
+	};
+
+
 static int dummy_khz(int khz, int *jtag_speed)
 {
 	if (khz == 0)
@@ -178,7 +151,19 @@ static int dummy_quit(void)
 	return ERROR_OK;
 }
 
-static void dummy_led(int on)
-{
-}
+/* The dummy driver is used to easily check the code path
+ * where the target is unresponsive.
+ */
+struct jtag_interface dummy_interface = {
+		.name = "dummy",
+
+		.execute_queue = &bitbang_execute_queue,
+
+		.speed = &dummy_speed,
+		.register_commands = &dummy_register_commands,
+		.khz = &dummy_khz,
+		.speed_div = &dummy_speed_div,
 
+		.init = &dummy_init,
+		.quit = &dummy_quit,
+	};
diff --git a/src/jtag/jlink.c b/src/jtag/jlink.c
index dbbddb8..ebc9acd 100644
--- a/src/jtag/jlink.c
+++ b/src/jtag/jlink.c
@@ -82,15 +82,6 @@ static uint8_t usb_emu_result_buffer[JLINK_EMU_RESULT_BUFFER_SIZE];
 /* max speed 12MHz v5.0 jlink */
 #define JLINK_MAX_SPEED 12000
 
-/* External interface functions */
-static int jlink_execute_queue(void);
-static int jlink_speed(int speed);
-static int jlink_speed_div(int speed, int* khz);
-static int jlink_khz(int khz, int *jtag_speed);
-static int jlink_register_commands(struct command_context *cmd_ctx);
-static int jlink_init(void);
-static int jlink_quit(void);
-
 /* Queue command functions */
 static void jlink_end_state(tap_state_t state);
 static void jlink_state_move(void);
@@ -134,18 +125,6 @@ static struct jlink* jlink_handle;
 /***************************************************************************/
 /* External interface implementation */
 
-struct jtag_interface jlink_interface =
-{
-	.name = "jlink",
-	.execute_queue = jlink_execute_queue,
-	.speed = jlink_speed,
-	.speed_div = jlink_speed_div,
-	.khz = jlink_khz,
-	.register_commands = jlink_register_commands,
-	.init = jlink_init,
-	.quit = jlink_quit
-};
-
 static void jlink_execute_runtest(struct jtag_command *cmd)
 {
 	DEBUG_JTAG_IO("runtest %i cycles, end in %i",
@@ -661,6 +640,17 @@ static int jlink_register_commands(struct command_context *cmd_ctx)
 	return ERROR_OK;
 }
 
+struct jtag_interface jlink_interface = {
+		.name = "jlink",
+		.execute_queue = &jlink_execute_queue,
+		.speed = &jlink_speed,
+		.speed_div = &jlink_speed_div,
+		.khz = &jlink_khz,
+		.register_commands = &jlink_register_commands,
+		.init = &jlink_init,
+		.quit = &jlink_quit,
+	};
+
 /***************************************************************************/
 /* J-Link tap functions */
 
diff --git a/src/jtag/presto.c b/src/jtag/presto.c
index 1d6bc1d..437e2c0 100644
--- a/src/jtag/presto.c
+++ b/src/jtag/presto.c
@@ -39,42 +39,6 @@
 #error "BUG: either FTD2XX and LIBFTDI has to be used"
 #endif
 
-static int presto_jtag_speed(int speed);
-static int presto_jtag_khz(int khz, int *jtag_speed);
-static int presto_jtag_speed_div(int speed, int *khz);
-static int presto_jtag_register_commands(struct command_context *cmd_ctx);
-static int presto_jtag_init(void);
-static int presto_jtag_quit(void);
-
-struct jtag_interface presto_interface =
-{
-	.name = "presto",
-	.execute_queue = bitq_execute_queue,
-	.speed = presto_jtag_speed,
-	.khz = presto_jtag_khz,
-	.speed_div = presto_jtag_speed_div,
-	.register_commands = presto_jtag_register_commands,
-	.init = presto_jtag_init,
-	.quit = presto_jtag_quit,
-};
-
-static int presto_bitq_out(int tms, int tdi, int tdo_req);
-static int presto_bitq_flush(void);
-static int presto_bitq_sleep(unsigned long us);
-static int presto_bitq_reset(int trst, int srst);
-static int presto_bitq_in_rdy(void);
-static int presto_bitq_in(void);
-
-static struct bitq_interface presto_bitq =
-{
-	.out = presto_bitq_out,
-	.flush = presto_bitq_flush,
-	.sleep = presto_bitq_sleep,
-	.reset = presto_bitq_reset,
-	.in_rdy = presto_bitq_in_rdy,
-	.in = presto_bitq_in,
-};
-
 /* -------------------------------------------------------------------------- */
 
 #define FT_DEVICE_NAME_LEN 64
@@ -699,6 +663,15 @@ static int presto_bitq_reset(int trst, int srst)
 	return 0;
 }
 
+static struct bitq_interface presto_bitq = {
+		.out = &presto_bitq_out,
+		.flush = &presto_bitq_flush,
+		.sleep = &presto_bitq_sleep,
+		.reset = &presto_bitq_reset,
+		.in_rdy = &presto_bitq_in_rdy,
+		.in = &presto_bitq_in,
+	};
+
 /* -------------------------------------------------------------------------- */
 
 static int presto_jtag_khz(int khz, int *jtag_speed)
@@ -807,3 +780,14 @@ static int presto_jtag_quit(void)
 
 	return ERROR_OK;
 }
+
+struct jtag_interface presto_interface = {
+		.name = "presto",
+		.execute_queue = &bitq_execute_queue,
+		.speed = &presto_jtag_speed,
+		.khz = &presto_jtag_khz,
+		.speed_div = &presto_jtag_speed_div,
+		.register_commands = &presto_jtag_register_commands,
+		.init = &presto_jtag_init,
+		.quit = &presto_jtag_quit,
+	};
diff --git a/src/jtag/usbprog.c b/src/jtag/usbprog.c
index 10dfe06..e8c0ead 100644
--- a/src/jtag/usbprog.c
+++ b/src/jtag/usbprog.c
@@ -49,28 +49,12 @@
 #define TCK_BIT			2
 #define TMS_BIT			1
 
-static int usbprog_execute_queue(void);
-static int usbprog_speed(int speed);
-static int usbprog_register_commands(struct command_context *cmd_ctx);
-static int usbprog_init(void);
-static int usbprog_quit(void);
-
 static void usbprog_end_state(tap_state_t state);
 static void usbprog_state_move(void);
 static void usbprog_path_move(struct pathmove_command *cmd);
 static void usbprog_runtest(int num_cycles);
 static void usbprog_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size);
 
-struct jtag_interface usbprog_interface =
-{
-	.name = "usbprog",
-	.execute_queue = usbprog_execute_queue,
-	.speed = usbprog_speed,
-	.register_commands = usbprog_register_commands,
-	.init = usbprog_init,
-	.quit = usbprog_quit
-};
-
 #define UNKOWN_COMMAND	0x00
 #define PORT_DIRECTION	0x01
 #define PORT_SET		0x02
@@ -120,11 +104,6 @@ static int usbprog_speed(int speed)
 	return ERROR_OK;
 }
 
-static int usbprog_register_commands(struct command_context *cmd_ctx)
-{
-	return ERROR_OK;
-}
-
 static int usbprog_execute_queue(void)
 {
 	struct jtag_command *cmd = jtag_command_queue; /* currently processed command */
@@ -688,3 +667,11 @@ static void usbprog_jtag_tms_send(struct usbprog_jtag *usbprog_jtag)
 		tms_chain_index = 0;
 	}
 }
+
+struct jtag_interface usbprog_interface = {
+		.name = "usbprog",
+		.execute_queue = &usbprog_execute_queue,
+		.speed = &usbprog_speed,
+		.init = &usbprog_init,
+		.quit = &usbprog_quit
+	};

commit c46c2d77e63264a9f0187a477b77032d0ce6fcfa
Author: Zachary T Welch <zw...@su...>
Date:   Sat Nov 21 10:19:47 2009 -0800

    allow jtag interfaces to lack commands
    
    Allow JTAG interface drivers to skip registering an register_commands
    callback when it will just be empty.

diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 1266cd7..7307f64 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -636,9 +636,12 @@ COMMAND_HANDLER(handle_interface_command)
 		if (strcmp(CMD_ARGV[0], jtag_interfaces[i]->name) != 0)
 			continue;
 
-		int retval = jtag_interfaces[i]->register_commands(CMD_CTX);
-		if (ERROR_OK != retval)
+		if (NULL != jtag_interfaces[i]->register_commands)
+		{
+			int retval = jtag_interfaces[i]->register_commands(CMD_CTX);
+			if (ERROR_OK != retval)
 				return retval;
+		}
 
 		jtag_interface = jtag_interfaces[i];
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/arm-jtag-ew.c |   30 +++++++--------------
 src/jtag/dummy.c       |   69 ++++++++++++++++++-----------------------------
 src/jtag/jlink.c       |   32 +++++++--------------
 src/jtag/presto.c      |   56 ++++++++++++++-------------------------
 src/jtag/tcl.c         |    7 +++-
 src/jtag/usbprog.c     |   29 +++++--------------
 6 files changed, 81 insertions(+), 142 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-511-g425e43d

From: David B. <dbr...@us...> - 2009-11-21 18:30:37

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  425e43d9d1f09a4de86eae89c91924ec98ef2de0 (commit)
      from  69c751956293e822faa6cf844f2864d81c36a578 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 425e43d9d1f09a4de86eae89c91924ec98ef2de0
Author: Andreas Fritiofson <and...@gm...>
Date:   Sat Nov 21 09:30:09 2009 -0800

    show script search dirs in debug log
    
    Add this to ease debugging why the standard scripts aren't
    found on the default script search path in some build/install
    enviroments. Especially on Windows it's not straight forward
    where openocd actually looks for the scripts.
    
    Signed-off-by: Andreas Fritiofson <and...@gm...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/helper/configuration.c b/src/helper/configuration.c
index 74bcc9b..2ea5da4 100644
--- a/src/helper/configuration.c
+++ b/src/helper/configuration.c
@@ -41,6 +41,8 @@ void add_script_search_dir (const char *dir)
 
 	script_search_dirs[num_script_dirs-1] = strdup(dir);
 	script_search_dirs[num_script_dirs] = NULL;
+
+	LOG_DEBUG("adding %s", dir);
 }
 
 void add_config_command (const char *cfg)

-----------------------------------------------------------------------

Summary of changes:
 src/helper/configuration.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-510-g69c7519

From: David B. <dbr...@us...> - 2009-11-21 01:27:47

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  69c751956293e822faa6cf844f2864d81c36a578 (commit)
       via  85fe1506a2296493d13368e545fa2d4ddb13ea72 (commit)
      from  7a67aae93c7de1e72baaba65635af0461ad8d040 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 69c751956293e822faa6cf844f2864d81c36a578
Author: David Brownell <dbr...@us...>
Date:   Fri Nov 20 16:27:24 2009 -0800

    ARM: pass 'struct reg *' to register r/w routines
    
    Implementations need to access the register struct they modify;
    make it easier and less error-prone to identify the instance.
    (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...)
    
    Plus some minor fixes noted when making these updates:  ARM7/ARM9
    accessor methods should be static; don't leave CPSR wrongly marked
    "dirty"; note significant XScale omissions in register handling;
    and have armv4_5_build_reg_cache() record its result.
    
    Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used
    for more than those older architecture generations.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 7a2b542..3a32764 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1577,7 +1577,7 @@ int arm7_9_restore_context(struct target *target)
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	struct reg *reg;
-	struct armv4_5_core_reg *reg_arch_info;
+	struct arm_reg *reg_arch_info;
 	enum armv4_5_mode current_mode = armv4_5->core_mode;
 	int i, j;
 	int dirty;
@@ -2084,25 +2084,24 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 	return err;
 }
 
-int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
+static int arm7_9_read_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode)
 {
 	uint32_t* reg_p[16];
 	uint32_t value;
 	int retval;
+	struct arm_reg *areg = r->arch_info;
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
 	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
-
-	enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
-
 	if ((num < 0) || (num > 16))
 		return ERROR_INVALID_ARGUMENTS;
 
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
-			&& (reg_mode != ARMV4_5_MODE_ANY))
+			&& (areg->mode != ARMV4_5_MODE_ANY))
 	{
 		uint32_t tmp_cpsr;
 
@@ -2125,10 +2124,7 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
 		/* read a program status register
 		 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
 		 */
-		struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
-		int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
-
-		arm7_9->read_xpsr(target, &value, spsr);
+		arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
 	}
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2136,13 +2132,13 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
 		return retval;
 	}
 
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
+	r->valid = 1;
+	r->dirty = 0;
+	buf_set_u32(r->value, 0, 32, value);
 
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
-			&& (reg_mode != ARMV4_5_MODE_ANY))	{
+			&& (areg->mode != ARMV4_5_MODE_ANY))	{
 		/* restore processor mode (mask T bit) */
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 	}
@@ -2150,23 +2146,22 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
 	return ERROR_OK;
 }
 
-int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value)
+static int arm7_9_write_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode, uint32_t value)
 {
 	uint32_t reg[16];
+	struct arm_reg *areg = r->arch_info;
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
 	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
-
-	enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
-
 	if ((num < 0) || (num > 16))
 		return ERROR_INVALID_ARGUMENTS;
 
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
-			&& (reg_mode != ARMV4_5_MODE_ANY))	{
+			&& (areg->mode != ARMV4_5_MODE_ANY))	{
 		uint32_t tmp_cpsr;
 
 		/* change processor mode (mask T bit) */
@@ -2188,8 +2183,7 @@ int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode
 		/* write a program status register
 		* if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
 		*/
-		struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
-		int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
+		int spsr = (areg->mode != ARMV4_5_MODE_ANY);
 
 		/* if we're writing the CPSR, mask the T bit */
 		if (!spsr)
@@ -2198,12 +2192,12 @@ int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode
 		arm7_9->write_xpsr(target, value, spsr);
 	}
 
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+	r->valid = 1;
+	r->dirty = 0;
 
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
-			&& (reg_mode != ARMV4_5_MODE_ANY))	{
+			&& (areg->mode != ARMV4_5_MODE_ANY))	{
 		/* restore processor mode (mask T bit) */
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 	}
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 266bf80..2f7132a 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -139,7 +139,6 @@ int arm7_9_full_context(struct target *target);
 int arm7_9_restore_context(struct target *target);
 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
-int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode);
 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer);
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 3bd5236..e7ea768 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -644,7 +644,6 @@ static void arm7tdmi_build_reg_cache(struct target *target)
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
 }
 
 int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index a69e49e..38b2284 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -754,7 +754,6 @@ static void arm9tdmi_build_reg_cache(struct target *target)
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
 }
 
 int arm9tdmi_init_target(struct command_context *cmd_ctx,
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index f8ab153..71c7299 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -363,7 +363,7 @@ static void arm_gdb_dummy_init(void)
 static int armv4_5_get_core_reg(struct reg *reg)
 {
 	int retval;
-	struct armv4_5_core_reg *armv4_5 = reg->arch_info;
+	struct arm_reg *armv4_5 = reg->arch_info;
 	struct target *target = armv4_5->target;
 
 	if (target->state != TARGET_HALTED)
@@ -372,16 +372,18 @@ static int armv4_5_get_core_reg(struct reg *reg)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
-	if (retval == ERROR_OK)
+	retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode);
+	if (retval == ERROR_OK) {
 		reg->valid = 1;
+		reg->dirty = 0;
+	}
 
 	return retval;
 }
 
 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 {
-	struct armv4_5_core_reg *armv4_5 = reg->arch_info;
+	struct arm_reg *armv4_5 = reg->arch_info;
 	struct target *target = armv4_5->target;
 	struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
 	uint32_t value = buf_get_u32(buf, 0, 32);
@@ -392,8 +394,16 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
+	/* Except for CPSR, the "reg" command exposes a writeback model
+	 * for the register cache.
+	 */
+	buf_set_u32(reg->value, 0, 32, value);
+	reg->dirty = 1;
+	reg->valid = 1;
+
 	if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
 	{
+		/* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */
 		if (value & 0x20)
 		{
 			/* T bit should be set */
@@ -415,19 +425,23 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 			}
 		}
 
+		/* REVISIT Why only update core for mode change, not also
+		 * for state changes?  Possibly older cores need to stay
+		 * in ARM mode during halt mode debug, not execute Thumb;
+		 * v6/v7a/v7r seem to do that automatically...
+		 */
+
 		if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
 		{
 			LOG_DEBUG("changing ARM core mode to '%s'",
 					arm_mode_name(value & 0x1f));
 			armv4_5_target->core_mode = value & 0x1f;
-			armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
+			armv4_5_target->write_core_reg(target, reg,
+					16, ARMV4_5_MODE_ANY, value);
+			reg->dirty = 0;
 		}
 	}
 
-	buf_set_u32(reg->value, 0, 32, value);
-	reg->dirty = 1;
-	reg->valid = 1;
-
 	return ERROR_OK;
 }
 
@@ -441,8 +455,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 	int num_regs = ARRAY_SIZE(arm_core_regs);
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 	struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
-	struct armv4_5_core_reg *arch_info = calloc(num_regs,
-					sizeof(struct armv4_5_core_reg));
+	struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
 	int i;
 
 	if (!cache || !reg_list || !arch_info) {
@@ -480,6 +493,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		cache->num_regs++;
 	}
 
+	armv4_5_common->core_cache = cache;
 	return cache;
 }
 
@@ -811,9 +825,14 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
 
 	for (i = 0; i <= 16; i++)
 	{
-		if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
-			armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
-		context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+		struct reg *r;
+
+		r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5_algorithm_info->core_mode, i);
+		if (!r->valid)
+			armv4_5->read_core_reg(target, r, i,
+					armv4_5_algorithm_info->core_mode);
+		context[i] = buf_get_u32(r->value, 0, 32);
 	}
 	cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
 
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index dbd62c0..c8fc558 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -109,9 +109,9 @@ struct arm
 	struct etm_context *etm;
 
 	int (*full_context)(struct target *target);
-	int (*read_core_reg)(struct target *target,
+	int (*read_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target *target,
+	int (*write_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
 };
@@ -137,7 +137,7 @@ struct armv4_5_algorithm
 	enum armv4_5_state core_state;
 };
 
-struct armv4_5_core_reg
+struct arm_reg
 {
 	int num;
 	enum armv4_5_mode mode;
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 168fe12..c6a46c5 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -877,7 +877,7 @@ static int cortex_a8_restore_context(struct target *target)
 
 		/* write dirty non-{R0,CPSR} registers sharing the same mode */
 		for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
-			struct armv4_5_core_reg *reg;
+			struct arm_reg *reg;
 
 			if (!r->dirty || i == ARMV4_5_CPSR)
 				continue;
@@ -1018,16 +1018,17 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
 #endif
 
 
-static int cortex_a8_write_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode, uint32_t value);
+static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode, uint32_t value);
 
-static int cortex_a8_read_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode)
+static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode)
 {
 	uint32_t value;
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 	struct reg_cache *cache = armv4_5->core_cache;
+	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
 
@@ -1042,10 +1043,10 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
-					.value, 0, 32);
-			cortex_a8_write_core_reg(target, 16,
-					ARMV4_5_MODE_ANY, mode);
+			cpsr_r = cache->reg_list + ARMV4_5_CPSR;
+			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
+			cortex_a8_write_core_reg(target, cpsr_r,
+					16, ARMV4_5_MODE_ANY, mode);
 		}
 	}
 
@@ -1066,24 +1067,24 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
 	cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
 	retval = jtag_execute_queue();
 	if (retval == ERROR_OK) {
-		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
-
 		r->valid = 1;
 		r->dirty = 0;
 		buf_set_u32(r->value, 0, 32, value);
 	}
 
-	if (cpsr)
-		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+	if (cpsr_r)
+		cortex_a8_write_core_reg(target, cpsr_r,
+				16, ARMV4_5_MODE_ANY, cpsr);
 	return retval;
 }
 
-static int cortex_a8_write_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode, uint32_t value)
+static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode, uint32_t value)
 {
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 	struct reg_cache *cache = armv4_5->core_cache;
+	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
 
@@ -1098,10 +1099,10 @@ static int cortex_a8_write_core_reg(struct target *target, int num,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
-					.value, 0, 32);
-			cortex_a8_write_core_reg(target, 16,
-					ARMV4_5_MODE_ANY, mode);
+			cpsr_r = cache->reg_list + ARMV4_5_CPSR;
+			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
+			cortex_a8_write_core_reg(target, cpsr_r,
+					16, ARMV4_5_MODE_ANY, mode);
 		}
 	}
 
@@ -1122,15 +1123,14 @@ static int cortex_a8_write_core_reg(struct target *target, int num,
 
 	cortex_a8_dap_write_coreregister_u32(target, value, cookie);
 	if ((retval = jtag_execute_queue()) == ERROR_OK) {
-		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
-
 		buf_set_u32(r->value, 0, 32, value);
 		r->valid = 1;
 		r->dirty = 0;
 	}
 
-	if (cpsr)
-		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+	if (cpsr_r)
+		cortex_a8_write_core_reg(target, cpsr_r,
+				16, ARMV4_5_MODE_ANY, cpsr);
 	return retval;
 }
 
@@ -1619,7 +1619,6 @@ static void cortex_a8_build_reg_cache(struct target *target)
 	armv4_5->core_type = ARM_MODE_MON;
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
 }
 
 
diff --git a/src/target/xscale.c b/src/target/xscale.c
index f13366a..c908fd7 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1646,16 +1646,18 @@ static int xscale_deassert_reset(struct target *target)
 	return ERROR_OK;
 }
 
-static int xscale_read_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode)
+static int xscale_read_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode)
 {
+	/** \todo add debug handler support for core register reads */
 	LOG_ERROR("not implemented");
 	return ERROR_OK;
 }
 
-static int xscale_write_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode, uint32_t value)
+static int xscale_write_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode, uint32_t value)
 {
+	/** \todo add debug handler support for core register writes */
 	LOG_ERROR("not implemented");
 	return ERROR_OK;
 }
@@ -2829,7 +2831,6 @@ static void xscale_build_reg_cache(struct target *target)
 	int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
 
 	(*cache_p)->next = malloc(sizeof(struct reg_cache));
 	cache_p = &(*cache_p)->next;

commit 85fe1506a2296493d13368e545fa2d4ddb13ea72
Author: David Brownell <dbr...@us...>
Date:   Fri Nov 20 16:21:29 2009 -0800

    ARM7/ARM9: remove old "debug commands"
    
    Remove two commands that were documented as "debug commands"
    and where "you probably don't want to use this".   We never
    intended to support them, and at least one problem report
    boiled down to using this when it shouldn't have been used.
    
    Update the docs on the existing register commands to talk a
    bit more about register access and cache behavior.  (Those
    debug commands existed largely to *bypass* the cache.)  And
    fix some minor doc goofs that snuck in with recent changes,
    renaming "armv4_5" as "arm" and "arm9tdmi" as "arm9".
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 0253dc0..9659e92 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4933,26 +4933,37 @@ target which should become current.
 
 @deffn Command reg [(number|name) [value]]
 Access a single register by @var{number} or by its @var{name}.
+The target must generally be halted before access to CPU core
+registers is allowed.  Depending on the hardware, some other
+registers may be accessible while the target is running.
 
 @emph{With no arguments}:
 list all available registers for the current target,
 showing number, name, size, value, and cache status.
+For valid entries, a value is shown; valid entries
+which are also dirty (and will be written back later)
+are flagged as such.
 
 @emph{With number/name}: display that register's value.
 
 @emph{With both number/name and value}: set register's value.
+Writes may be held in a writeback cache internal to OpenOCD,
+so that setting the value marks the register as dirty instead
+of immediately flushing that value.  Resuming CPU execution
+(including by single stepping) or otherwise activating the
+relevant module will flush such values.
 
 Cores may have surprisingly many registers in their
 Debug and trace infrastructure:
 
 @example
 > reg
-(0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
-(1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
-(2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
+===== ARM registers
+(0) r0 (/32): 0x0000D3C2 (dirty)
+(1) r1 (/32): 0xFD61F31C
+(2) r2 (/32)
 ...
-(164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
-              0x00000000 (dirty: 0, valid: 0)
+(164) ETM_contextid_comparator_mask (/32)
 >
 @end example
 @end deffn
@@ -5554,17 +5565,25 @@ ThumbEE disassembly currently has no explicit support.
 
 @deffn Command {arm reg}
 Display a table of all banked core registers, fetching the current value from every
-core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
-register value.
+core mode if necessary.
 @end deffn
 
+@section ARMv4 and ARMv5 Architecture
+@cindex ARMv4
+@cindex ARMv5
+
+The ARMv4 and ARMv5 architectures are widely used in embedded systems,
+and introduced core parts of the instruction set in use today. 
+That includes the Thumb instruction set, introduced in the ARMv4T
+variant.
+
 @subsection ARM7 and ARM9 specific commands
 @cindex ARM7
 @cindex ARM9
 
 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
 ARM9TDMI, ARM920T or ARM926EJ-S.
-They are available in addition to the ARMv4/5 commands,
+They are available in addition to the ARM commands,
 and any other core-specific commands that may be available.
 
 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
@@ -5591,49 +5610,13 @@ cables (FT2232), but might be unsafe if used with targets running at very low
 speeds, like the 32kHz startup clock of an AT91RM9200.
 @end deffn
 
-@deffn {Debug Command} {arm7_9 write_core_reg} num mode word
-@emph{This is intended for use while debugging OpenOCD; you probably
-shouldn't use it.}
-
-Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
-as used in the specified @var{mode}
-(where e.g. mode 16 is "user" and mode 19 is "supervisor";
-the M4..M0 bits of the PSR).
-Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
-Register 16 is the mode-specific SPSR,
-unless the specified mode is 0xffffffff (32-bit all-ones)
-in which case register 16 is the CPSR.
-The write goes directly to the CPU, bypassing the register cache.
-@end deffn
-
-@deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
-@emph{This is intended for use while debugging OpenOCD; you probably
-shouldn't use it.}
-
-If the second parameter is zero, writes @var{word} to the
-Current Program Status register (CPSR).
-Else writes @var{word} to the current mode's Saved PSR (SPSR).
-In both cases, this bypasses the register cache.
-@end deffn
-
-@deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
-@emph{This is intended for use while debugging OpenOCD; you probably
-shouldn't use it.}
-
-Writes eight bits to the CPSR or SPSR,
-first rotating them by @math{2*rotate} bits,
-and bypassing the register cache.
-This has lower JTAG overhead than writing the entire CPSR or SPSR
-with @command{arm7_9 write_xpsr}.
-@end deffn
-
 @subsection ARM720T specific commands
 @cindex ARM720T
 
 These commands are available to ARM720T based CPUs,
 which are implementations of the ARMv4T architecture
 based on the ARM7TDMI-S integer core.
-They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
+They are available in addition to the ARM and ARM7/ARM9 commands.
 
 @deffn Command {arm720t cp15} regnum [value]
 Display cp15 register @var{regnum};
@@ -5677,8 +5660,8 @@ or a list with one or more of the following:
 These commands are available to ARM920T based CPUs,
 which are implementations of the ARMv4T architecture
 built using the ARM9TDMI integer core.
-They are available in addition to the ARMv4/5, ARM7/ARM9,
-and ARM9TDMI commands.
+They are available in addition to the ARM, ARM7/ARM9,
+and ARM9 commands.
 
 @deffn Command {arm920t cache_info}
 Print information about the caches found. This allows to see whether your target
@@ -5711,8 +5694,8 @@ Dump the content of the ITLB and DTLB to a file named @file{filename}.
 These commands are available to ARM926ej-s based CPUs,
 which are implementations of the ARMv5TEJ architecture
 based on the ARM9EJ-S integer core.
-They are available in addition to the ARMv4/5, ARM7/ARM9,
-and ARM9TDMI commands.
+They are available in addition to the ARM, ARM7/ARM9,
+and ARM9 commands.
 
 The Feroceon cores also support these commands, although
 they are not built from ARM926ej-s designs.
@@ -5733,8 +5716,8 @@ Else that register is read and displayed.
 
 These commands are available to ARM966 based CPUs,
 which are implementations of the ARMv5TE architecture.
-They are available in addition to the ARMv4/5, ARM7/ARM9,
-and ARM9TDMI commands.
+They are available in addition to the ARM, ARM7/ARM9,
+and ARM9 commands.
 
 @deffn Command {arm966e cp15} regnum [value]
 Display cp15 register @var{regnum};
@@ -5926,7 +5909,7 @@ cores @emph{except the ARM1176} use the same six bits.
 @cindex Debug Access Port
 @cindex DAP
 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
-included on cortex-m3 and cortex-a8 systems.
+included on Cortex-M3 and Cortex-A8 systems.
 They are available in addition to other core-specific commands that may be available.
 
 @deffn Command {dap info} [num]
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 1c85417..7a2b542 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2737,124 +2737,6 @@ int arm7_9_examine(struct target *target)
 	return retval;
 }
 
-
-COMMAND_HANDLER(handle_arm7_9_write_xpsr_command)
-{
-	uint32_t value;
-	int spsr;
-	int retval;
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-
-	if (!is_arm7_9(arm7_9))
-	{
-		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
-		return ERROR_TARGET_INVALID;
-	}
-
-	if (target->state != TARGET_HALTED)
-	{
-		command_print(CMD_CTX, "can't write registers while running");
-		return ERROR_FAIL;
-	}
-
-	if (CMD_ARGC < 2)
-	{
-		command_print(CMD_CTX, "usage: write_xpsr <value> <not cpsr | spsr>");
-		return ERROR_FAIL;
-	}
-
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], spsr);
-
-	/* if we're writing the CPSR, mask the T bit */
-	if (!spsr)
-		value &= ~0x20;
-
-	arm7_9->write_xpsr(target, value, spsr);
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		LOG_ERROR("JTAG error while writing to xpsr");
-		return retval;
-	}
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command)
-{
-	uint32_t value;
-	int rotate;
-	int spsr;
-	int retval;
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-
-	if (!is_arm7_9(arm7_9))
-	{
-		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
-		return ERROR_TARGET_INVALID;
-	}
-
-	if (target->state != TARGET_HALTED)
-	{
-		command_print(CMD_CTX, "can't write registers while running");
-		return ERROR_FAIL;
-	}
-
-	if (CMD_ARGC < 3)
-	{
-		command_print(CMD_CTX, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
-		return ERROR_FAIL;
-	}
-
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], rotate);
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], spsr);
-
-	arm7_9->write_xpsr_im8(target, value, rotate, spsr);
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
-		return retval;
-	}
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
-{
-	uint32_t value;
-	uint32_t mode;
-	int num;
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-
-	if (!is_arm7_9(arm7_9))
-	{
-		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
-		return ERROR_TARGET_INVALID;
-	}
-
-	if (target->state != TARGET_HALTED)
-	{
-		command_print(CMD_CTX, "can't write registers while running");
-		return ERROR_FAIL;
-	}
-
-	if (CMD_ARGC < 3)
-	{
-		command_print(CMD_CTX, "usage: write_core_reg <num> <mode> <value>");
-		return ERROR_FAIL;
-	}
-
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], num);
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], mode);
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
-
-	return arm7_9_write_core_reg(target, num, mode, value);
-}
-
 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
@@ -2948,18 +2830,6 @@ int arm7_9_register_commands(struct command_context *cmd_ctx)
 	arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
 			NULL, COMMAND_ANY, "arm7/9 specific commands");
 
-	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr",
-			handle_arm7_9_write_xpsr_command, COMMAND_EXEC,
-			"write program status register <value> <not cpsr | spsr>");
-	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8",
-			handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC,
-			"write program status register "
-			"<8bit immediate> <rotate> <not cpsr | spsr>");
-
-	register_command(cmd_ctx, arm7_9_cmd, "write_core_reg",
-			handle_arm7_9_write_core_reg_command, COMMAND_EXEC,
-			"write core register <num> <mode> <value>");
-
 	register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
 			handle_arm7_9_dbgrq_command, COMMAND_ANY,
 			"use EmbeddedICE dbgrq instead of breakpoint "

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi           |   87 +++++++++-------------
 src/target/arm7_9_common.c |  172 +++++---------------------------------------
 src/target/arm7_9_common.h |    1 -
 src/target/arm7tdmi.c      |    1 -
 src/target/arm9tdmi.c      |    1 -
 src/target/armv4_5.c       |   47 +++++++++----
 src/target/armv4_5.h       |    6 +-
 src/target/cortex_a8.c     |   47 ++++++------
 src/target/xscale.c        |   11 ++--
 9 files changed, 118 insertions(+), 255 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-508-g7a67aae

From: Zach W. <zw...@us...> - 2009-11-21 00:12:57

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  7a67aae93c7de1e72baaba65635af0461ad8d040 (commit)
       via  a19aaf913688424dbd6384028854c178c9eb5bf2 (commit)
       via  e5b0a69ba99f58991ebb5d07ad947592f09728f1 (commit)
       via  5458fef43ca7072312440301a9469c686ca641e2 (commit)
       via  82449e2d60fbbb5ce8a6285b6e6d60e5767ee429 (commit)
       via  9e9633c6b98cc9243ae78cd12ab657d041eaa73e (commit)
       via  73c6e3bb18326050acc8908b561443a7b37549bb (commit)
       via  67c29d9935b023a85056149e2f73288434c25995 (commit)
      from  7b77b3c5d1a20793cc2057a96e67d8f7ca20e4cb (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 7a67aae93c7de1e72baaba65635af0461ad8d040
Author: Zachary T Welch <zw...@su...>
Date:   Fri Nov 20 10:16:46 2009 -0800

    maintain command lists in sorted order
    
    Use insertion sort to the command link lists.  The only practical effect
    of this is to order the output of the new 'help' command.

diff --git a/src/helper/command.c b/src/helper/command.c
index d8b7875..f6c6b2d 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -177,7 +177,8 @@ static int script_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 
 /**
  * Find a command by name from a list of commands.
- * @returns The named command if found, or NULL.
+ * @returns Returns the named command if it exists in the list.
+ * Returns NULL otherwise.
  */
 static struct command *command_find(struct command *head, const char *name)
 {
@@ -190,9 +191,10 @@ static struct command *command_find(struct command *head, const char *name)
 }
 
 /**
- * Add the command to the end of linked list.
- * @returns Returns false if the named command already exists in the list.
- * Returns true otherwise.
+ * Add the command into the linked list, sorted by name.
+ * @param head Address to head of command list pointer, which may be
+ * updated if @c c gets inserted at the beginning of the list.
+ * @param c The command to add to the list pointed to by @c head.
  */
 static void command_add_child(struct command **head, struct command *c)
 {
@@ -202,9 +204,17 @@ static void command_add_child(struct command **head, struct command *c)
 		*head = c;
 		return;
 	}
-	struct command *cc = *head;
-	while (cc->next) cc = cc->next;
-	cc->next = c;
+
+	while ((*head)->next && (strcmp(c->name, (*head)->name) > 0))
+		head = &(*head)->next;
+
+	if (strcmp(c->name, (*head)->name) > 0) {
+		c->next = (*head)->next;
+		(*head)->next = c;
+	} else {
+		c->next = *head;
+		*head = c;
+	}
 }
 
 static struct command **command_list_for_parent(

commit a19aaf913688424dbd6384028854c178c9eb5bf2
Author: Zachary T Welch <zw...@su...>
Date:   Thu Nov 19 07:23:25 2009 -0800

    add add_help_text command handler
    
    Rewrite means for scripts to register help text for commands.  These
    cause the new commands to be stored in the command heirarchy, with
    built-in commands; however, they will never be invoked there because
    they do not receive a command handler.  The same trick is used for
    the Jim commands.
    
    Remove the old helpers that were used to register commands.

diff --git a/src/helper/command.c b/src/helper/command.c
index 0958147..d8b7875 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -172,32 +172,6 @@ static int script_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	return (retval == ERROR_OK)?JIM_OK:JIM_ERR;
 }
 
-static Jim_Obj *command_name_list(struct command *c)
-{
-	Jim_Obj *cmd_list = c->parent ?
-			command_name_list(c->parent) :
-			Jim_NewListObj(interp, NULL, 0);
-	Jim_ListAppendElement(interp, cmd_list,
-			Jim_NewStringObj(interp, c->name, -1));
-
-	return cmd_list;
-}
-
-static void command_helptext_add(Jim_Obj *cmd_list, const char *help)
-{
-	Jim_Obj *cmd_entry = Jim_NewListObj(interp, NULL, 0);
-	Jim_ListAppendElement(interp, cmd_entry, cmd_list);
-	Jim_ListAppendElement(interp, cmd_entry,
-			Jim_NewStringObj(interp, help ? : "", -1));
-
-	/* accumulate help text in Tcl helptext list.  */
-	Jim_Obj *helptext = Jim_GetGlobalVariableStr(interp,
-			"ocd_helptext", JIM_ERRMSG);
-	if (Jim_IsShared(helptext))
-		helptext = Jim_DuplicateObj(interp, helptext);
-	Jim_ListAppendElement(interp, helptext, cmd_entry);
-}
-
 /* nice short description of source file */
 #define __THIS__FILE__ "command.c"
 
@@ -258,8 +232,6 @@ static struct command *command_new(struct command_context *cmd_ctx,
 
 	command_add_child(command_list_for_parent(cmd_ctx, parent), c);
 
-	command_helptext_add(command_name_list(c), help);
-
 	return c;
 }
 static void command_free(struct command *c)
@@ -771,6 +743,66 @@ COMMAND_HANDLER(handle_help_command)
 	return CALL_COMMAND_HANDLER(command_help_show, c, 0);
 }
 
+
+int help_add_command(struct command_context *cmd_ctx, struct command *parent,
+		const char *cmd_name, const char *help_text)
+{
+	struct command **head = command_list_for_parent(cmd_ctx, parent);
+	struct command *nc = command_find(*head, cmd_name);
+	if (NULL == nc)
+	{
+		// add a new command with help text
+		nc = register_command(cmd_ctx, parent, cmd_name,
+				NULL, COMMAND_ANY, help_text);
+		if (NULL == nc)
+		{
+			LOG_ERROR("failed to add '%s' help text", cmd_name);
+			return ERROR_FAIL;
+		}
+		LOG_DEBUG("added '%s' help text", cmd_name);
+	}
+	else
+	{
+		bool replaced = false;
+		if (nc->help)
+		{
+			free((void *)nc->help);
+			replaced = true;
+		}
+		nc->help = strdup(help_text);
+
+		if (replaced)
+			LOG_INFO("replaced existing '%s' help", cmd_name);
+		else
+			LOG_DEBUG("added '%s' help text", cmd_name);
+	}
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(handle_help_add_command)
+{
+	if (CMD_ARGC < 2)
+	{
+		LOG_ERROR("%s: insufficient arguments", CMD_NAME);
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	// save help text and remove it from argument list
+	const char *help_text = CMD_ARGV[--CMD_ARGC];
+	// likewise for the leaf command name
+	const char *cmd_name = CMD_ARGV[--CMD_ARGC];
+
+	struct command *c = NULL;
+	if (CMD_ARGC > 0)
+	{
+		c = CMD_CTX->commands;
+		int retval = CALL_COMMAND_HANDLER(command_help_find, c, &c);
+		if (ERROR_OK != retval)
+			return retval;
+	}
+	return help_add_command(CMD_CTX, c, cmd_name, help_text);
+}
+
 /* sleep command sleeps for <n> miliseconds
  * this is useful in target startup scripts
  */
@@ -866,6 +898,11 @@ struct command_context* command_init(const char *startup_tcl)
 	interp->cb_fflush = openocd_jim_fflush;
 	interp->cb_fgets = openocd_jim_fgets;
 
+	register_command(context, NULL, "add_help_text",
+			handle_help_add_command, COMMAND_ANY,
+			"<command> [...] <help_text>] - "
+			"add new command help text");
+
 #if !BUILD_ECOSBOARD
 	Jim_EventLoopOnLoad(interp);
 #endif
@@ -922,7 +959,7 @@ void register_jim(struct command_context *cmd_ctx, const char *name,
 	Jim_ListAppendElement(interp, cmd_list,
 			Jim_NewStringObj(interp, name, -1));
 
-	command_helptext_add(cmd_list, help);
+	help_add_command(cmd_ctx, NULL, name, help);
 }
 
 #define DEFINE_PARSE_NUM_TYPE(name, type, func, min, max) \
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index ddfef1d..fc84943 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -3,21 +3,6 @@
 # Embedded into OpenOCD executable
 #
 
-# Help text list. A list of command + help text pairs.
-#
-# Commands can be more than one word and they are stored
-# as "flash banks" "help text x x x"
-
-proc add_help_text {cmd cmd_help} {
-	global ocd_helptext
-	lappend ocd_helptext [list $cmd $cmd_help]
-}
-
-proc get_help_text {} {
-	global ocd_helptext
-	return $ocd_helptext
-}
-
 
 # We need to explicitly redirect this to the OpenOCD command
 # as Tcl defines the exit proc
@@ -25,6 +10,7 @@ proc exit {} {
 	ocd_throw exit
 }
 
+# Help text list. A list of command + help text pairs.
 proc cmd_help {cmdname h indent} {
 	set indent [expr $indent * 2]
 

commit e5b0a69ba99f58991ebb5d07ad947592f09728f1
Author: Zachary T Welch <zw...@su...>
Date:   Fri Nov 20 09:11:39 2009 -0800

    provide command context during cmd_init
    
    For the startup.tcl code to use built-in commands, the context must be
    associated with the interpreter temporarily.  This will be required to
    add help text.

diff --git a/src/helper/command.c b/src/helper/command.c
index f135bb0..0958147 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -869,12 +869,14 @@ struct command_context* command_init(const char *startup_tcl)
 #if !BUILD_ECOSBOARD
 	Jim_EventLoopOnLoad(interp);
 #endif
+	Jim_SetAssocData(interp, "context", NULL, context);
 	if (Jim_Eval_Named(interp, startup_tcl, "embedded:startup.tcl",1) == JIM_ERR)
 	{
 		LOG_ERROR("Failed to run startup.tcl (embedded into OpenOCD)");
 		Jim_PrintErrorMessage(interp);
 		exit(-1);
 	}
+	Jim_DeleteAssocData(interp, "context");
 
 	register_command(context, NULL, "sleep",
 			handle_sleep_command, COMMAND_ANY,

commit 5458fef43ca7072312440301a9469c686ca641e2
Author: Zachary T Welch <zw...@su...>
Date:   Thu Nov 19 06:48:37 2009 -0800

    improve 'help' command
    
    Rewrites 'help' command in C, using new 'cmd_help' for display.  Adds the
    built-in 'help' COMMAND_HANDLER to provide better output than the
    TCL-based script command (e.g. heirarchical listing of commands).
    
    The help string is stored in the command structure, though it conitnues
    to be pushed into the Jim environment.  The current idiomatic usage
    suggests the addition of a usage field as well, to provide two levels
    of detail for users to consume (i.e. terse usage list, or verbose help).

diff --git a/src/helper/command.c b/src/helper/command.c
index 87a898f..f135bb0 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -250,6 +250,8 @@ static struct command *command_new(struct command_context *cmd_ctx,
 	memset(c, 0, sizeof(struct command));
 
 	c->name = strdup(name);
+	if (help)
+		c->help = strdup(help);
 	c->parent = parent;
 	c->handler = handler;
 	c->mode = mode;
@@ -273,6 +275,8 @@ static void command_free(struct command *c)
 
 	if (c->name)
 		free(c->name);
+	if (c->help)
+		free((void*)c->help);
 	free(c);
 }
 
@@ -721,6 +725,52 @@ static int jim_capture(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	return retcode;
 }
 
+static COMMAND_HELPER(command_help_find, struct command *head,
+		struct command **out)
+{
+	if (0 == CMD_ARGC)
+		return ERROR_INVALID_ARGUMENTS;
+	*out = command_find(head, CMD_ARGV[0]);
+	if (NULL == *out)
+		return ERROR_INVALID_ARGUMENTS;
+	if (--CMD_ARGC == 0)
+		return ERROR_OK;
+	CMD_ARGV++;
+	return CALL_COMMAND_HANDLER(command_help_find, (*out)->children, out);
+}
+
+static COMMAND_HELPER(command_help_show, struct command *c, unsigned n);
+
+static COMMAND_HELPER(command_help_show_list, struct command *head, unsigned n)
+{
+	for (struct command *c = head; NULL != c; c = c->next)
+		CALL_COMMAND_HANDLER(command_help_show, c, n);
+	return ERROR_OK;
+}
+static COMMAND_HELPER(command_help_show, struct command *c, unsigned n)
+{
+	command_run_linef(CMD_CTX, "cmd_help {%s} {%s} %d", command_name(c, ' '),
+			c->help ? : "no help available", n);
+
+	if (++n >= 2)
+		return ERROR_OK;
+
+	return CALL_COMMAND_HANDLER(command_help_show_list, c->children, n);
+}
+COMMAND_HANDLER(handle_help_command)
+{
+	struct command *c = CMD_CTX->commands;
+
+	if (0 == CMD_ARGC)
+		return CALL_COMMAND_HANDLER(command_help_show_list, c, 0);
+
+	int retval = CALL_COMMAND_HANDLER(command_help_find, c, &c);
+	if (ERROR_OK != retval)
+		return retval;
+
+	return CALL_COMMAND_HANDLER(command_help_show, c, 0);
+}
+
 /* sleep command sleeps for <n> miliseconds
  * this is useful in target startup scripts
  */
@@ -831,6 +881,10 @@ struct command_context* command_init(const char *startup_tcl)
 			"<n> [busy] - sleep for n milliseconds. "
 			"\"busy\" means busy wait");
 
+	register_command(context, NULL, "help",
+			&handle_help_command, COMMAND_ANY,
+			"[<command_name> ...] - show built-in command help");
+
 	return context;
 }
 
@@ -977,5 +1031,3 @@ COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label)
 	}
 	return ERROR_OK;
 }
-
-
diff --git a/src/helper/command.h b/src/helper/command.h
index a7b422a..837b4bd 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -159,6 +159,7 @@ typedef __COMMAND_HANDLER((*command_handler_t));
 struct command
 {
 	char *name;
+	const char *help;
 	struct command *parent;
 	struct command *children;
 	command_handler_t handler;
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index 30dc184..ddfef1d 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -58,24 +58,6 @@ proc cmd_help {cmdname h indent} {
 	}
 }
 
-#Print help text for a command. Word wrap
-#help text that is too wide inside column.
-proc help {args} {
-	global ocd_helptext
-	set cmd $args
-	foreach a [lsort $ocd_helptext] {
-		if {[string length $cmd] == 0 || \
-			[string first $cmd $a] != -1 || \
-			[string first $cmd [lindex $a 1]] != -1} \
-		{
-			cmd_help [lindex $a 0] [lindex $a 1] 0
-		}
-	}
-}
-
-add_help_text help "Tcl implementation of help command"
-
-
 # If a fn is unknown to Tcl, we try to execute it as an OpenOCD command
 #
 # We also support two level commands. "flash banks" is translated to

commit 82449e2d60fbbb5ce8a6285b6e6d60e5767ee429
Author: Zachary T Welch <zw...@su...>
Date:   Thu Nov 19 06:44:58 2009 -0800

    factor help script command into parts
    
    Creates a helper function, cmd_help, which displays the help string
    for a single command.  Presently, it is called from the loop in help.
    
    The routine has been extended to allow indentation of command groups,
    so an improved help command can improve the display of information.

diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index eefb690..30dc184 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -25,6 +25,39 @@ proc exit {} {
 	ocd_throw exit
 }
 
+proc cmd_help {cmdname h indent} {
+	set indent [expr $indent * 2]
+
+	set fmt_str [format "%%%ds%%-%ds %%s" $indent [expr 25 - $indent]]
+	set w [expr 50 - $indent]
+	set n 0
+
+	while 1 {
+		if {$n > [string length $h]} {break}
+
+		set next_a [expr $n + $w]
+		if {[string length $h] > $n + $w} \
+		{
+			set xxxx [string range $h $n [expr $n + $w]]
+			for {set lastpos [expr [string length $xxxx] - 1]} \
+				{$lastpos >= 0 && [string compare \
+					[string range $xxxx $lastpos $lastpos] " "] != 0} \
+				{set lastpos [expr $lastpos - 1]} \
+			{
+			}
+			#set next_a -1
+			if {$lastpos != -1} {
+				set next_a [expr $lastpos + $n + 1]
+			}
+		}
+
+		puts [format $fmt_str "" $cmdname \
+				[string range $h $n [expr $next_a - 1]] ]
+		set cmdname ""
+		set n [expr $next_a]
+	}
+}
+
 #Print help text for a command. Word wrap
 #help text that is too wide inside column.
 proc help {args} {
@@ -35,34 +68,7 @@ proc help {args} {
 			[string first $cmd $a] != -1 || \
 			[string first $cmd [lindex $a 1]] != -1} \
 		{
-			set w 50
-			set cmdname [lindex $a 0]
-			set h [lindex $a 1]
-			set n 0
-			while 1 {
-				if {$n > [string length $h]} {break}
-
-				set next_a [expr $n + $w]
-				if {[string length $h] > $n + $w} \
-				{
-					set xxxx [string range $h $n [expr $n + $w]]
-					for {set lastpos [expr [string length $xxxx] - 1]} \
-						{$lastpos >= 0 && [string compare \
-							[string range $xxxx $lastpos $lastpos] " "] != 0} \
-						{set lastpos [expr $lastpos - 1]} \
-					{
-					}
-					#set next_a -1
-					if {$lastpos != -1} {
-						set next_a [expr $lastpos + $n + 1]
-					}
-				}
-
-				puts [format "%-25s %s" $cmdname \
-						[string range $h $n [expr $next_a-1]] ]
-				set cmdname ""
-				set n [expr $next_a]
-			}
+			cmd_help [lindex $a 0] [lindex $a 1] 0
 		}
 	}
 }

commit 9e9633c6b98cc9243ae78cd12ab657d041eaa73e
Author: Zachary T Welch <zw...@su...>
Date:   Thu Nov 19 08:38:17 2009 -0800

    refactor command registration
    
    Refactors the command registration to use helpers to simplify the code.
    The unregistration routines were made more flexible by allowing them
    to operate on a single command, such that one can remove all of a
    commands children in one step (perhaps before adding back a 'config'
    subcommand that allows getting the others back).  Eliminates a bit
    of duplicated code and adds full API documentation for these routines.

diff --git a/src/helper/command.c b/src/helper/command.c
index 538c07b..87a898f 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -233,33 +233,69 @@ static void command_add_child(struct command **head, struct command *c)
 	cc->next = c;
 }
 
-struct command* register_command(struct command_context *context,
-		struct command *parent, char *name, command_handler_t handler,
-		enum command_mode mode, char *help)
+static struct command **command_list_for_parent(
+		struct command_context *cmd_ctx, struct command *parent)
 {
-	if (!context || !name)
-		return NULL;
+	return parent ? &parent->children : &cmd_ctx->commands;
+}
 
-	struct command **head = parent ? &parent->children : &context->commands;
-	struct command *c = command_find(*head, name);
-	if (NULL != c)
-		return c;
+static struct command *command_new(struct command_context *cmd_ctx,
+		struct command *parent, const char *name,
+		command_handler_t handler, enum command_mode mode,
+		const char *help)
+{
+	assert(name);
 
-	c = malloc(sizeof(struct command));
+	struct command *c = malloc(sizeof(struct command));
+	memset(c, 0, sizeof(struct command));
 
 	c->name = strdup(name);
 	c->parent = parent;
-	c->children = NULL;
 	c->handler = handler;
 	c->mode = mode;
-	c->next = NULL;
 
-	command_add_child(head, c);
+	command_add_child(command_list_for_parent(cmd_ctx, parent), c);
 
 	command_helptext_add(command_name_list(c), help);
 
-	/* just a placeholder, no handler */
-	if (c->handler == NULL)
+	return c;
+}
+static void command_free(struct command *c)
+{
+	/// @todo if command has a handler, unregister its jim command!
+
+	while (NULL != c->children)
+	{
+		struct command *tmp = c->children;
+		c->children = tmp->next;
+		command_free(tmp);
+	}
+
+	if (c->name)
+		free(c->name);
+	free(c);
+}
+
+struct command* register_command(struct command_context *context,
+		struct command *parent, const char *name,
+		command_handler_t handler, enum command_mode mode,
+		const char *help)
+{
+	if (!context || !name)
+		return NULL;
+
+	struct command **head = command_list_for_parent(context, parent);
+	struct command *c = command_find(*head, name);
+	if (NULL != c)
+	{
+		LOG_ERROR("command '%s' is already registered in '%s' context",
+				name, parent ? parent->name : "<global>");
+		return c;
+	}
+
+	c = command_new(context, parent, name, handler, mode, help);
+	/* if allocation failed or it is a placeholder (no handler), we're done */
+	if (NULL == c || NULL == c->handler)
 		return c;
 
 	const char *full_name = command_name(c, '_');
@@ -281,85 +317,43 @@ struct command* register_command(struct command_context *context,
 	return c;
 }
 
-int unregister_all_commands(struct command_context *context)
+int unregister_all_commands(struct command_context *context,
+		struct command *parent)
 {
-	struct command *c, *c2;
-
 	if (context == NULL)
 		return ERROR_OK;
 
-	while (NULL != context->commands)
+	struct command **head = command_list_for_parent(context, parent);
+	while (NULL != *head)
 	{
-		c = context->commands;
-
-		while (NULL != c->children)
-		{
-			c2 = c->children;
-			c->children = c->children->next;
-			free(c2->name);
-			c2->name = NULL;
-			free(c2);
-			c2 = NULL;
-		}
-
-		context->commands = context->commands->next;
-
-		free(c->name);
-		c->name = NULL;
-		free(c);
-		c = NULL;
+		struct command *tmp = *head;
+		*head = tmp->next;
+		command_free(tmp);
 	}
 
 	return ERROR_OK;
 }
 
-int unregister_command(struct command_context *context, char *name)
+int unregister_command(struct command_context *context,
+		struct command *parent, const char *name)
 {
-	struct command *c, *p = NULL, *c2;
-
 	if ((!context) || (!name))
 		return ERROR_INVALID_ARGUMENTS;
 
-	/* find command */
-	c = context->commands;
-
-	while (NULL != c)
+	struct command *p = NULL;
+	struct command **head = command_list_for_parent(context, parent);
+	for (struct command *c = *head; NULL != c; p = c, c = c->next)
 	{
-		if (strcmp(name, c->name) == 0)
-		{
-			/* unlink command */
-			if (p)
-			{
-				p->next = c->next;
-			}
-			else
-			{
-				/* first element in command list */
-				context->commands = c->next;
-			}
+		if (strcmp(name, c->name) != 0)
+			continue;
 
-			/* unregister children */
-			while (NULL != c->children)
-			{
-				c2 = c->children;
-				c->children = c->children->next;
-				free(c2->name);
-				c2->name = NULL;
-				free(c2);
-				c2 = NULL;
-			}
-
-			/* delete command */
-			free(c->name);
-			c->name = NULL;
-			free(c);
-			c = NULL;
-			return ERROR_OK;
-		}
+		if (p)
+			p->next = c->next;
+		else
+			*head = c->next;
 
-		/* remember the last command for unlinking */
-		p = c;
-		c = c->next;
+		command_free(c);
+		return ERROR_OK;
 	}
 
 	return ERROR_OK;
diff --git a/src/helper/command.h b/src/helper/command.h
index def0935..a7b422a 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -176,12 +176,53 @@ struct command
  */
 char *command_name(struct command *c, char delim);
 
-struct command* register_command(struct command_context *context,
-		struct command *parent, char *name, command_handler_t handler,
-		enum command_mode mode, char *help);
+/**
+ * Register a command @c handler that can be called from scripts during
+ * the execution @c mode specified.
+ *
+ * If @c parent is non-NULL, the new command will be registered as a
+ * sub-command under it; otherwise, it will be available as a top-level
+ * command.
+ *
+ * A conventioal format should be used for help strings, to provide both
+ * usage and basic information:
+ * @code
+ * "@<options@> ... - some explanation text"
+ * @endcode
+ *
+ * @param cmd_ctx The command_context in which to register the command.
+ * @param parent Register this command as a child of this, or NULL to
+ * register a top-level command.
+ * @param name The name of the command to register, which must not have
+ * been registered previously.
+ * @param handler The callback function that will be called.  If NULL,
+ * then the command serves as a placeholder for its children or a script.
+ * @param mode The command mode(s) in which this command may be run.
+ * @param help The help text that will be displayed to the user.
+ * @returns The new command, if successful; otherwise, NULL.
+ */
+struct command* register_command(struct command_context *cmd_ctx,
+		struct command *parent, const char *name,
+		command_handler_t handler, enum command_mode mode,
+		const char *help);
 
-int unregister_command(struct command_context *context, char *name);
-int unregister_all_commands(struct command_context *context);
+/**
+ * Unregisters command @c name from the given context, @c cmd_ctx.
+ * @param cmd_ctx The context of the registered command.
+ * @param parent The parent of the given command, or NULL.
+ * @param name The name of the command to unregister.
+ * @returns ERROR_OK on success, or an error code.
+ */
+int unregister_command(struct command_context *cmd_ctx,
+		struct command *parent, const char *name);
+/**
+ * Unregisters all commands from the specfied context.
+ * @param cmd_ctx The context that will be cleared of registered commands.
+ * @param parent If given, only clear commands from under this one command.
+ * @returns ERROR_OK on success, or an error code.
+ */
+int unregister_all_commands(struct command_context *cmd_ctx,
+		struct command *parent);
 
 void command_set_output_handler(struct command_context* context,
 		command_output_handler_t output_handler, void *priv);
diff --git a/src/openocd.c b/src/openocd.c
index b7781a6..8e8ceac 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -278,7 +278,7 @@ int openocd_main(int argc, char *argv[])
 	httpd_stop();
 #endif
 
-	unregister_all_commands(cmd_ctx);
+	unregister_all_commands(cmd_ctx, NULL);
 
 	/* free commandline interface */
 	command_done(cmd_ctx);

commit 73c6e3bb18326050acc8908b561443a7b37549bb
Author: Zachary T Welch <zw...@su...>
Date:   Thu Nov 19 07:26:28 2009 -0800

    change command_find helper interface
    
    Avoid requiring double pointers where a single would suffice.

diff --git a/src/helper/command.c b/src/helper/command.c
index ba28784..538c07b 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -205,10 +205,9 @@ static void command_helptext_add(Jim_Obj *cmd_list, const char *help)
  * Find a command by name from a list of commands.
  * @returns The named command if found, or NULL.
  */
-static struct command *command_find(struct command **head, const char *name)
+static struct command *command_find(struct command *head, const char *name)
 {
-	assert(head);
-	for (struct command *cc = *head; cc; cc = cc->next)
+	for (struct command *cc = head; cc; cc = cc->next)
 	{
 		if (strcmp(cc->name, name) == 0)
 			return cc;
@@ -242,7 +241,7 @@ struct command* register_command(struct command_context *context,
 		return NULL;
 
 	struct command **head = parent ? &parent->children : &context->commands;
-	struct command *c = command_find(head, name);
+	struct command *c = command_find(*head, name);
 	if (NULL != c)
 		return c;
 

commit 67c29d9935b023a85056149e2f73288434c25995
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 16:34:34 2009 -0800

    factor script_command argv allocation
    
    Splits argument allocation out from script command, reusing free() code.

diff --git a/src/helper/command.c b/src/helper/command.c
index ba689b0..ba28784 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -75,15 +75,45 @@ void script_debug(Jim_Interp *interp, const char *name,
 	}
 }
 
+static void script_command_args_free(const char **words, unsigned nwords)
+{
+	for (unsigned i = 0; i < nwords; i++)
+		free((void *)words[i]);
+	free(words);
+}
+static const char **script_command_args_alloc(
+		unsigned argc, Jim_Obj *const *argv, unsigned *nwords)
+{
+	const char **words = malloc(argc * sizeof(char *));
+	if (NULL == words)
+		return NULL;
+
+	unsigned i;
+	for (i = 0; i < argc; i++)
+	{
+		int len;
+		const char *w = Jim_GetString(argv[i], &len);
+		/* a comment may end the line early */
+		if (*w == '#')
+			break;
+
+		words[i] = strdup(w);
+		if (words[i] == NULL)
+		{
+			script_command_args_free(words, i);
+			return NULL;
+		}
+	}
+	*nwords = i;
+	return words;
+}
+
 static int script_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
 	/* the private data is stashed in the interp structure */
 	struct command *c;
 	struct command_context *context;
 	int retval;
-	int i;
-	int nwords;
-	char **words;
 
 	/* DANGER!!!! be careful what we invoke here, since interp->cmdPrivData might
 	 * get overwritten by running other Jim commands! Treat it as an
@@ -101,27 +131,10 @@ static int script_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 
 	script_debug(interp, c->name, argc, argv);
 
-	words = malloc(argc * sizeof(char *));
-	for (i = 0; i < argc; i++)
-	{
-		int len;
-		const char *w = Jim_GetString(argv[i], &len);
-		if (*w=='#')
-		{
-			/* hit an end of line comment */
-			break;
-		}
-		words[i] = strdup(w);
-		if (words[i] == NULL)
-		{
-			int j;
-			for (j = 0; j < i; j++)
-				free(words[j]);
-			free(words);
-			return JIM_ERR;
-		}
-	}
-	nwords = i;
+	unsigned nwords;
+	const char **words = script_command_args_alloc(argc, argv, &nwords);
+	if (NULL == words)
+		return JIM_ERR;
 
 	/* grab the command context from the associated data */
 	context = Jim_GetAssocData(interp, "context");
@@ -148,9 +161,7 @@ static int script_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	Jim_SetResult(interp, tclOutput);
 	Jim_DecrRefCount(interp, tclOutput);
 
-	for (i = 0; i < nwords; i++)
-		free(words[i]);
-	free(words);
+	script_command_args_free(words, nwords);
 
 	int *return_retval = Jim_GetAssocData(interp, "retval");
 	if (return_retval != NULL)

-----------------------------------------------------------------------

Summary of changes:
 src/helper/command.c   |  393 ++++++++++++++++++++++++++++++------------------
 src/helper/command.h   |   52 ++++++-
 src/helper/startup.tcl |   80 ++++-------
 src/openocd.c          |    2 +-
 4 files changed, 324 insertions(+), 203 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-500-g7b77b3c

From: David B. <dbr...@us...> - 2009-11-20 21:22:28

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  7b77b3c5d1a20793cc2057a96e67d8f7ca20e4cb (commit)
      from  153848e6cc79241a8da51c1b601c13722b5380a6 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 7b77b3c5d1a20793cc2057a96e67d8f7ca20e4cb
Author: David Brownell <dbr...@us...>
Date:   Fri Nov 20 12:21:00 2009 -0800

    target.cfg: TAP id for Hilscher netX 500
    
    Based on email from "Martin Kaul <mar...@le...>".
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/NEWTAPS b/NEWTAPS
index c923082..2fc6f12 100644
--- a/NEWTAPS
+++ b/NEWTAPS
@@ -135,3 +135,11 @@ For example: A consumer GPS unit or a cellphone
     ie: An FPGA or CPLD ...
 
 ========================================
+
+(I) What target config files need updating?
+
+    In fact it's best if you submit a patch with those
+    updates.  Most of the other information listed here
+    is just to help create a good patch.
+
+========================================
diff --git a/tcl/target/netx500.cfg b/tcl/target/netx500.cfg
index 66f4a2e..90315af 100644
--- a/tcl/target/netx500.cfg
+++ b/tcl/target/netx500.cfg
@@ -1,6 +1,5 @@
 #Hilscher netX 500 CPU
 
-
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
 } else {
@@ -16,19 +15,18 @@ if { [info exists ENDIAN] } {
 if { [info exists CPUTAPID ] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
-   set _CPUTAPID 0xffffffff
+   set _CPUTAPID 0x07926021
 }
 
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
+# FIXME most reset config belongs in board code
 reset_config trst_and_srst
-#jtag scan chain
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 jtag_nsrst_delay 100
 jtag_ntrst_delay 100
 
+# jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# that TAP is associated with a target
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
 

-----------------------------------------------------------------------

Summary of changes:
 NEWTAPS                |    8 ++++++++
 tcl/target/netx500.cfg |   16 +++++++---------
 2 files changed, 15 insertions(+), 9 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-499-g153848e

From: Zach W. <zw...@us...> - 2009-11-20 16:13:28

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  153848e6cc79241a8da51c1b601c13722b5380a6 (commit)
      from  a1777fc6493b4c1879ef133c565327212859d37c (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 153848e6cc79241a8da51c1b601c13722b5380a6
Author: Zachary T Welch <zw...@su...>
Date:   Thu Nov 19 18:11:30 2009 -0800

    fix flash/nand name parsing
    
    Start driver.num check from end, and make sure the numeric part is
    actually a number.  Fix problems trying to parse bank names.

diff --git a/src/flash/common.c b/src/flash/common.c
index 253ed9d..072e691 100644
--- a/src/flash/common.c
+++ b/src/flash/common.c
@@ -25,9 +25,11 @@
 
 unsigned get_flash_name_index(const char *name)
 {
-	const char *index = strchr(name, '.');
+	const char *index = strrchr(name, '.');
 	if (NULL == index)
 		return 0;
+	if (index[1] < '0' || index[1] > '9')
+		return ~0U;
 	unsigned requested;
 	int retval = parse_uint(index + 1, &requested);
 	// detect parsing error by forcing past end of bank list

-----------------------------------------------------------------------

Summary of changes:
 src/flash/common.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-498-ga1777fc

From: David B. <dbr...@us...> - 2009-11-20 04:03:29

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a1777fc6493b4c1879ef133c565327212859d37c (commit)
       via  d7760352e8044e8eb8cd9b381574e34093e1f26f (commit)
       via  71cde5e359f273585880ea8986709b950ba85b08 (commit)
      from  31fb7788a605fe1c0c405444b5bab51a7e42d481 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit a1777fc6493b4c1879ef133c565327212859d37c
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 19:03:12 2009 -0800

    Cortex-A8: better context restore
    
    The previous version never wrote dirty registers
    for non-current CPU modes ... fix that.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 01b7aee..168fe12 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -531,7 +531,7 @@ static int cortex_a8_resume(struct target *target, int current,
 			armv4_5->core_mode, 15).valid = 1;
 
 	cortex_a8_restore_context(target);
-//	arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
+
 #if 0
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
@@ -850,30 +850,84 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
 static int cortex_a8_restore_context(struct target *target)
 {
-	int i;
 	uint32_t value;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct reg_cache *cache = armv7a->armv4_5_common.core_cache;
+	unsigned max = cache->num_regs;
+	struct reg *r;
+	bool flushed, flush_cpsr = false;
 
 	LOG_DEBUG(" ");
 
 	if (armv7a->pre_restore_context)
 		armv7a->pre_restore_context(target);
 
-	for (i = 15; i >= 0; i--)
-	{
-		if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, i).dirty)
-		{
-			value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
-						armv4_5->core_cache,
-						armv4_5->core_mode, i).value,
-					0, 32);
+	/* Flush all dirty registers from the cache, one mode at a time so
+	 * that we write CPSR as little as possible.  Save CPSR and R0 for
+	 * last; they're used to change modes and write other registers.
+	 *
+	 * REVISIT be smarter:  save eventual mode for last loop, don't
+	 * need to write CPSR an extra time.
+	 */
+	do {
+		enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+		unsigned i;
+
+		flushed = false;
+
+		/* write dirty non-{R0,CPSR} registers sharing the same mode */
+		for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
+			struct armv4_5_core_reg *reg;
+
+			if (!r->dirty || i == ARMV4_5_CPSR)
+				continue;
+			reg = r->arch_info;
+
 			/* TODO Check return values */
-			cortex_a8_dap_write_coreregister_u32(target, value, i);
+
+			/* Pick a mode and update CPSR; else ignore this
+			 * register if it's for a different mode than what
+			 * we're handling on this pass.
+			 *
+			 * REVISIT don't distinguish SYS and USR modes.
+			 *
+			 * FIXME if we restore from FIQ mode, R8..R12 will
+			 * get wrongly flushed onto FIQ shadows...
+			 */
+			if (mode == ARMV4_5_MODE_ANY) {
+				mode = reg->mode;
+				if (mode != ARMV4_5_MODE_ANY) {
+					cortex_a8_dap_write_coreregister_u32(
+							target, mode, 16);
+					flush_cpsr = true;
+				}
+			} else if (mode != reg->mode)
+				continue;
+
+			/* Write this register */
+			value = buf_get_u32(r->value, 0, 32);
+			cortex_a8_dap_write_coreregister_u32(target, value,
+					(reg->num == 16) ? 17 : reg->num);
+			r->dirty = false;
+			flushed = true;
 		}
+
+	} while (flushed);
+
+	/* now flush CPSR if needed ... */
+	r = cache->reg_list + ARMV4_5_CPSR;
+	if (flush_cpsr || r->dirty) {
+		value = buf_get_u32(r->value, 0, 32);
+		cortex_a8_dap_write_coreregister_u32(target, value, 16);
+		r->dirty = false;
 	}
 
+	/* ... and R0 always (it was dirtied when we saved context) */
+	r = cache->reg_list + 0;
+	value = buf_get_u32(r->value, 0, 32);
+	cortex_a8_dap_write_coreregister_u32(target, value, 0);
+	r->dirty = false;
+
 	if (armv7a->post_restore_context)
 		armv7a->post_restore_context(target);
 

commit d7760352e8044e8eb8cd9b381574e34093e1f26f
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 19:03:02 2009 -0800

    Cortex-A8: mode support
    
    We *should* be able to read and write registers in any core mode,
    instead of being stuck with whatever mode the core was when we
    entered debug state.  This patch makes them work.
    
    Note that the current restore_context() only handles the current
    mode; writing to other-mode registers is a NOP without a followup
    patch fixing that.  Also, that SPSR access needed some bugfixes;
    it was confused with CPSR.
    
    Secure monitor mode also seems dubious; there's probably more to
    be done before that's sufficiently understood by the debugger.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index d02fee9..01b7aee 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -237,7 +237,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
-	if (reg > 16)
+	if (reg > 17)
 		return retval;
 
 	if (reg < 15)
@@ -251,10 +251,12 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 		cortex_a8_exec_opcode(target, 0xE1A0000F);
 		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
 	}
-	else if (reg == 16)
+	else
 	{
-		/* "MRS r0, CPSR"; then move r0 to DCCTX */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
+		/* "MRS r0, CPSR" or "MRS r0, SPSR"
+		 * then move r0 to DCCTX
+		 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1));
 		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
 	}
 
@@ -268,11 +270,13 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 
 	retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRTX, value);
+	LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
 
 	return retval;
 }
 
-static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+		uint32_t value, int regnum)
 {
 	int retval = ERROR_OK;
 	uint8_t Rd = regnum&0xFF;
@@ -292,29 +296,39 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t
 		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
 	}
 
-	if (Rd > 16)
+	if (Rd > 17)
 		return retval;
 
 	/* Write to DCCRX */
+	LOG_DEBUG("write DCC 0x%08" PRIx32, value);
 	retval = mem_ap_write_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRRX, value);
 
 	if (Rd < 15)
 	{
-		/* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+		/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
 		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
 	}
 	else if (Rd == 15)
 	{
+		/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+		 * then "mov r15, r0"
+		 */
 		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
 		cortex_a8_exec_opcode(target, 0xE1A0F000);
 	}
-	else if (Rd == 16)
+	else
 	{
+		/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+		 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
+		 */
 		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-		cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
-		/* Execute a PrefetchFlush instruction through the ITR. */
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+		cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1));
+
+		/* "Prefetch flush" after modifying execution status in CPSR */
+		if (Rd == 16)
+			cortex_a8_exec_opcode(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
 	}
 
 	return retval;
@@ -950,28 +964,64 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
 #endif
 
 
+static int cortex_a8_write_core_reg(struct target *target, int num,
+		enum armv4_5_mode mode, uint32_t value);
+
 static int cortex_a8_read_core_reg(struct target *target, int num,
 		enum armv4_5_mode mode)
 {
 	uint32_t value;
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	struct reg_cache *cache = armv4_5->core_cache;
+	uint32_t cpsr = 0;
+	unsigned cookie = num;
 
-	/* FIXME cortex may not be in "mode" ... */
-
-	cortex_a8_dap_read_coreregister_u32(target, &value, num);
+	/* avoid some needless mode changes
+	 * FIXME move some of these to shared ARM code...
+	 */
+	if (mode != armv4_5->core_mode) {
+		if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+				&& (mode == ARMV4_5_MODE_USR))
+			mode = ARMV4_5_MODE_ANY;
+		else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+			mode = ARMV4_5_MODE_ANY;
+
+		if (mode != ARMV4_5_MODE_ANY) {
+			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
+					.value, 0, 32);
+			cortex_a8_write_core_reg(target, 16,
+					ARMV4_5_MODE_ANY, mode);
+		}
+	}
 
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		return retval;
+	if (num == 16) {
+		switch (mode) {
+		case ARMV4_5_MODE_USR:
+		case ARMV4_5_MODE_SYS:
+		case ARMV4_5_MODE_ANY:
+			/* CPSR */
+			break;
+		default:
+			/* SPSR */
+			cookie++;
+			break;
+		}
 	}
 
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-			mode, num).value, 0, 32, value);
+	cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
+	retval = jtag_execute_queue();
+	if (retval == ERROR_OK) {
+		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
 
-	return ERROR_OK;
+		r->valid = 1;
+		r->dirty = 0;
+		buf_set_u32(r->value, 0, 32, value);
+	}
+
+	if (cpsr)
+		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+	return retval;
 }
 
 static int cortex_a8_write_core_reg(struct target *target, int num,
@@ -979,19 +1029,55 @@ static int cortex_a8_write_core_reg(struct target *target, int num,
 {
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	struct reg_cache *cache = armv4_5->core_cache;
+	uint32_t cpsr = 0;
+	unsigned cookie = num;
 
-	/* FIXME cortex may not be in "mode" ... */
+	/* avoid some needless mode changes
+	 * FIXME move some of these to shared ARM code...
+	 */
+	if (mode != armv4_5->core_mode) {
+		if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+				&& (mode == ARMV4_5_MODE_USR))
+			mode = ARMV4_5_MODE_ANY;
+		else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+			mode = ARMV4_5_MODE_ANY;
+
+		if (mode != ARMV4_5_MODE_ANY) {
+			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
+					.value, 0, 32);
+			cortex_a8_write_core_reg(target, 16,
+					ARMV4_5_MODE_ANY, mode);
+		}
+	}
 
-	cortex_a8_dap_write_coreregister_u32(target, value, num);
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		return retval;
+
+	if (num == 16) {
+		switch (mode) {
+		case ARMV4_5_MODE_USR:
+		case ARMV4_5_MODE_SYS:
+		case ARMV4_5_MODE_ANY:
+			/* CPSR */
+			break;
+		default:
+			/* SPSR */
+			cookie++;
+			break;
+		}
 	}
 
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+	cortex_a8_dap_write_coreregister_u32(target, value, cookie);
+	if ((retval = jtag_execute_queue()) == ERROR_OK) {
+		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
 
-	return ERROR_OK;
+		buf_set_u32(r->value, 0, 32, value);
+		r->valid = 1;
+		r->dirty = 0;
+	}
+
+	if (cpsr)
+		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+	return retval;
 }
 
 

commit 71cde5e359f273585880ea8986709b950ba85b08
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 19:02:10 2009 -0800

    target: create/use register_cache_invalidate()
    
    Create a generic register_cache_invalidate(), and use it to
    replace three all-but-identical core-specific routines:
    
     - armv4_5_invalidate_core_regs()
     - armv7m_invalidate_core_regs
     - mips32_invalidate_core_regs() too.
    
    Make cache->num_regs be unsigned, avoiding various errors.
    
    Net code shrink and simplification.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index eb4b038..1c85417 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1040,7 +1040,7 @@ int arm7_9_assert_reset(struct target *target)
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
 
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
 
 	if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
 	{
@@ -1224,10 +1224,7 @@ int arm7_9_soft_reset_halt(struct target *target)
 	}
 
 	/* all register content is now invalid */
-	if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
-	{
-		return retval;
-	}
+	register_cache_invalidate(armv4_5->core_cache);
 
 	/* SVC, ARM state, IRQ and FIQ disabled */
 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
@@ -1921,7 +1918,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
 	if (!debug_execution)
 	{
 		/* registers are now invalid */
-		armv4_5_invalidate_core_regs(target);
+		register_cache_invalidate(armv4_5->core_cache);
 		target->state = TARGET_RUNNING;
 		if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
 		{
@@ -2064,7 +2061,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 	arm7_9->disable_single_step(target);
 
 	/* registers are now invalid */
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(armv4_5->core_cache);
 
 	if (err != ERROR_OK)
 	{
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 44e5b0a..f8ab153 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -436,22 +436,6 @@ static const struct reg_arch_type arm_reg_type = {
 	.set = armv4_5_set_core_reg,
 };
 
-/** Marks the contents of the register cache as invalid (and clean). */
-int armv4_5_invalidate_core_regs(struct target *target)
-{
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	unsigned num_regs = armv4_5->core_cache->num_regs;
-	struct reg *reg = armv4_5->core_cache->reg_list;
-
-	for (unsigned i = 0; i < num_regs; i++, reg++) {
-		reg->valid = 0;
-		reg->dirty = 0;
-	}
-
-	/* FIXME don't bother returning a value then */
-	return ERROR_OK;
-}
-
 struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
 {
 	int num_regs = ARRAY_SIZE(arm_core_regs);
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 50af57b..dbd62c0 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -162,8 +162,6 @@ int armv4_5_run_algorithm(struct target *target,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info);
 
-int armv4_5_invalidate_core_regs(struct target *target);
-
 int arm_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *checksum);
 int arm_blank_check_memory(struct target *target,
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 56fbb05..88ff6f2 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -246,21 +246,6 @@ static int armv7m_write_core_reg(struct target *target, unsigned num)
 	return ERROR_OK;
 }
 
-/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
-int armv7m_invalidate_core_regs(struct target *target)
-{
-	struct armv7m_common *armv7m = target_to_armv7m(target);
-	int i;
-
-	for (i = 0; i < armv7m->core_cache->num_regs; i++)
-	{
-		armv7m->core_cache->reg_list[i].valid = 0;
-		armv7m->core_cache->reg_list[i].dirty = 0;
-	}
-
-	return ERROR_OK;
-}
-
 /**
  * Returns generic ARM userspace registers to GDB.
  * GDB doesn't quite understand that most ARMs don't have floating point
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index c0a7466..d02fee9 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -545,7 +545,7 @@ static int cortex_a8_resume(struct target *target, int current,
 	target->state = TARGET_RUNNING;
 
 	/* registers are now invalid */
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(armv4_5->core_cache);
 
 	if (!debug_execution)
 	{
@@ -1182,11 +1182,12 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 
 static int cortex_a8_assert_reset(struct target *target)
 {
+	struct armv7a_common *armv7a = target_to_armv7a(target);
 
 	LOG_DEBUG(" ");
 
 	/* registers are now invalid */
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(armv7a->armv4_5_common.core_cache);
 
 	target->state = TARGET_RESET;
 
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index e7b5110..8279a8b 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
 	}
 	swjdp_transaction_endcheck(swjdp);
 
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	/* make sure we have latest dhcsr flags */
 	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -510,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
 	target->state = TARGET_RESET;
 
 	/* registers are now invalid */
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	while (timeout < 100)
 	{
@@ -617,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
 	target->debug_reason = DBG_REASON_NOTHALTED;
 
 	/* registers are now invalid */
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(armv7m->core_cache);
+
 	if (!debug_execution)
 	{
 		target->state = TARGET_RUNNING;
@@ -673,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
 	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
 	/* registers are now invalid */
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	if (breakpoint)
 		cortex_m3_set_breakpoint(target, breakpoint);
@@ -812,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
 
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	if (target->reset_halt)
 	{
diff --git a/src/target/etm.c b/src/target/etm.c
index 85cc6eb..1678c2f 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -234,7 +234,7 @@ static const struct reg_arch_type etm_scan6_type = {
 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 {
 	struct reg_cache *cache = etm_ctx->reg_cache;
-	int i;
+	unsigned i;
 
 	for (i = 0; i < cache->num_regs; i++) {
 		struct etm_reg *reg = cache->reg_list[i].arch_info;
diff --git a/src/target/mips32.c b/src/target/mips32.c
index f986079..0b8ebb4 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -175,21 +175,6 @@ int mips32_write_core_reg(struct target *target, int num)
 	return ERROR_OK;
 }
 
-int mips32_invalidate_core_regs(struct target *target)
-{
-	/* get pointers to arch-specific information */
-	struct mips32_common *mips32 = target->arch_info;
-	int i;
-
-	for (i = 0; i < mips32->core_cache->num_regs; i++)
-	{
-		mips32->core_cache->reg_list[i].valid = 0;
-		mips32->core_cache->reg_list[i].dirty = 0;
-	}
-
-	return ERROR_OK;
-}
-
 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 {
 	/* get pointers to arch-specific information */
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 1ac682b..7d1928e 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -147,7 +147,6 @@ int mips32_examine(struct target *target);
 
 int mips32_register_commands(struct command_context *cmd_ctx);
 
-int mips32_invalidate_core_regs(struct target *target);
 int mips32_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
 
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 864ede0..0a566c3 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -309,7 +309,7 @@ int mips_m4k_assert_reset(struct target *target)
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
 
-	mips32_invalidate_core_regs(target);
+	register_cache_invalidate(mips32->core_cache);
 
 	if (target->reset_halt)
 	{
@@ -410,7 +410,7 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha
 	target->debug_reason = DBG_REASON_NOTHALTED;
 
 	/* registers are now invalid */
-	mips32_invalidate_core_regs(target);
+	register_cache_invalidate(mips32->core_cache);
 
 	if (!debug_execution)
 	{
@@ -467,7 +467,7 @@ int mips_m4k_step(struct target *target, int current, uint32_t address, int hand
 	mips_ejtag_exit_debug(ejtag_info);
 
 	/* registers are now invalid */
-	mips32_invalidate_core_regs(target);
+	register_cache_invalidate(mips32->core_cache);
 
 	if (breakpoint)
 		mips_m4k_set_breakpoint(target, breakpoint);
diff --git a/src/target/register.c b/src/target/register.c
index d9ef53e..392455d 100644
--- a/src/target/register.c
+++ b/src/target/register.c
@@ -28,11 +28,20 @@
 #include "register.h"
 #include "log.h"
 
+/**
+ * @file
+ * Holds utilities to work with register caches.
+ *
+ * OpenOCD uses machine registers internally, and exposes them by name
+ * to Tcl scripts.  Sets of related registers are grouped into caches.
+ * For example, a CPU core will expose a set of registers, and there
+ * may be separate registers associated with debug or trace modules.
+ */
 
 struct reg* register_get_by_name(struct reg_cache *first,
 		const char *name, bool search_all)
 {
-	int i;
+	unsigned i;
 	struct reg_cache *cache = first;
 
 	while (cache)
@@ -65,6 +74,17 @@ struct reg_cache** register_get_last_cache_p(struct reg_cache **first)
 	return cache_p;
 }
 
+/** Marks the contents of the register cache as invalid (and clean). */
+void register_cache_invalidate(struct reg_cache *cache)
+{
+	struct reg *reg = cache->reg_list;
+
+	for (unsigned n = cache->num_regs; n != 0; n--, reg++) {
+		reg->valid = 0;
+		reg->dirty = 0;
+	}
+}
+
 static int register_get_dummy_core_reg(struct reg *reg)
 {
 	return ERROR_OK;
diff --git a/src/target/register.h b/src/target/register.h
index c14dfd4..0f8f2f4 100644
--- a/src/target/register.h
+++ b/src/target/register.h
@@ -41,7 +41,7 @@ struct reg_cache
 	char *name;
 	struct reg_cache *next;
 	struct reg *reg_list;
-	int num_regs;
+	unsigned num_regs;
 };
 
 struct reg_arch_type
@@ -53,6 +53,7 @@ struct reg_arch_type
 struct reg* register_get_by_name(struct reg_cache *first,
 		const char *name, bool search_all);
 struct reg_cache** register_get_last_cache_p(struct reg_cache **first);
+void register_cache_invalidate(struct reg_cache *cache);
 
 void register_init_dummy(struct reg *reg);
 
diff --git a/src/target/target.c b/src/target/target.c
index f203913..70fd8f2 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1860,7 +1860,7 @@ COMMAND_HANDLER(handle_reg_command)
 {
 	struct target *target;
 	struct reg *reg = NULL;
-	int count = 0;
+	unsigned count = 0;
 	char *value;
 
 	LOG_DEBUG("-");
@@ -1875,7 +1875,7 @@ COMMAND_HANDLER(handle_reg_command)
 		count = 0;
 		while (cache)
 		{
-			int i;
+			unsigned i;
 
 			command_print(CMD_CTX, "===== %s", cache->name);
 
@@ -1917,10 +1917,10 @@ COMMAND_HANDLER(handle_reg_command)
 		count = 0;
 		while (cache)
 		{
-			int i;
+			unsigned i;
 			for (i = 0; i < cache->num_regs; i++)
 			{
-				if (count++ == (int)num)
+				if (count++ == num)
 				{
 					reg = &cache->reg_list[i];
 					break;
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 28f89f1..f13366a 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1322,7 +1322,7 @@ static int xscale_resume(struct target *target, int current,
 	if (!debug_execution)
 	{
 		/* registers are now invalid */
-		armv4_5_invalidate_core_regs(target);
+		register_cache_invalidate(armv4_5->core_cache);
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 	}
@@ -1401,8 +1401,7 @@ static int xscale_step_inner(struct target *target, int current,
 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
 	/* registers are now invalid */
-	if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
-		return retval;
+	register_cache_invalidate(armv4_5->core_cache);
 
 	/* wait for and process debug entry */
 	if ((retval = xscale_debug_entry(target)) != ERROR_OK)
@@ -1538,7 +1537,7 @@ static int xscale_deassert_reset(struct target *target)
 		breakpoint = breakpoint->next;
 	}
 
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(xscale->armv4_5_common.core_cache);
 
 	/* FIXME mark hardware watchpoints got unset too.  Also,
 	 * at least some of the XScale registers are invalid...

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm7_9_common.c |   11 +--
 src/target/armv4_5.c       |   16 ---
 src/target/armv4_5.h       |    2 -
 src/target/armv7m.c        |   15 ---
 src/target/cortex_a8.c     |  231 +++++++++++++++++++++++++++++++++++---------
 src/target/cortex_m3.c     |   11 +-
 src/target/etm.c           |    2 +-
 src/target/mips32.c        |   15 ---
 src/target/mips32.h        |    1 -
 src/target/mips_m4k.c      |    6 +-
 src/target/register.c      |   22 ++++-
 src/target/register.h      |    3 +-
 src/target/target.c        |    8 +-
 src/target/xscale.c        |    7 +-
 14 files changed, 230 insertions(+), 120 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-495-g31fb778

From: Zach W. <zw...@us...> - 2009-11-20 00:36:12

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  31fb7788a605fe1c0c405444b5bab51a7e42d481 (commit)
      from  4b18ef15a36a8b618c18ab18d0ed8596ecf9eaaa (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 31fb7788a605fe1c0c405444b5bab51a7e42d481
Author: Dean Glazeski <dn...@gm...>
Date:   Thu Nov 19 17:12:23 2009 -0600

    NAND verify doesn't advance.
    
    Fix to move the device address up as the contents are verified.
    
    Signed-off-by: Zachary T Welch <zw...@su...>

diff --git a/src/flash/nand.c b/src/flash/nand.c
index 2085028..77aa3e5 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -1620,7 +1620,7 @@ COMMAND_HANDLER(handle_nand_verify_command)
 		}
 
 		file.size -= bytes_read;
-		file.address += nand->page_size;
+		dev.address += nand->page_size;
 	}
 
 	if (nand_fileio_finish(&file) == ERROR_OK)

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-494-g4b18ef1

From: Zach W. <zw...@us...> - 2009-11-19 23:37:36

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4b18ef15a36a8b618c18ab18d0ed8596ecf9eaaa (commit)
       via  3e1f5e7c64ea545f6e87b5fa1adb0c00358be505 (commit)
       via  664ba309d5dac2532c83fed441d14f93c7381d62 (commit)
       via  59d4466b551e89077e41b0dba21c7a95db9c7b0a (commit)
       via  2dfa5e9c844a5a3f8aaca146c874f13570b8f667 (commit)
       via  fd654c8a3e3dbd5ab97eb6b3834ee462dd509a66 (commit)
       via  dd44ae18b49f6cb54a4c361e9fab70f4d0fafeec (commit)
       via  ff25e76bad7e57da4ebd363f1b35d4af04acaa67 (commit)
       via  870b8c04557f0b7441cc502debaf537984d77e2a (commit)
      from  8f446fcf676e9cd13cf53d9946f0cae5d29a10ec (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 4b18ef15a36a8b618c18ab18d0ed8596ecf9eaaa
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 03:16:37 2009 -0800

    document new flash syntax
    
    Updates the user documentation with the new syntax for defining
    flash and nand banks.

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 2767d78..0253dc0 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3540,7 +3540,7 @@ board by (re)installing working boot firmware.
 @section Flash Configuration Commands
 @cindex flash configuration
 
-@deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
+@deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
 Configures a flash bank which provides persistent storage
 for addresses from @math{base} to @math{base + size - 1}.
 These banks will often be visible to GDB through the target's memory map.
@@ -3548,6 +3548,8 @@ In some cases, configuring a flash bank will activate extra commands;
 see the driver-specific documentation.
 
 @itemize @bullet
+@item @var{name} ... may be used to reference the flash bank
+in other flash commands.
 @item @var{driver} ... identifies the controller driver
 associated with the flash bank being declared.
 This is usually @code{cfi} for external flash, or else
@@ -4456,7 +4458,7 @@ NAND chips must be declared in configuration scripts,
 plus some additional configuration that's done after
 OpenOCD has initialized.
 
-@deffn {Config Command} {nand device} controller target [configparams...]
+@deffn {Config Command} {nand device} name controller target [configparams...]
 Declares a NAND device, which can be read and written to
 after it has been configured through @command{nand probe}.
 In OpenOCD, devices are single chips; this is unlike some
@@ -4470,6 +4472,8 @@ initialization has completed.  Use it in board specific
 configuration files, not interactively.
 
 @itemize @bullet
+@item @var{name} ... may be used to reference the NAND bank
+in other commands.
 @item @var{controller} ... identifies the controller driver
 associated with the NAND device being declared.
 @xref{NAND Driver List}.

commit 3e1f5e7c64ea545f6e87b5fa1adb0c00358be505
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 02:19:35 2009 -0800

    update 'nand device' usage in scripts
    
    Add $_FLASHNAME variable to update 'nand device' command syntax.

diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 8b126fa..1f814b2 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -191,8 +191,10 @@ proc dm355evm_init {} {
 # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
 # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
 # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
-nand device davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
-nand device davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
+set _FLASHNAME $_CHIPNAME.boot
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
 
 # FIXME
 #  - support writing UBL with its header (new layout only with new ROMs)
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index a77dcdb..e8784d4 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -11,7 +11,8 @@ $_TARGETNAME configure \
 arm7_9 dcc_downloads enable
 
 # this assumes the hardware default peripherals location before u-Boot moves it
-nand device orion 0 0xd8000000
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME orion 0 0xd8000000
 
 proc openrd_init { } {
 
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index 62b78ee..afd621a 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -11,7 +11,8 @@ $_TARGETNAME configure \
 arm7_9 dcc_downloads enable
 
 # this assumes the hardware default peripherals location before u-Boot moves it
-nand device orion 0 0xd8000000
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME orion 0 0xd8000000
 
 proc sheevaplug_init { } {
 

commit 664ba309d5dac2532c83fed441d14f93c7381d62
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 14:11:24 2009 -0800

    add support for naming NAND banks
    
    Requires users to name their nand banks, allowing them to be used
    instead of bank numbers in script commands.

diff --git a/src/flash/nand.c b/src/flash/nand.c
index 70b14b0..2085028 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -212,7 +212,7 @@ COMMAND_HANDLER(handle_nand_list_drivers)
 	return ERROR_OK;
 }
 
-static COMMAND_HELPER(create_nand_device,
+static COMMAND_HELPER(create_nand_device, const char *bank_name,
 		struct nand_flash_controller *controller)
 {
 	int retval = controller->register_commands(CMD_CTX);
@@ -221,9 +221,9 @@ static COMMAND_HELPER(create_nand_device,
 		LOG_ERROR("couldn't register '%s' commands", controller->name);
 		return retval;
 	}
-
 	struct nand_device *c = malloc(sizeof(struct nand_device));
 
+	c->name = strdup(bank_name);
 	c->controller = controller;
 	c->controller_priv = NULL;
 	c->manufacturer = NULL;
@@ -260,6 +260,10 @@ COMMAND_HANDLER(handle_nand_device_command)
 		return ERROR_FLASH_BANK_INVALID;
 	}
 
+	// save name and increment (for compatibility) with drivers
+	const char *bank_name = *CMD_ARGV++;
+	CMD_ARGC--;
+
 	const char *driver_name = CMD_ARGV[0];
 	for (unsigned i = 0; nand_flash_controllers[i]; i++)
 	{
@@ -267,7 +271,8 @@ COMMAND_HANDLER(handle_nand_device_command)
 		if (strcmp(driver_name, controller->name) != 0)
 			continue;
 
-		return CALL_COMMAND_HANDLER(create_nand_device, controller);
+		return CALL_COMMAND_HANDLER(create_nand_device,
+				bank_name, controller);
 	}
 
 	LOG_ERROR("No valid NAND flash driver found (%s)", driver_name);
@@ -297,6 +302,8 @@ struct nand_device *get_nand_device_by_name(const char *name)
 	struct nand_device *nand;
 	for (nand = nand_devices; NULL != nand; nand = nand->next)
 	{
+		if (strcmp(nand->name, name) == 0)
+			return nand;
 		if (!flash_driver_name_matches(nand->controller->name, name))
 			continue;
 		if (++found < requested)
diff --git a/src/flash/nand.h b/src/flash/nand.h
index d38ed67..af52c77 100644
--- a/src/flash/nand.h
+++ b/src/flash/nand.h
@@ -75,6 +75,7 @@ struct nand_ecclayout {
 
 struct nand_device
 {
+	char *name;
 	struct nand_flash_controller *controller;
 	void *controller_priv;
 	struct nand_manufacturer *manufacturer;

commit 59d4466b551e89077e41b0dba21c7a95db9c7b0a
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 15:14:03 2009 -0800

    refactor handle_nand_device_command
    
    Move bulk of for-loop to a new static command helper function.
    
    Adds handle_nand_list_drivers command handler, registered as
    'nand drivers'.
    
    Improves command help text and error reporting.

diff --git a/src/flash/nand.c b/src/flash/nand.c
index 3518056..70b14b0 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -204,87 +204,87 @@ static struct nand_ecclayout nand_oob_64 = {
 		 .length = 38}}
 };
 
-/* nand device <nand_controller> [controller options]
- */
-COMMAND_HANDLER(handle_nand_device_command)
+COMMAND_HANDLER(handle_nand_list_drivers)
 {
-	int i;
-	int retval;
+	command_print(CMD_CTX, "Available NAND flash controller drivers:");
+	for (unsigned i = 0; nand_flash_controllers[i]; i++)
+		command_print(CMD_CTX, "  %s", nand_flash_controllers[i]->name);
+	return ERROR_OK;
+}
 
-	if (CMD_ARGC < 1)
+static COMMAND_HELPER(create_nand_device,
+		struct nand_flash_controller *controller)
+{
+	int retval = controller->register_commands(CMD_CTX);
+	if (ERROR_OK != retval)
 	{
-		LOG_WARNING("incomplete flash device nand configuration");
-		return ERROR_FLASH_BANK_INVALID;
+		LOG_ERROR("couldn't register '%s' commands", controller->name);
+		return retval;
 	}
 
-	for (i = 0; nand_flash_controllers[i]; i++)
-	{
-		struct nand_device *p, *c;
+	struct nand_device *c = malloc(sizeof(struct nand_device));
 
-		if (strcmp(CMD_ARGV[0], nand_flash_controllers[i]->name) == 0)
-		{
-			/* register flash specific commands */
-			if ((retval = nand_flash_controllers[i]->register_commands(CMD_CTX)) != ERROR_OK)
-			{
-				LOG_ERROR("couldn't register '%s' commands", CMD_ARGV[0]);
-				return retval;
-			}
+	c->controller = controller;
+	c->controller_priv = NULL;
+	c->manufacturer = NULL;
+	c->device = NULL;
+	c->bus_width = 0;
+	c->address_cycles = 0;
+	c->page_size = 0;
+	c->use_raw = 0;
+	c->next = NULL;
 
-			c = malloc(sizeof(struct nand_device));
+	retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c);
+	if (ERROR_OK != retval)
+	{
+		LOG_ERROR("'%s' driver rejected nand flash", controller->name);
+		free(c);
+		return ERROR_OK;
+	}
 
-			c->controller = nand_flash_controllers[i];
-			c->controller_priv = NULL;
-			c->manufacturer = NULL;
-			c->device = NULL;
-			c->bus_width = 0;
-			c->address_cycles = 0;
-			c->page_size = 0;
-			c->use_raw = 0;
-			c->next = NULL;
+	if (nand_devices) {
+		struct nand_device *p = nand_devices;
+		while (p && p->next) p = p->next;
+		p->next = c;
+	} else
+		nand_devices = c;
 
-			retval = CALL_COMMAND_HANDLER(nand_flash_controllers[i]->nand_device_command, c);
-			if (ERROR_OK != retval)
-			{
-				LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
-				free(c);
-				return ERROR_OK;
-			}
-
-			/* put NAND device in linked list */
-			if (nand_devices)
-			{
-				/* find last flash device */
-				for (p = nand_devices; p && p->next; p = p->next);
-				if (p)
-					p->next = c;
-			}
-			else
-			{
-				nand_devices = c;
-			}
+	return ERROR_OK;
+}
 
-			return ERROR_OK;
-		}
+COMMAND_HANDLER(handle_nand_device_command)
+{
+	if (CMD_ARGC < 1)
+	{
+		LOG_ERROR("incomplete nand device configuration");
+		return ERROR_FLASH_BANK_INVALID;
 	}
 
-	/* no valid NAND controller was found (i.e. the configuration option,
-	 * didn't match one of the compiled-in controllers)
-	 */
-	LOG_ERROR("No valid NAND flash controller found (%s)", CMD_ARGV[0]);
-	LOG_ERROR("compiled-in NAND flash controllers:");
-	for (i = 0; nand_flash_controllers[i]; i++)
+	const char *driver_name = CMD_ARGV[0];
+	for (unsigned i = 0; nand_flash_controllers[i]; i++)
 	{
-		LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
+		struct nand_flash_controller *controller = nand_flash_controllers[i];
+		if (strcmp(driver_name, controller->name) != 0)
+			continue;
+
+		return CALL_COMMAND_HANDLER(create_nand_device, controller);
 	}
 
-	return ERROR_OK;
+	LOG_ERROR("No valid NAND flash driver found (%s)", driver_name);
+	return CALL_COMMAND_HANDLER(handle_nand_list_drivers);
 }
 
 int nand_register_commands(struct command_context *cmd_ctx)
 {
-	nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
-
-	register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
+	nand_cmd = register_command(cmd_ctx, NULL, "nand",
+			NULL, COMMAND_ANY, "NAND specific commands");
+
+	register_command(cmd_ctx, nand_cmd, "device",
+			&handle_nand_device_command, COMMAND_CONFIG,
+			"defines a new NAND bank");
+	register_command(cmd_ctx, nand_cmd, "drivers",
+			&handle_nand_list_drivers, COMMAND_ANY,
+			"lists available NAND drivers");
 
 	return ERROR_OK;
 }

commit 2dfa5e9c844a5a3f8aaca146c874f13570b8f667
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 02:15:52 2009 -0800

    update 'flash bank' usage in scripts
    
    Sets $_FLASHNAME to "$_CHIPNAME.flash" and passes it as the
    first argument to 'flash bank'.

diff --git a/tcl/board/balloon3-cpu.cfg b/tcl/board/balloon3-cpu.cfg
index 8a646b7..ecb1a28 100644
--- a/tcl/board/balloon3-cpu.cfg
+++ b/tcl/board/balloon3-cpu.cfg
@@ -10,4 +10,5 @@ reset_config trst_and_srst separate
 
 # flash bank <driver> <base> <size> <chip_width> <bus_width>
 # 29LV650 64Mbit Flash
-flash bank cfi 0x00000000 0x800000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 0
diff --git a/tcl/board/crossbow_tech_imote2.cfg b/tcl/board/crossbow_tech_imote2.cfg
index a7d1215..88d4aa7 100644
--- a/tcl/board/crossbow_tech_imote2.cfg
+++ b/tcl/board/crossbow_tech_imote2.cfg
@@ -9,4 +9,5 @@ jtag_nsrst_delay 800
 reset_config trst_and_srst separate
 
 # works for P30 flash
-flash bank cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index c2c4789..de19660 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -4,7 +4,8 @@
 source [find target/at91rm9200.cfg]
 
 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
-flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
 
 # ETM9 trace port connector present on this board, 16 data pins.
 if { [info exists ETM_DRIVER] } {
diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg
index e6d17bd..3bc26ad 100644
--- a/tcl/board/digi_connectcore_wi-9c.cfg
+++ b/tcl/board/digi_connectcore_wi-9c.cfg
@@ -122,4 +122,5 @@ $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-a
 
 #M29DW323DB - not working
 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x50000000 0x0400000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 0
diff --git a/tcl/board/hammer.cfg b/tcl/board/hammer.cfg
index ed83803..d366a45 100644
--- a/tcl/board/hammer.cfg
+++ b/tcl/board/hammer.cfg
@@ -33,4 +33,5 @@ $_TARGETNAME configure -event reset-init {
 
 #flash configuration
 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x00000000 0x1000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 0
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index d0b2864..7d06f74 100644
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -28,7 +28,8 @@ $_TARGETNAME configure -event reset-start {
 }
 
 # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
-flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
 
 
 $_TARGETNAME configure -event reset-init {
diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg
index e7b7961..968d80e 100644
--- a/tcl/board/hitex_str9-comstick.cfg
+++ b/tcl/board/hitex_str9-comstick.cfg
@@ -68,5 +68,7 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
 
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
diff --git a/tcl/board/lubbock.cfg b/tcl/board/lubbock.cfg
index 63cc2a4..32af386 100644
--- a/tcl/board/lubbock.cfg
+++ b/tcl/board/lubbock.cfg
@@ -12,8 +12,10 @@ jtag_ntrst_delay 250
 
 # CS0, CS1 -- two banks of CFI flash, 32 MBytes each
 # each bank is 32-bits wide, two 16-bit chips in parallel
-flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
-flash bank cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
 
 # CS2 low -- FPGA registers
 # CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
diff --git a/tcl/board/omap2420_h4.cfg b/tcl/board/omap2420_h4.cfg
index c2190b5..12efa05 100644
--- a/tcl/board/omap2420_h4.cfg
+++ b/tcl/board/omap2420_h4.cfg
@@ -8,5 +8,7 @@ reset_config trst_and_srst separate
 # Board configs can vary a *LOT* ... parts, jumpers, etc.
 # This GP board boots from cs0 using NOR (2x32M), and also
 # has 64M NAND on cs6.
-flash bank cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
-flash bank cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
diff --git a/tcl/board/osk5912.cfg b/tcl/board/osk5912.cfg
index d78c6ef..c33ae28 100644
--- a/tcl/board/osk5912.cfg
+++ b/tcl/board/osk5912.cfg
@@ -19,8 +19,10 @@ etm_dummy config $_TARGETNAME
 
 # standard boards populate two 16 MB chips, but manufacturing
 # options or an expansion board could change this config.
-flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
-flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
 
 proc osk5912_init {} {
 	omap5912_reset
diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 8bc691b..ce90387 100644
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -13,7 +13,8 @@ source [find target/pxa255.cfg]
 $_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
 
 # flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
-flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
 
 proc pxa255_sst_init {} {
 	xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
diff --git a/tcl/board/str910-eval.cfg b/tcl/board/str910-eval.cfg
index fa872a9..0cf794a 100644
--- a/tcl/board/str910-eval.cfg
+++ b/tcl/board/str910-eval.cfg
@@ -54,8 +54,10 @@ $_TARGETNAME configure -event reset-init {
 }
 
 #flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg
index c4e5d67..0cbdb81 100644
--- a/tcl/board/telo.cfg
+++ b/tcl/board/telo.cfg
@@ -54,7 +54,8 @@ proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
 # it's really 16MB but the upper 8mb is controller via gpio
 # openocd does not support 'complex reads/writes' to NOR
-flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
 
 # writing data to memory does not work without this
 memwrite burst disable
\ No newline at end of file
diff --git a/tcl/board/topas910.cfg b/tcl/board/topas910.cfg
index ce7c87a..ae72c4b 100644
--- a/tcl/board/topas910.cfg
+++ b/tcl/board/topas910.cfg
@@ -115,4 +115,5 @@ arm7_9 dcc_downloads enable       # Enable faster DCC downloads
 #####################
 
 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x20000000 0x2000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 0
diff --git a/tcl/board/topasa900.cfg b/tcl/board/topasa900.cfg
index a8a6caf..5984f81 100644
--- a/tcl/board/topasa900.cfg
+++ b/tcl/board/topasa900.cfg
@@ -121,5 +121,6 @@ arm7_9 dcc_downloads enable       # Enable faster DCC downloads
 #####################
 
 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x20000000 0x1000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 0
 
diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg
index 2abd367..ad7b13c 100644
--- a/tcl/board/unknown_at91sam9260.cfg
+++ b/tcl/board/unknown_at91sam9260.cfg
@@ -91,6 +91,7 @@ $_TARGETNAME configure -event reset-init {
 #####################
 
 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 0
 
 
diff --git a/tcl/board/x300t.cfg b/tcl/board/x300t.cfg
index 3b09493..d914180 100644
--- a/tcl/board/x300t.cfg
+++ b/tcl/board/x300t.cfg
@@ -8,7 +8,8 @@ $_TARGETNAME configure -event reset-init { x300t_init }
 
 # 1MB CFI capable flash
 # flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank cfi 0xac000000 0x100000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 0
 
 proc x300t_init { } {
 	# Setup SDRAM config and flash mapping
diff --git a/tcl/board/zy1000.cfg b/tcl/board/zy1000.cfg
index 54bb7bb..3f526d0 100644
--- a/tcl/board/zy1000.cfg
+++ b/tcl/board/zy1000.cfg
@@ -38,7 +38,8 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
 
-flash bank ecosflash 0x01000000 0x200000 2 2 $_TARGETNAME ecos/at91eb40a.elf
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME ecosflash 0x01000000 0x200000 2 2 $_TARGETNAME ecos/at91eb40a.elf
 $_TARGETNAME configure -event reset-init {
 	# Set up chip selects & timings
 	mww 0xFFE00000 0x0100273D
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg
index b60c967..58cc9b9 100644
--- a/tcl/target/aduc702x.cfg
+++ b/tcl/target/aduc702x.cfg
@@ -35,7 +35,8 @@ $_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
 
 ## flash configuration
 # only target number is needed
-flash bank aduc702x 0 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME aduc702x 0 0 0 0 0
 
 ## If you use the watchdog, the following code makes sure that the board
 ## doesn't reboot when halted via JTAG.  Yes, on the older generation
diff --git a/tcl/target/at91eb40a.cfg b/tcl/target/at91eb40a.cfg
index 8b3a9ec..e78ccea 100644
--- a/tcl/target/at91eb40a.cfg
+++ b/tcl/target/at91eb40a.cfg
@@ -42,7 +42,8 @@ arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
 
 #flash driver
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
 
 # required for usable performance. Used for lots of
 # other things than flash programming.
diff --git a/tcl/target/at91r40008.cfg b/tcl/target/at91r40008.cfg
index e8710f7..9069ae5 100644
--- a/tcl/target/at91r40008.cfg
+++ b/tcl/target/at91r40008.cfg
@@ -45,7 +45,8 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 
 $_TARGETNAME configure -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
 
-flash bank cfi 0x10000000 0x400000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/at91sam3u1c.cfg b/tcl/target/at91sam3u1c.cfg
index d338f30..47c227b 100644
--- a/tcl/target/at91sam3u1c.cfg
+++ b/tcl/target/at91sam3u1c.cfg
@@ -2,6 +2,7 @@
 source [find target/at91sam3uxx.cfg]
 
 # size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 
 
diff --git a/tcl/target/at91sam3u1e.cfg b/tcl/target/at91sam3u1e.cfg
index d338f30..47c227b 100644
--- a/tcl/target/at91sam3u1e.cfg
+++ b/tcl/target/at91sam3u1e.cfg
@@ -2,6 +2,7 @@
 source [find target/at91sam3uxx.cfg]
 
 # size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 
 
diff --git a/tcl/target/at91sam3u2c.cfg b/tcl/target/at91sam3u2c.cfg
index d338f30..47c227b 100644
--- a/tcl/target/at91sam3u2c.cfg
+++ b/tcl/target/at91sam3u2c.cfg
@@ -2,6 +2,7 @@
 source [find target/at91sam3uxx.cfg]
 
 # size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 
 
diff --git a/tcl/target/at91sam3u2e.cfg b/tcl/target/at91sam3u2e.cfg
index d338f30..47c227b 100644
--- a/tcl/target/at91sam3u2e.cfg
+++ b/tcl/target/at91sam3u2e.cfg
@@ -2,6 +2,7 @@
 source [find target/at91sam3uxx.cfg]
 
 # size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 
 
diff --git a/tcl/target/at91sam3u4c.cfg b/tcl/target/at91sam3u4c.cfg
index e8fdaba..e281287 100644
--- a/tcl/target/at91sam3u4c.cfg
+++ b/tcl/target/at91sam3u4c.cfg
@@ -2,8 +2,10 @@
 source [find target/at91sam3uxx.cfg]
 
 # size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 256K chip, it has the 2nd bank
-flash bank at91sam3 0x000100000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
 
 
diff --git a/tcl/target/at91sam3u4e.cfg b/tcl/target/at91sam3u4e.cfg
index 9477ad0..242b53e 100644
--- a/tcl/target/at91sam3u4e.cfg
+++ b/tcl/target/at91sam3u4e.cfg
@@ -2,8 +2,10 @@
 source [find target/at91sam3uxx.cfg]
 
 # size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 256K chip - it has the 2nd bank
-flash bank at91sam3 0x000100000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
 
 
diff --git a/tcl/target/at91sam7sx.cfg b/tcl/target/at91sam7sx.cfg
index 2a7f90c..f3cc88e 100644
--- a/tcl/target/at91sam7sx.cfg
+++ b/tcl/target/at91sam7sx.cfg
@@ -49,7 +49,8 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index de7e9ab..690406b 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -55,7 +55,8 @@ $_TARGETNAME configure -event reset-deassert-post {at91sam_init}
 
 # Flash configuration
 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
 
 
 proc at91sam_init { } {
diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg
index eaf4ee9..7e4599d 100644
--- a/tcl/target/epc9301.cfg
+++ b/tcl/target/epc9301.cfg
@@ -28,4 +28,5 @@ target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
 
 #flash configuration
 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
diff --git a/tcl/target/faux.cfg b/tcl/target/faux.cfg
index cc09ee3..6fe0cd7 100644
--- a/tcl/target/faux.cfg
+++ b/tcl/target/faux.cfg
@@ -26,4 +26,5 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
 
 #dummy flash driver
-flash bank faux 0x01000000 0x200000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 0
diff --git a/tcl/target/lm3s1968.cfg b/tcl/target/lm3s1968.cfg
index e54bbfe..330bb56 100644
--- a/tcl/target/lm3s1968.cfg
+++ b/tcl/target/lm3s1968.cfg
@@ -25,4 +25,5 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
 
 #flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/lm3s3748.cfg b/tcl/target/lm3s3748.cfg
index 5317a6d..274377a 100644
--- a/tcl/target/lm3s3748.cfg
+++ b/tcl/target/lm3s3748.cfg
@@ -25,4 +25,5 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
 
 # flash configuration -- one bank of 128K
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/lm3s6965.cfg b/tcl/target/lm3s6965.cfg
index f0eb6b0..02d85d4 100644
--- a/tcl/target/lm3s6965.cfg
+++ b/tcl/target/lm3s6965.cfg
@@ -34,4 +34,5 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
 
 #flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/lm3s811.cfg b/tcl/target/lm3s811.cfg
index 8210696..49879d0 100644
--- a/tcl/target/lm3s811.cfg
+++ b/tcl/target/lm3s811.cfg
@@ -25,4 +25,5 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
 
 #flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/lm3s9b9x.cfg b/tcl/target/lm3s9b9x.cfg
index e822bb2..a727251 100644
--- a/tcl/target/lm3s9b9x.cfg
+++ b/tcl/target/lm3s9b9x.cfg
@@ -29,4 +29,5 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x4000
 
 #flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 0b07d51..9a813f5 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -44,7 +44,8 @@ $_TARGETNAME configure -event reset-init {
 # LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
 # flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
 
-flash bank lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
 
 # 4MHz / 6 = 666kHz, so use 500
 jtag_khz 500
diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg
index 0aadee8..13535f5 100644
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -35,4 +35,5 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x2000 -work-a
 
 # 32kB of internal Flash, core clocked with 12MHz crystal
 # flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
-flash bank lpc2000 0x0 0x8000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x8000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 471286b..9a27aec 100644
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -39,4 +39,5 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-a
 
 
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14745 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14745 calc_checksum
diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index a686a47..287fa5d 100644
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -38,4 +38,5 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
 $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index 1f833e7..cf6287c 100644
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -52,4 +52,5 @@ $_TARGETNAME configure -event reset-init {
 }
 
 # flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
-flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME lpc2000_v2 14765 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME lpc2000_v2 14765 calc_checksum
diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg
index a34940e..d43d740 100644
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -32,7 +32,8 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-a
 
 #flash configuration
 #flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
-flash bank lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index aa3fad2..4e50ac5 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -43,7 +43,8 @@ $_TARGETNAME configure -event reset-init {
 # LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
 # After reset the chip uses its internal 4MHz RC oscillator
 #flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
-flash bank lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
 
 # 4MHz / 6 = 666kHz, so use 500
 jtag_khz 500
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index b0af4c0..d0bff1a 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -43,7 +43,8 @@ $_TARGETNAME configure -event reset-init {
 # LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
 # After reset the chip uses its internal 4MHz RC oscillator.
 # flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-flash bank lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
 
 # Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 = 666kHz, so use 500.
 jtag_rclk 500
diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg
index fa5bd5b..2371dd7 100644
--- a/tcl/target/lpc2900.cfg
+++ b/tcl/target/lpc2900.cfg
@@ -62,4 +62,5 @@ arm7_9 dcc_downloads enable
 # Flash bank configuration:
 # Flash:   flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
 # Flash base address, total flash size, and number of sectors are all configured automatically.
-flash bank lpc2900         0 0 0 0 $_TARGETNAME $FLASH_CLOCK
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2900         0 0 0 0 $_TARGETNAME $FLASH_CLOCK
diff --git a/tcl/target/mega128.cfg b/tcl/target/mega128.cfg
index e444889..2bc2294 100644
--- a/tcl/target/mega128.cfg
+++ b/tcl/target/mega128.cfg
@@ -22,7 +22,8 @@ target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
 
 #$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
 
-flash bank avr 0 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 0
 
 #to use it, script will be like:
 #init
diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index 6127a54..a346c47 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -33,8 +33,10 @@ target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAM
 
 $_TARGETNAME configure -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
 
-flash bank pic32mx 0xbd000000 0 0 0 0
-flash bank pic32mx 0xbfc00000 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 0
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/sam7se512.cfg b/tcl/target/sam7se512.cfg
index 0f1e412..d255067 100644
--- a/tcl/target/sam7se512.cfg
+++ b/tcl/target/sam7se512.cfg
@@ -35,5 +35,6 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
 
diff --git a/tcl/target/sam7x256.cfg b/tcl/target/sam7x256.cfg
index c3f7cd9..5bab642 100644
--- a/tcl/target/sam7x256.cfg
+++ b/tcl/target/sam7x256.cfg
@@ -46,7 +46,8 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/smdk6410.cfg b/tcl/target/smdk6410.cfg
index 7f15f8b..dd8bf87 100644
--- a/tcl/target/smdk6410.cfg
+++ b/tcl/target/smdk6410.cfg
@@ -5,4 +5,5 @@
 
 source [find target/samsung_s3c6410.cfg]
 
-flash bank cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe
diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32.cfg
index 242bbbe..463a85c 100644
--- a/tcl/target/stm32.cfg
+++ b/tcl/target/stm32.cfg
@@ -62,7 +62,8 @@ target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNA
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-flash bank stm32x 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index 8e5d36f..395a26c 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -39,8 +39,10 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 $_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank str7x <base> <size> 0 0 <target#> <variant>
-flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
-flash bank str7x 0x400C0000 0x00004000 0 0 0 STR71x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 0 STR71x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 0 STR71x
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index c98d56c..6432d15 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -42,5 +42,6 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 0 STR3x
 
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index 5439c33..496c4e3 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -45,6 +45,8 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x
-flash bank str7x 0x200C0000 0x00004000 0 0 0 STR75x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 0 STR75x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 0 STR75x
 
diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 0dd6848..d844584 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -63,8 +63,10 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
 
 #flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
 
 # For more information about the configuration files, take a look at:
 # openocd.texi
diff --git a/tcl/target/telo.cfg b/tcl/target/telo.cfg
index c4e5d67..0cbdb81 100644
--- a/tcl/target/telo.cfg
+++ b/tcl/target/telo.cfg
@@ -54,7 +54,8 @@ proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
 # it's really 16MB but the upper 8mb is controller via gpio
 # openocd does not support 'complex reads/writes' to NOR
-flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
 
 # writing data to memory does not work without this
 memwrite burst disable
\ No newline at end of file
diff --git a/tcl/target/xba_revA3.cfg b/tcl/target/xba_revA3.cfg
index 9d258a5..fb02c68 100644
--- a/tcl/target/xba_revA3.cfg
+++ b/tcl/target/xba_revA3.cfg
@@ -79,7 +79,8 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
 
 
-flash bank cfi 0x50000000 0x400000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
 
 init
 reset init
diff --git a/tcl/test/syntax1.cfg b/tcl/test/syntax1.cfg
index 40a7c1d..c3d8ed9 100644
--- a/tcl/test/syntax1.cfg
+++ b/tcl/test/syntax1.cfg
@@ -25,5 +25,6 @@ mvb 0xE01FC040 0x01
 
 
 
-flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
 

commit fd654c8a3e3dbd5ab97eb6b3834ee462dd509a66
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 14:04:25 2009 -0800

    add support for naming flash banks
    
    Requires users to name their flash banks, allowing them to be used
    instead of bank numbers in script commands.

diff --git a/src/flash/flash.c b/src/flash/flash.c
index e93aa63..ef6c6da 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -189,6 +189,8 @@ struct flash_bank *get_flash_bank_by_name(const char *name)
 	struct flash_bank *bank;
 	for (bank = flash_banks; NULL != bank; bank = bank->next)
 	{
+		if (strcmp(bank->name, name) == 0)
+			return bank;
 		if (!flash_driver_name_matches(bank->driver->name, name))
 			continue;
 		if (++found < requested)
@@ -239,12 +241,15 @@ COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
 
 COMMAND_HANDLER(handle_flash_bank_command)
 {
-	if (CMD_ARGC < 6)
+	if (CMD_ARGC < 7)
 	{
-		LOG_ERROR("usage: flash bank <driver> "
+		LOG_ERROR("usage: flash bank <name> <driver> "
 				"<base> <size> <chip_width> <bus_width>");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
+	// save bank name and advance arguments for compatibility
+	const char *bank_name = *CMD_ARGV++;
+	CMD_ARGC--;
 
 	struct target *target;
 	if ((target = get_target(CMD_ARGV[5])) == NULL)
@@ -269,6 +274,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
 		}
 
 		c = malloc(sizeof(struct flash_bank));
+		c->name = strdup(bank_name);
 		c->target = target;
 		c->driver = flash_drivers[i];
 		c->driver_priv = NULL;
diff --git a/src/flash/flash.h b/src/flash/flash.h
index 1235a41..ac1600e 100644
--- a/src/flash/flash.h
+++ b/src/flash/flash.h
@@ -240,6 +240,8 @@ struct flash_driver
  */
 struct flash_bank
 {
+	char *name;
+
 	struct target *target; /**< Target to which this bank belongs. */
 
 	struct flash_driver *driver; /**< Driver for this bank. */

commit dd44ae18b49f6cb54a4c361e9fab70f4d0fafeec
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 13:52:43 2009 -0800

    refactor handle_flash_bank_command
    
    Move variables to point of first use, reducing their scope.
    Add driver_name temporary to help arguments be changed later.
    
    Eliminates the useless 'found' variable, changing the code to terminate
    the loop immediate and return its success.

diff --git a/src/flash/flash.c b/src/flash/flash.c
index b960c64..e93aa63 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -239,25 +239,24 @@ COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
 
 COMMAND_HANDLER(handle_flash_bank_command)
 {
-	int retval;
-	int i;
-	int found = 0;
-	struct target *target;
-
 	if (CMD_ARGC < 6)
 	{
+		LOG_ERROR("usage: flash bank <driver> "
+				"<base> <size> <chip_width> <bus_width>");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
+	struct target *target;
 	if ((target = get_target(CMD_ARGV[5])) == NULL)
 	{
 		LOG_ERROR("target '%s' not defined", CMD_ARGV[5]);
 		return ERROR_FAIL;
 	}
 
-	for (i = 0; flash_drivers[i]; i++)
+	const char *driver_name = CMD_ARGV[0];
+	for (unsigned i = 0; flash_drivers[i]; i++)
 	{
-		if (strcmp(CMD_ARGV[0], flash_drivers[i]->name) != 0)
+		if (strcmp(driver_name, flash_drivers[i]->name) != 0)
 			continue;
 
 		struct flash_bank *p, *c;
@@ -265,7 +264,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
 		/* register flash specific commands */
 		if (flash_drivers[i]->register_commands(CMD_CTX) != ERROR_OK)
 		{
-			LOG_ERROR("couldn't register '%s' commands", CMD_ARGV[0]);
+			LOG_ERROR("couldn't register '%s' commands", driver_name);
 			return ERROR_FAIL;
 		}
 
@@ -281,10 +280,12 @@ COMMAND_HANDLER(handle_flash_bank_command)
 		c->sectors = NULL;
 		c->next = NULL;
 
+		int retval;
 		retval = CALL_COMMAND_HANDLER(flash_drivers[i]->flash_bank_command, c);
 		if (ERROR_OK != retval)
 		{
-			LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32 , CMD_ARGV[0], c->base);
+			LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32,
+					driver_name, c->base);
 			free(c);
 			return retval;
 		}
@@ -305,17 +306,12 @@ COMMAND_HANDLER(handle_flash_bank_command)
 			c->bank_number = 0;
 		}
 
-		found = 1;
+		return ERROR_OK;
 	}
 
 	/* no matching flash driver found */
-	if (!found)
-	{
-		LOG_ERROR("flash driver '%s' not found", CMD_ARGV[0]);
-		return ERROR_FAIL;
-	}
-
-	return ERROR_OK;
+	LOG_ERROR("flash driver '%s' not found", driver_name);
+	return ERROR_FAIL;
 }
 
 COMMAND_HANDLER(handle_flash_info_command)

commit ff25e76bad7e57da4ebd363f1b35d4af04acaa67
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 13:07:36 2009 -0800

    rename flash and nand command helpers
    
    After adding support for referencing banks by name, renames
    the COMMAND_HELPERs appropriately:
    flash_command_get_bank_by_num  -> flash_command_get_bank
    nand_command_get_device_by_num -> flash_command_get_device

diff --git a/src/flash/avrf.c b/src/flash/avrf.c
index 20c619d..356c404 100644
--- a/src/flash/avrf.c
+++ b/src/flash/avrf.c
@@ -426,7 +426,7 @@ COMMAND_HANDLER(avrf_handle_mass_erase_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
diff --git a/src/flash/flash.c b/src/flash/flash.c
index 071503f..b960c64 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -216,7 +216,7 @@ struct flash_bank *get_flash_bank_by_num(int num)
 	return p;
 }
 
-COMMAND_HELPER(flash_command_get_bank_by_num, unsigned name_index,
+COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
 		struct flash_bank **bank)
 {
 	const char *name = CMD_ARGV[name_index];
@@ -425,7 +425,7 @@ COMMAND_HANDLER(handle_flash_erase_check_command)
 	}
 
 	struct flash_bank *p;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -513,7 +513,7 @@ COMMAND_HANDLER(handle_flash_protect_check_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	struct flash_bank *p;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -837,7 +837,7 @@ COMMAND_HANDLER(handle_flash_write_bank_command)
 	duration_start(&bench);
 
 	struct flash_bank *p;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
diff --git a/src/flash/flash.h b/src/flash/flash.h
index fb88c35..1235a41 100644
--- a/src/flash/flash.h
+++ b/src/flash/flash.h
@@ -333,7 +333,7 @@ struct flash_bank *get_flash_bank_by_num(int num);
  * @param bank On output, contians a pointer to the bank or NULL.
  * @returns ERROR_OK on success, or an error indicating the problem.
  */
-COMMAND_HELPER(flash_command_get_bank_by_num, unsigned name_index,
+COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
 		struct flash_bank **bank);
 /**
  * Returns the flash bank like get_flash_bank_by_num(), without probing.
diff --git a/src/flash/lpc2000.c b/src/flash/lpc2000.c
index 5442e71..b60c6cf 100644
--- a/src/flash/lpc2000.c
+++ b/src/flash/lpc2000.c
@@ -749,7 +749,7 @@ COMMAND_HANDLER(lpc2000_handle_part_id_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
diff --git a/src/flash/lpc2900.c b/src/flash/lpc2900.c
index 1d5abd9..465d776 100644
--- a/src/flash/lpc2900.c
+++ b/src/flash/lpc2900.c
@@ -544,7 +544,7 @@ COMMAND_HANDLER(lpc2900_handle_signature_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -589,7 +589,7 @@ COMMAND_HANDLER(lpc2900_handle_read_custom_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -660,7 +660,7 @@ COMMAND_HANDLER(lpc2900_handle_password_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -695,7 +695,7 @@ COMMAND_HANDLER(lpc2900_handle_write_custom_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -806,7 +806,7 @@ COMMAND_HANDLER(lpc2900_handle_secure_sector_command)
 
 	/* Get the bank descriptor */
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -905,7 +905,7 @@ COMMAND_HANDLER(lpc2900_handle_secure_jtag_command)
 
 	/* Get the bank descriptor */
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
diff --git a/src/flash/nand.c b/src/flash/nand.c
index d812805..3518056 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -322,7 +322,7 @@ struct nand_device *get_nand_device_by_num(int num)
 	return NULL;
 }
 
-COMMAND_HELPER(nand_command_get_device_by_num, unsigned name_index,
+COMMAND_HELPER(nand_command_get_device, unsigned name_index,
 		struct nand_device **nand)
 {
 	const char *str = CMD_ARGV[name_index];
@@ -1100,7 +1100,7 @@ COMMAND_HANDLER(handle_nand_info_command)
 	int last = -1;
 
 	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -1175,7 +1175,7 @@ COMMAND_HANDLER(handle_nand_probe_command)
 	}
 
 	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -1204,7 +1204,7 @@ COMMAND_HANDLER(handle_nand_erase_command)
 	}
 
 	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -1263,7 +1263,7 @@ COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
 	}
 
 	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -1415,7 +1415,7 @@ static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	struct nand_device *nand;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &nand);
+	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -1674,7 +1674,7 @@ COMMAND_HANDLER(handle_nand_raw_access_command)
 	}
 
 	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device_by_num, 0, &p);
+	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
 	if (ERROR_OK != retval)
 		return retval;
 
diff --git a/src/flash/nand.h b/src/flash/nand.h
index a108771..d38ed67 100644
--- a/src/flash/nand.h
+++ b/src/flash/nand.h
@@ -239,7 +239,7 @@ int nand_register_commands(struct command_context *cmd_ctx);
 int nand_init(struct command_context *cmd_ctx);
 
 /// helper for parsing a nand device command argument string
-COMMAND_HELPER(nand_command_get_device_by_num, unsigned name_index,
+COMMAND_HELPER(nand_command_get_device, unsigned name_index,
 		struct nand_device **nand);
 
 
diff --git a/src/flash/pic32mx.c b/src/flash/pic32mx.c
index 4bfe91b..fa5a4d6 100644
--- a/src/flash/pic32mx.c
+++ b/src/flash/pic32mx.c
@@ -684,7 +684,7 @@ COMMAND_HANDLER(pic32mx_handle_lock_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -730,7 +730,7 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -820,7 +820,7 @@ COMMAND_HANDLER(pic32mx_handle_chip_erase_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -858,7 +858,7 @@ COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 2, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
diff --git a/src/flash/stellaris.c b/src/flash/stellaris.c
index a18c99b..32fa415 100644
--- a/src/flash/stellaris.c
+++ b/src/flash/stellaris.c
@@ -1139,7 +1139,7 @@ COMMAND_HANDLER(stellaris_handle_mass_erase_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
diff --git a/src/flash/stm32x.c b/src/flash/stm32x.c
index 4db338d..c96b49d 100644
--- a/src/flash/stm32x.c
+++ b/src/flash/stm32x.c
@@ -905,7 +905,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -951,7 +951,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -995,7 +995,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -1051,7 +1051,7 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
 	}
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+	int retval = CALL_COMMAND_HANDLE...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-485-g8f446fc

From: David B. <dbr...@us...> - 2009-11-19 22:24:10

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  8f446fcf676e9cd13cf53d9946f0cae5d29a10ec (commit)
       via  cbc13187c315227c0cf8d85fb0b92d0ba4a10dab (commit)
      from  e3ed06579bd8129c11af0a1636a55d62af08980b (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 8f446fcf676e9cd13cf53d9946f0cae5d29a10ec
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 13:23:49 2009 -0800

    ARM: remove per-register malloc
    
    Just pre-allocate memory for the cached register value.
    Shrinks heap overhead; increases locality-of-reference.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index b6061af..44e5b0a 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -489,7 +489,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 
 		reg_list[i].name = (char *) arm_core_regs[i].name;
 		reg_list[i].size = 32;
-		reg_list[i].value = calloc(1, 4);
+		reg_list[i].value = &arch_info[i].value;
 		reg_list[i].type = &arm_reg_type;
 		reg_list[i].arch_info = &arch_info[i];
 
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 6b1dd76..50af57b 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -143,6 +143,7 @@ struct armv4_5_core_reg
 	enum armv4_5_mode mode;
 	struct target *target;
 	struct arm *armv4_5_common;
+	uint32_t value;
 };
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target,

commit cbc13187c315227c0cf8d85fb0b92d0ba4a10dab
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 13:23:08 2009 -0800

    ARM: streamline register init
    
    Combine register names with other per-register data into a
    single template structure.  This saves space, and makes it
    easier to change how registers get handled (by shrinking
    the number of places that care about cache indices).
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 5e882e6..b6061af 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -36,26 +36,6 @@
 #include "register.h"
 
 
-static const char *armv4_5_core_reg_list[] =
-{
-	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-	"r8", "r9", "r10", "r11", "r12", "sp_usr", "lr_usr", "pc",
-
-	"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq",
-
-	"sp_irq", "lr_irq",
-
-	"sp_svc", "lr_svc",
-
-	"sp_abt", "lr_abt",
-
-	"sp_und", "lr_und",
-
-	"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
-
-	"sp_mon", "lr_mon", "spsr_mon",
-};
-
 static const uint8_t arm_usr_indices[17] = {
 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
 };
@@ -230,58 +210,90 @@ char* armv4_5_state_strings[] =
 	"ARM", "Thumb", "Jazelle", "ThumbEE",
 };
 
-static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
-{
-	{0, ARMV4_5_MODE_ANY, NULL, NULL},
-	{1, ARMV4_5_MODE_ANY, NULL, NULL},
-	{2, ARMV4_5_MODE_ANY, NULL, NULL},
-	{3, ARMV4_5_MODE_ANY, NULL, NULL},
-	{4, ARMV4_5_MODE_ANY, NULL, NULL},
-	{5, ARMV4_5_MODE_ANY, NULL, NULL},
-	{6, ARMV4_5_MODE_ANY, NULL, NULL},
-	{7, ARMV4_5_MODE_ANY, NULL, NULL},
-	{8, ARMV4_5_MODE_ANY, NULL, NULL},
-	{9, ARMV4_5_MODE_ANY, NULL, NULL},
-	{10, ARMV4_5_MODE_ANY, NULL, NULL},
-	{11, ARMV4_5_MODE_ANY, NULL, NULL},
-	{12, ARMV4_5_MODE_ANY, NULL, NULL},
-	{13, ARMV4_5_MODE_USR, NULL, NULL},
-	{14, ARMV4_5_MODE_USR, NULL, NULL},
-	{15, ARMV4_5_MODE_ANY, NULL, NULL},
-
-	{8, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{9, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{10, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{11, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{12, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{13, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{14, ARMV4_5_MODE_FIQ, NULL, NULL},
-
-	{13, ARMV4_5_MODE_IRQ, NULL, NULL},
-	{14, ARMV4_5_MODE_IRQ, NULL, NULL},
-
-	{13, ARMV4_5_MODE_SVC, NULL, NULL},
-	{14, ARMV4_5_MODE_SVC, NULL, NULL},
-
-	{13, ARMV4_5_MODE_ABT, NULL, NULL},
-	{14, ARMV4_5_MODE_ABT, NULL, NULL},
-
-	{13, ARMV4_5_MODE_UND, NULL, NULL},
-	{14, ARMV4_5_MODE_UND, NULL, NULL},
-
-	{16, ARMV4_5_MODE_ANY, NULL, NULL},
-	{16, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{16, ARMV4_5_MODE_IRQ, NULL, NULL},
-	{16, ARMV4_5_MODE_SVC, NULL, NULL},
-	{16, ARMV4_5_MODE_ABT, NULL, NULL},
-	{16, ARMV4_5_MODE_UND, NULL, NULL},
-
-	{13, ARM_MODE_MON, NULL, NULL},
-	{14, ARM_MODE_MON, NULL, NULL},
-	{16, ARM_MODE_MON, NULL, NULL},
+/* Templates for ARM core registers.
+ *
+ * NOTE:  offsets in this table are coupled to the arm_mode_data
+ * table above, the armv4_5_core_reg_map array below, and also to
+ * the ARMV4_5_*PSR* symols.
+ */
+static const struct {
+	/* The name is used for e.g. the "regs" command. */
+	const char *name;
+
+	/* The {cookie, mode} tuple uniquely identifies one register.
+	 * In a given mode, cookies 0..15 map to registers R0..R15,
+	 * with R13..R15 usually called SP, LR, PC.
+	 *
+	 * MODE_ANY is used as *input* to the mapping, and indicates
+	 * various special cases (sigh) and errors.
+	 *
+	 * Cookie 16 is (currently) confusing, since it indicates
+	 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
+	 * (Exception modes have both CPSR and SPSR registers ...)
+	 */
+	unsigned cookie;
+	enum armv4_5_mode mode;
+} arm_core_regs[] = {
+	{ .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
+
+	/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
+	 * them as MODE_ANY creates special cases.
+	 */
+	{ .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
+
+	/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
+	{ .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
+	{ .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
+
+	{ .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
+
+	{ .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
+	{ .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
+	{ .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
+	{ .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
+	{ .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
+
+	{ .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
+	{ .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
+
+	{ .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
+	{ .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
+
+	{ .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
+	{ .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
+
+	{ .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
+	{ .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
+
+	{ .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
+	{ .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
+
+	{ .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
+	{ .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
+	{ .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
+	{ .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
+	{ .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
+	{ .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
+
+	{ .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, },
+	{ .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, },
+	{ .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
 };
 
-/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
+/* map core mode (USR, FIQ, ...) and register number to
+ * indices into the register cache
+ */
 const int armv4_5_core_reg_map[8][17] =
 {
 	{	/* USR */
@@ -442,7 +454,7 @@ int armv4_5_invalidate_core_regs(struct target *target)
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
 {
-	int num_regs = ARRAY_SIZE(armv4_5_core_reg_list_arch_info);
+	int num_regs = ARRAY_SIZE(arm_core_regs);
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 	struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 	struct armv4_5_core_reg *arch_info = calloc(num_regs,
@@ -464,16 +476,18 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 	for (i = 0; i < num_regs; i++)
 	{
 		/* Skip registers this core doesn't expose */
-		if (armv4_5_core_reg_list_arch_info[i].mode == ARM_MODE_MON
+		if (arm_core_regs[i].mode == ARM_MODE_MON
 				&& armv4_5_common->core_type != ARM_MODE_MON)
 			continue;
 
 		/* REVISIT handle Cortex-M, which only shadows R13/SP */
 
-		arch_info[i] = armv4_5_core_reg_list_arch_info[i];
+		arch_info[i].num = arm_core_regs[i].cookie;
+		arch_info[i].mode = arm_core_regs[i].mode;
 		arch_info[i].target = target;
 		arch_info[i].armv4_5_common = armv4_5_common;
-		reg_list[i].name = (char *) armv4_5_core_reg_list[i];
+
+		reg_list[i].name = (char *) arm_core_regs[i].name;
 		reg_list[i].size = 32;
 		reg_list[i].value = calloc(1, 4);
 		reg_list[i].type = &arm_reg_type;

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv4_5.c |  164 +++++++++++++++++++++++++++-----------------------
 src/target/armv4_5.h |    1 +
 2 files changed, 90 insertions(+), 75 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-483-ge3ed065

From: David B. <dbr...@us...> - 2009-11-19 19:47:50

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  e3ed06579bd8129c11af0a1636a55d62af08980b (commit)
      from  c049033fde1592e1bfa922641034c1ab136e0b47 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit e3ed06579bd8129c11af0a1636a55d62af08980b
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 10:47:31 2009 -0800

    Cortex-A8: parts of examine() run just once
    
    The examine() method has some conceptual breakage.  Cope
    with it by manually splitting out the run-once parts from
    the after-each-reset parts ... this gets rid of memory
    leaks and speeds up resets after the first one.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index d62740c..c0a7466 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1362,7 +1362,7 @@ static int cortex_a8_handle_target_request(void *priv)
  * Cortex-A8 target information and configuration
  */
 
-static int cortex_a8_examine(struct target *target)
+static int cortex_a8_examine_first(struct target *target)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1447,10 +1447,21 @@ static int cortex_a8_examine(struct target *target)
 	LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
 			cortex_a8->brp_num , cortex_a8->wrp_num);
 
-	/* Configure core debug access */
-	cortex_a8_init_debug_access(target);
-
 	target_set_examined(target);
+	return ERROR_OK;
+}
+
+static int cortex_a8_examine(struct target *target)
+{
+	int retval = ERROR_OK;
+
+	/* don't re-probe hardware after each reset */
+	if (!target_was_examined(target))
+		retval = cortex_a8_examine_first(target);
+
+	/* Configure core debug access */
+	if (retval == ERROR_OK)
+		retval = cortex_a8_init_debug_access(target);
 
 	return retval;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_a8.c |   19 +++++++++++++++----
 1 files changed, 15 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-482-gc049033

From: Zach W. <zw...@us...> - 2009-11-19 16:01:48

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  c049033fde1592e1bfa922641034c1ab136e0b47 (commit)
      from  195ce5eb273983dbeabeea41cc18b77e4f30ab41 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit c049033fde1592e1bfa922641034c1ab136e0b47
Author: Dean Glazeski <dn...@gm...>
Date:   Wed Nov 18 23:22:25 2009 -0600

    nand_fileio_parse_args parses wrong param for size
    
    This changes the size parameter from argv[2] to argv[3], which is what it's
    supposed to be.
    
    Signed-off-by: Zachary T Welch <zw...@su...>

diff --git a/src/flash/nand.c b/src/flash/nand.c
index 23caed0..53b6531 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -1406,7 +1406,7 @@ static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->address);
 	if (need_size)
 	{
-			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->size);
+			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], state->size);
 			if (state->size % nand->page_size)
 			{
 				command_print(CMD_CTX, "only page-aligned sizes are supported");

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-481-g195ce5e

From: David B. <dbr...@us...> - 2009-11-19 11:33:18

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  195ce5eb273983dbeabeea41cc18b77e4f30ab41 (commit)
       via  f320b1228932e33292207d89778125c03379de5d (commit)
      from  f382ebae1050fe26f25d13fd558277d8a032c778 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 195ce5eb273983dbeabeea41cc18b77e4f30ab41
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 02:33:01 2009 -0800

    ARMv7-A: use standard ARM core states
    
    We don't want an ARMv7-specific core state enumeration just to
    add ThumbEE state.  Update the generic stuff to handle that,
    and replace the V7-specific bits with it.
    
    For Cortex-A8:  on debug entry, check both the T and J bits
    instead of just the T bit.  When the J bit is set, set the
    right state and warn appropriately.
    
    (And while we're at it, move the generic arm struct to the front
    of the v7a structure, for somewhat better code generation.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6c6f2bf..5e882e6 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -227,7 +227,7 @@ enum armv4_5_mode armv4_5_number_to_mode(int number)
 
 char* armv4_5_state_strings[] =
 {
-	"ARM", "Thumb", "Jazelle"
+	"ARM", "Thumb", "Jazelle", "ThumbEE",
 };
 
 static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index e3d053c..6b1dd76 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -52,6 +52,7 @@ typedef enum armv4_5_state
 	ARMV4_5_STATE_ARM,
 	ARMV4_5_STATE_THUMB,
 	ARMV4_5_STATE_JAZELLE,
+	ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 98e3fa3..ea883c1 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -34,11 +34,6 @@
 #include <unistd.h>
 
 
-static const char *armv7a_state_strings[] =
-{
-	"ARM", "Thumb", "Jazelle", "ThumbEE"
-};
-
 static void armv7a_show_fault_registers(struct target *target)
 {
 	uint32_t dfsr, ifsr, dfar, ifar;
@@ -75,7 +70,7 @@ int armv7a_arch_state(struct target *target)
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			 "MMU: %s, D-Cache: %s, I-Cache: %s",
-		 armv7a_state_strings[armv7a->core_state],
+		 armv4_5_state_strings[armv4_5->core_state],
 		 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 				target->debug_reason)->name,
 		 arm_mode_name(armv4_5->core_mode),
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index f31a7af..635cd40 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -24,15 +24,6 @@
 #include "armv4_5_mmu.h"
 #include "armv4_5_cache.h"
 
-
-typedef enum armv7a_state
-{
-	ARMV7A_STATE_ARM,
-	ARMV7A_STATE_THUMB,
-	ARMV7A_STATE_JAZELLE,
-	ARMV7A_STATE_THUMBEE,
-} armv7a_state_t;
-
 enum
 {
 	ARM_PC  = 15,
@@ -64,9 +55,9 @@ enum
 
 struct armv7a_common
 {
+	struct arm armv4_5_common;
 	int common_magic;
 	struct reg_cache *core_cache;
-	enum armv7a_state core_state;
 
 	/* arm adp debug port */
 	struct swjdp_common swjdp_info;
@@ -78,7 +69,6 @@ struct armv7a_common
 
 	/* Cache and Memory Management Unit */
 	struct armv4_5_mmu_common armv4_5_mmu;
-	struct arm armv4_5_common;
 
 	int (*read_cp15)(struct target *target,
 			uint32_t op1, uint32_t op2,
@@ -107,7 +97,7 @@ struct armv7a_algorithm
 	int common_magic;
 
 	enum armv4_5_mode core_mode;
-	enum armv7a_state core_state;
+	enum armv4_5_state core_state;
 };
 
 struct armv7a_core_reg
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index fc78844..d62740c 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -491,16 +491,21 @@ static int cortex_a8_resume(struct target *target, int current,
 	/* Make sure that the Armv7 gdb thumb fixups does not
 	 * kill the return address
 	 */
-	if (armv7a->core_state == ARMV7A_STATE_ARM)
+	switch (armv4_5->core_state)
 	{
+	case ARMV4_5_STATE_ARM:
 		resume_pc &= 0xFFFFFFFC;
-	}
-	/* When the return address is loaded into PC
-	 * bit 0 must be 1 to stay in Thumb state
-	 */
-	if (armv7a->core_state == ARMV7A_STATE_THUMB)
-	{
+		break;
+	case ARMV4_5_STATE_THUMB:
+	case ARM_STATE_THUMB_EE:
+		/* When the return address is loaded into PC
+		 * bit 0 must be 1 to stay in Thumb state
+		 */
 		resume_pc |= 0x1;
+		break;
+	case ARMV4_5_STATE_JAZELLE:
+		LOG_ERROR("How do I resume into Jazelle state??");
+		return ERROR_FAIL;
 	}
 	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
 	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
@@ -630,9 +635,29 @@ static int cortex_a8_debug_entry(struct target *target)
 	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
 	armv4_5->core_mode = cpsr & 0x1F;
-	armv7a->core_state = (cpsr & 0x20)
-			? ARMV7A_STATE_THUMB
-			: ARMV7A_STATE_ARM;
+
+	i = (cpsr >> 5) & 1;	/* T */
+	i |= (cpsr >> 23) & 1;	/* J << 1 */
+	switch (i) {
+	case 0:	/* J = 0, T = 0 */
+		armv4_5->core_state = ARMV4_5_STATE_ARM;
+		break;
+	case 1:	/* J = 0, T = 1 */
+		armv4_5->core_state = ARMV4_5_STATE_THUMB;
+		break;
+	case 2:	/* J = 1, T = 0 */
+		LOG_WARNING("Jazelle state -- not handled");
+		armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+		break;
+	case 3:	/* J = 1, T = 1 */
+		/* ThumbEE is very much like Thumb, but some of the
+		 * instructions are different.  Single stepping and
+		 * breakpoints need updating...
+		 */
+		LOG_WARNING("ThumbEE -- incomplete support");
+		armv4_5->core_state = ARM_STATE_THUMB_EE;
+		break;
+	}
 
 	/* update cache */
 	reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
@@ -651,7 +676,7 @@ static int cortex_a8_debug_entry(struct target *target)
 	}
 
 	/* Fixup PC Resume Address */
-	if (armv7a->core_state == ARMV7A_STATE_THUMB)
+	if (cpsr & (1 << 5))
 	{
 		// T bit set for Thumb or ThumbEE state
 		regfile[ARM_PC] -= 4;
@@ -775,7 +800,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
 	/* Setup single step breakpoint */
 	stepbreakpoint.address = address;
-	stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
+	stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+			? 2 : 4;
 	stepbreakpoint.type = BKPT_HARD;
 	stepbreakpoint.set = 0;
 

commit f320b1228932e33292207d89778125c03379de5d
Author: David Brownell <dbr...@us...>
Date:   Thu Nov 19 02:31:34 2009 -0800

    ARMv7-A: use standard ARM core_mode symbols
    
    The only way ARMv7-A modes differ from ARMv4/ARMv5 flavors
    is that v7-A is allowed to include "Secure monitor" support.
    That's now handled by our standard top-level ARM code ... so
    phase out the stuff that's specific to ARMv7-A.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 6aa9d2f..98e3fa3 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -86,7 +86,7 @@ int armv7a_arch_state(struct target *target)
 		 state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 		 state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 
-	if (armv4_5->core_mode == ARMV7A_MODE_ABT)
+	if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
 		armv7a_show_fault_registers(target);
 
 	return ERROR_OK;
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index b008361..f31a7af 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -24,18 +24,6 @@
 #include "armv4_5_mmu.h"
 #include "armv4_5_cache.h"
 
-typedef enum armv7a_mode
-{
-	ARMV7A_MODE_USR = 16,
-	ARMV7A_MODE_FIQ = 17,
-	ARMV7A_MODE_IRQ = 18,
-	ARMV7A_MODE_SVC = 19,
-	ARMV7A_MODE_ABT = 23,
-	ARMV7A_MODE_UND = 27,
-	ARMV7A_MODE_SYS = 31,
-	ARMV7A_MODE_MON = 22,
-	ARMV7A_MODE_ANY = -1
-} armv7a_t;
 
 typedef enum armv7a_state
 {
@@ -78,7 +66,6 @@ struct armv7a_common
 {
 	int common_magic;
 	struct reg_cache *core_cache;
-	enum armv7a_mode core_mode;
 	enum armv7a_state core_state;
 
 	/* arm adp debug port */
@@ -119,14 +106,14 @@ struct armv7a_algorithm
 {
 	int common_magic;
 
-	enum armv7a_mode core_mode;
+	enum armv4_5_mode core_mode;
 	enum armv7a_state core_state;
 };
 
 struct armv7a_core_reg
 {
 	int num;
-	enum armv7a_mode mode;
+	enum armv4_5_mode mode;
 	struct target *target;
 	struct armv7a_common *armv7a_common;
 };

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv4_5.c   |    2 +-
 src/target/armv4_5.h   |    1 +
 src/target/armv7a.c    |    9 +------
 src/target/armv7a.h    |   31 +++-------------------------
 src/target/cortex_a8.c |   50 ++++++++++++++++++++++++++++++++++++-----------
 5 files changed, 46 insertions(+), 47 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-479-gf382eba

From: Zach W. <zw...@us...> - 2009-11-19 00:52:11

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  f382ebae1050fe26f25d13fd558277d8a032c778 (commit)
       via  c0d14dc7f19d785702eee5f69de5b1a63902554b (commit)
       via  20218b8de61dea545c7575f36e1b74b9599c9848 (commit)
       via  4d8d1d32d0f0e0b8866a06cb1d3f304563fa6796 (commit)
       via  7e4adfe1c53aa18d4feba1e58ceb5c5aaa470775 (commit)
       via  410fab9ea8c6632da2e4967d960f66eecc7821ec (commit)
       via  75a37eb5b37386768327e9670acfedc7811d529f (commit)
       via  bd5a1799ea63c2a863eae4aca2b55e41373d7528 (commit)
      from  bd9d05e14bd08352811561e2d59a7ef2d9f3ed25 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit f382ebae1050fe26f25d13fd558277d8a032c778
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 06:00:26 2009 -0800

    fix zy1000 command handler
    
    Rewrite ZY1000 power command handler to use new macros, simplify logic.
    
    Remove unused port command handler declaration.

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 206b362..28515c7 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -46,9 +46,6 @@ int zy1000_register_commands(struct command_context *cmd_ctx);
 int zy1000_init(void);
 int zy1000_quit(void);
 
-/* interface commands */
-int zy1000_handle_zy1000_port_command(struct command_context *cmd_ctx, char *cmd, char **args, int argc);
-
 static int zy1000_khz(int khz, int *jtag_speed)
 {
 	if (khz == 0)
@@ -227,21 +224,22 @@ static void setPower(bool power)
 	}
 }
 
-int handle_power_command(struct command_context *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_power_command)
 {
-	if (argc > 1)
-	{
-		return ERROR_INVALID_ARGUMENTS;
-	}
-
-	if (argc == 1)
+	switch (CMD_ARGC)
 	{
+	case 1: {
 		bool enable;
-		COMMAND_PARSE_ON_OFF(args[0], enable);
+		COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
 		setPower(enable);
+		// fall through
+	}
+	case 0:
+		command_print(cmd_ctx, "Target power %s", savePower ? "on" : "off");
+		break;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
 	}
-
-	command_print(cmd_ctx, "Target power %s", savePower ? "on" : "off");
 
 	return ERROR_OK;
 }

commit c0d14dc7f19d785702eee5f69de5b1a63902554b
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 05:02:08 2009 -0800

    remove fast command and jim_global_long
    
    Removing the fast command eliminates the fast_and_dangerous global,
    which was used only by arm7_9_common as an initializer.  The command
    is not called in the tree; instead, more explicit commands are used.
    
    The jim_global_long function was not used anywhere in the tree.

diff --git a/src/helper/command.c b/src/helper/command.c
index b7c44ef..ba689b0 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -44,7 +44,6 @@
 #include "jim-eventloop.h"
 
 
-int fast_and_dangerous = 0;
 Jim_Interp *interp = NULL;
 
 static int run_command(struct command_context *context,
@@ -141,7 +140,6 @@ static int script_command(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 
 	log_add_callback(tcl_output, tclOutput);
 
-	// turn words[0] into CMD_ARGV[-1] with this cast
 	retval = run_command(context, c, (const char **)words, nwords);
 
 	log_remove_callback(tcl_output, tclOutput);
@@ -755,17 +753,6 @@ COMMAND_HANDLER(handle_sleep_command)
 	return ERROR_OK;
 }
 
-COMMAND_HANDLER(handle_fast_command)
-{
-	if (CMD_ARGC != 1)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	fast_and_dangerous = strcmp("enable", CMD_ARGV[0]) == 0;
-
-	return ERROR_OK;
-}
-
-
 struct command_context* command_init(const char *startup_tcl)
 {
 	struct command_context* context = malloc(sizeof(struct command_context));
@@ -839,10 +826,6 @@ struct command_context* command_init(const char *startup_tcl)
 			handle_sleep_command, COMMAND_ANY,
 			"<n> [busy] - sleep for n milliseconds. "
 			"\"busy\" means busy wait");
-	register_command(context, NULL, "fast",
-			handle_fast_command, COMMAND_ANY,
-			"fast <enable/disable> - place at beginning of "
-			"config files. Sets defaults to fast and dangerous.");
 
 	return context;
 }
@@ -882,18 +865,6 @@ void register_jim(struct command_context *cmd_ctx, const char *name,
 	command_helptext_add(cmd_list, help);
 }
 
-/* return global variable long value or 0 upon failure */
-long jim_global_long(const char *variable)
-{
-	Jim_Obj *objPtr = Jim_GetGlobalVariableStr(interp, variable, JIM_ERRMSG);
-	long t;
-	if (Jim_GetLong(interp, objPtr, &t) == JIM_OK)
-	{
-		return t;
-	}
-	return 0;
-}
-
 #define DEFINE_PARSE_NUM_TYPE(name, type, func, min, max) \
 	int parse##name(const char *str, type *ul) \
 	{ \
diff --git a/src/helper/command.h b/src/helper/command.h
index a2e9797..def0935 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -214,15 +214,11 @@ void process_jim_events(void);
 #define		ERROR_COMMAND_ARGUMENT_OVERFLOW		(-604)
 #define		ERROR_COMMAND_ARGUMENT_UNDERFLOW	(-605)
 
-extern int fast_and_dangerous;
-
 extern Jim_Interp *interp;
 
 void register_jim(struct command_context *context, const char *name,
 		Jim_CmdProc cmd, const char *help);
 
-long jim_global_long(const char *variable);
-
 int parse_ulong(const char *str, unsigned long *ul);
 int parse_ullong(const char *str, unsigned long long *ul);
 
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 16c8a92..eb4b038 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2929,8 +2929,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 
 	arm7_9->wp_available_max = 2;
 
-	arm7_9->fast_memory_access = fast_and_dangerous;
-	arm7_9->dcc_downloads = fast_and_dangerous;
+	arm7_9->fast_memory_access = false;
+	arm7_9->dcc_downloads = false;
 
 	armv4_5->arch_info = arm7_9;
 	armv4_5->read_core_reg = arm7_9_read_core_reg;

commit 20218b8de61dea545c7575f36e1b74b9599c9848
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 15:20:58 2009 -0800

    update src/hello.c with parsing examples
    
    Adds the foo/bar commands to provide more working examples of command
    argument parsing, including the new handle_command_parse_bool helper.
    
    Updates hello command help text to provide useful information.

diff --git a/src/hello.c b/src/hello.c
index dd33650..2ab7eb5 100644
--- a/src/hello.c
+++ b/src/hello.c
@@ -22,6 +22,57 @@
 #endif
 #include "log.h"
 
+COMMAND_HANDLER(handle_foo_command)
+{
+	if (CMD_ARGC < 1 || CMD_ARGC > 2)
+	{
+		LOG_ERROR("%s: incorrect number of arguments", CMD_NAME);
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	uint32_t address;
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+
+	const char *msg = "<unchanged>";
+	if (CMD_ARGC == 2)
+	{
+		bool enable;
+		COMMAND_PARSE_ENABLE(CMD_ARGV[1], enable);
+		msg = enable ? "enable" : "disable";
+	}
+
+	LOG_INFO("%s: address=0x%8.8" PRIx32 " enabled=%s", CMD_NAME, address, msg);
+	return ERROR_OK;
+}
+
+static bool foo_flag;
+
+COMMAND_HANDLER(handle_flag_command)
+{
+	return CALL_COMMAND_HANDLER(handle_command_parse_bool,
+			&foo_flag, "foo flag");
+}
+
+int foo_register_commands(struct command_context *cmd_ctx)
+{
+	// register several commands under the foo command
+	struct command *cmd = register_command(cmd_ctx, NULL, "foo",
+			NULL, COMMAND_ANY, "foo: command handler skeleton");
+
+	register_command(cmd_ctx, cmd, "bar",
+			&handle_foo_command, COMMAND_ANY,
+			"<address> [enable|disable] - an example command");
+	register_command(cmd_ctx, cmd, "baz",
+			&handle_foo_command, COMMAND_ANY,
+			"<address> [enable|disable] - a sample command");
+
+	register_command(cmd_ctx, cmd, "flag",
+			&handle_flag_command, COMMAND_ANY,
+			"[on|off] - set a flag");
+
+	return ERROR_OK;
+}
+
 static COMMAND_HELPER(handle_hello_args, const char **sep, const char **name)
 {
 	if (CMD_ARGC > 1)
@@ -50,8 +101,10 @@ COMMAND_HANDLER(handle_hello_command)
 
 int hello_register_commands(struct command_context *cmd_ctx)
 {
+	foo_register_commands(cmd_ctx);
+
 	struct command *cmd = register_command(cmd_ctx, NULL, "hello",
 			&handle_hello_command, COMMAND_ANY,
-			"option");
+			"[<name>] - prints a warm welcome");
 	return cmd ? ERROR_OK : -ENOMEM;
 }

commit 4d8d1d32d0f0e0b8866a06cb1d3f304563fa6796
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 12:41:20 2009 -0800

    change all bool parsers to accept any value
    
    This patch changes the behavior of all boolean parsing callers to
    accept any one of "true/enable/on/yes/1" or "false/disable/off/no/0".
    
    Since one particular pair will be most appropriate in any given
    situation, the specific macros should continue to be used in
    order to display the most informative error messages possible.

diff --git a/src/helper/command.c b/src/helper/command.c
index 5f3fae5..b7c44ef 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -955,7 +955,7 @@ DEFINE_PARSE_LONG(_s32, int32_t, n < INT32_MIN, INT32_MAX)
 DEFINE_PARSE_LONG(_s16, int16_t, n < INT16_MIN, INT16_MAX)
 DEFINE_PARSE_LONG(_s8, int8_t, n < INT8_MIN, INT8_MAX)
 
-int command_parse_bool(const char *in, bool *out,
+static int command_parse_bool(const char *in, bool *out,
 		const char *on, const char *off)
 {
 	if (strcasecmp(in, on) == 0)
@@ -967,7 +967,7 @@ int command_parse_bool(const char *in, bool *out,
 	return  ERROR_OK;
 }
 
-int command_parse_bool_any(const char *in, bool *out)
+int command_parse_bool_arg(const char *in, bool *out)
 {
 	if (command_parse_bool(in, out, "on", "off") == ERROR_OK)
 		return ERROR_OK;
@@ -987,7 +987,7 @@ COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label)
 	switch (CMD_ARGC) {
 	case 1: {
 		const char *in = CMD_ARGV[0];
-		if (command_parse_bool_any(in, out) != ERROR_OK)
+		if (command_parse_bool_arg(in, out) != ERROR_OK)
 		{
 			LOG_ERROR("%s: argument '%s' is not valid", CMD_NAME, in);
 			return ERROR_INVALID_ARGUMENTS;
diff --git a/src/helper/command.h b/src/helper/command.h
index 06403ef..a2e9797 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -272,7 +272,7 @@ DECLARE_PARSE_WRAPPER(_s8, int8_t);
 #define COMMAND_PARSE_BOOL(in, out, on, off) \
 	do { \
 		bool value; \
-		int retval = command_parse_bool(in, &value, on, off); \
+		int retval = command_parse_bool_arg(in, &value); \
 		if (ERROR_OK != retval) { \
 			command_print(CMD_CTX, stringify(out) \
 				" option value ('%s') is not valid", in); \
@@ -283,8 +283,7 @@ DECLARE_PARSE_WRAPPER(_s8, int8_t);
 		out = value; \
 	} while (0)
 
-int command_parse_bool(const char *in, bool *out,
-		const char *on, const char *off);
+int command_parse_bool_arg(const char *in, bool *out);
 COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label);
 
 /// parses an on/off command argument

commit 7e4adfe1c53aa18d4feba1e58ceb5c5aaa470775
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 06:58:27 2009 -0800

    add handle_command_parse_bool command helper
    
    Rewrite arm11_handle_bool to provide a generic on/off command helper.
    
    Refactors COMMAND_PARSE_BOOL to use new command_parse_bool helper,
    which gets reused by the new command_parse_bool_any helper.
    This later helper is called by the new command helper function to
    accepts any on/off, enable/disable, true/false, yes/no, or 0/1 parameter.

diff --git a/src/helper/command.c b/src/helper/command.c
index 708a802..5f3fae5 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -954,3 +954,53 @@ DEFINE_PARSE_LONG(_int, int, n < INT_MIN, INT_MAX)
 DEFINE_PARSE_LONG(_s32, int32_t, n < INT32_MIN, INT32_MAX)
 DEFINE_PARSE_LONG(_s16, int16_t, n < INT16_MIN, INT16_MAX)
 DEFINE_PARSE_LONG(_s8, int8_t, n < INT8_MIN, INT8_MAX)
+
+int command_parse_bool(const char *in, bool *out,
+		const char *on, const char *off)
+{
+	if (strcasecmp(in, on) == 0)
+		*out = true;
+	else if (strcasecmp(in, off) == 0)
+		*out = false;
+	else
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	return  ERROR_OK;
+}
+
+int command_parse_bool_any(const char *in, bool *out)
+{
+	if (command_parse_bool(in, out, "on", "off") == ERROR_OK)
+		return ERROR_OK;
+	if (command_parse_bool(in, out, "enable", "disable") == ERROR_OK)
+		return ERROR_OK;
+	if (command_parse_bool(in, out, "true", "false") == ERROR_OK)
+		return ERROR_OK;
+	if (command_parse_bool(in, out, "yes", "no") == ERROR_OK)
+		return ERROR_OK;
+	if (command_parse_bool(in, out, "1", "0") == ERROR_OK)
+		return ERROR_OK;
+	return ERROR_INVALID_ARGUMENTS;
+}
+
+COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label)
+{
+	switch (CMD_ARGC) {
+	case 1: {
+		const char *in = CMD_ARGV[0];
+		if (command_parse_bool_any(in, out) != ERROR_OK)
+		{
+			LOG_ERROR("%s: argument '%s' is not valid", CMD_NAME, in);
+			return ERROR_INVALID_ARGUMENTS;
+		}
+		// fall through
+	}
+	case 0:
+		LOG_INFO("%s is %s", label, *out ? "enabled" : "disabled");
+		break;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+	return ERROR_OK;
+}
+
+
diff --git a/src/helper/command.h b/src/helper/command.h
index 9f2d971..06403ef 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -271,19 +271,22 @@ DECLARE_PARSE_WRAPPER(_s8, int8_t);
  */
 #define COMMAND_PARSE_BOOL(in, out, on, off) \
 	do { \
-		if (strcmp(in, on) == 0) \
-			out = true; \
-		else if (strcmp(in, off) == 0) \
-			out = false; \
-		else { \
+		bool value; \
+		int retval = command_parse_bool(in, &value, on, off); \
+		if (ERROR_OK != retval) { \
 			command_print(CMD_CTX, stringify(out) \
 				" option value ('%s') is not valid", in); \
 			command_print(CMD_CTX, "  choices are '%s' or '%s'", \
 				on, off); \
-			return ERROR_COMMAND_SYNTAX_ERROR; \
+			return retval; \
 		} \
+		out = value; \
 	} while (0)
 
+int command_parse_bool(const char *in, bool *out,
+		const char *on, const char *off);
+COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label);
+
 /// parses an on/off command argument
 #define COMMAND_PARSE_ON_OFF(in, out) \
 		COMMAND_PARSE_BOOL(in, out, "on", "off")
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 6e007cf..58b5d54 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1981,52 +1981,17 @@ static int arm11_build_reg_cache(struct target *target)
 	return ERROR_OK;
 }
 
-static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
-{
-	if (CMD_ARGC == 0)
-	{
-		LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
-		return ERROR_OK;
-	}
-
-	if (CMD_ARGC != 1)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	switch (CMD_ARGV[0][0])
-	{
-	case '0':	/* 0 */
-	case 'f':	/* false */
-	case 'F':
-	case 'd':	/* disable */
-	case 'D':
-		*var = false;
-		break;
-
-	case '1':	/* 1 */
-	case 't':	/* true */
-	case 'T':
-	case 'e':	/* enable */
-	case 'E':
-		*var = true;
-		break;
-	}
-
-	LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
-
-	return ERROR_OK;
-}
-
-#define BOOL_WRAPPER(name, print_name)	\
-COMMAND_HANDLER(arm11_handle_bool_##name) \
-{ \
-	return CALL_COMMAND_HANDLER(arm11_handle_bool, \
-			&arm11_config_##name, print_name); \
-}
+#define ARM11_BOOL_WRAPPER(name, print_name)	\
+		COMMAND_HANDLER(arm11_handle_bool_##name) \
+		{ \
+			return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
+					&arm11_config_##name, print_name); \
+		}
 
-BOOL_WRAPPER(memwrite_burst,			"memory write burst mode")
-BOOL_WRAPPER(memwrite_error_fatal,		"fatal error mode for memory writes")
-BOOL_WRAPPER(step_irq_enable,			"IRQs while stepping")
-BOOL_WRAPPER(hardware_step,			"hardware single step")
+ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
+ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
+ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
+ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
 
 COMMAND_HANDLER(arm11_handle_vcr)
 {

commit 410fab9ea8c6632da2e4967d960f66eecc7821ec
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 05:36:18 2009 -0800

    use COMMAND_PARSE_ENABLE macro where appropriate
    
    Updates all command parsing of simple "enable" and "disable" arguments.
    A few case in the tree use a tri-state or extended arguments, which
    cannot use this simple macro.
    
    Simlifies the xscale icache/dcache command handler logic.

diff --git a/src/flash/nand.c b/src/flash/nand.c
index c96354a..23caed0 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -1663,14 +1663,7 @@ COMMAND_HANDLER(handle_nand_raw_access_command)
 	}
 
 	if (CMD_ARGC == 2)
-	{
-		if (strcmp("enable", CMD_ARGV[1]) == 0)
-			p->use_raw = 1;
-		else if (strcmp("disable", CMD_ARGV[1]) == 0)
-			p->use_raw = 0;
-		else
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
+		COMMAND_PARSE_ENABLE(CMD_ARGV[1], p->use_raw);
 
 	const char *msg = p->use_raw ? "enabled" : "disabled";
 	command_print(CMD_CTX, "raw access is %s", msg);
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 96018b5..1266cd7 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -1357,12 +1357,9 @@ COMMAND_HANDLER(handle_verify_ircapture_command)
 
 	if (CMD_ARGC == 1)
 	{
-		if (strcmp(CMD_ARGV[0], "enable") == 0)
-			jtag_set_verify_capture_ir(true);
-		else if (strcmp(CMD_ARGV[0], "disable") == 0)
-			jtag_set_verify_capture_ir(false);
-		else
-			return ERROR_COMMAND_SYNTAX_ERROR;
+		bool enable;
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+		jtag_set_verify_capture_ir(enable);
 	}
 
 	const char *status = jtag_will_verify_capture_ir() ? "enabled": "disabled";
@@ -1378,12 +1375,9 @@ COMMAND_HANDLER(handle_verify_jtag_command)
 
 	if (CMD_ARGC == 1)
 	{
-		if (strcmp(CMD_ARGV[0], "enable") == 0)
-			jtag_set_verify(true);
-		else if (strcmp(CMD_ARGV[0], "disable") == 0)
-			jtag_set_verify(false);
-		else
-			return ERROR_COMMAND_SYNTAX_ERROR;
+		bool enable;
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+		jtag_set_verify(enable);
 	}
 
 	const char *status = jtag_will_verify() ? "enabled": "disabled";
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 9605f81..21dc24c 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2271,20 +2271,7 @@ COMMAND_HANDLER(handle_gdb_port_command)
 COMMAND_HANDLER(handle_gdb_memory_map_command)
 {
 	if (CMD_ARGC == 1)
-	{
-		if (strcmp(CMD_ARGV[0], "enable") == 0)
-		{
-			gdb_use_memory_map = 1;
-			return ERROR_OK;
-		}
-		else if (strcmp(CMD_ARGV[0], "disable") == 0)
-		{
-			gdb_use_memory_map = 0;
-			return ERROR_OK;
-		}
-		else
-			LOG_WARNING("invalid gdb_memory_map configuration directive %s", CMD_ARGV[0]);
-	}
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_use_memory_map);
 
 	return ERROR_COMMAND_SYNTAX_ERROR;
 }
@@ -2292,20 +2279,7 @@ COMMAND_HANDLER(handle_gdb_memory_map_command)
 COMMAND_HANDLER(handle_gdb_flash_program_command)
 {
 	if (CMD_ARGC == 1)
-	{
-		if (strcmp(CMD_ARGV[0], "enable") == 0)
-		{
-			gdb_flash_program = 1;
-			return ERROR_OK;
-		}
-		else if (strcmp(CMD_ARGV[0], "disable") == 0)
-		{
-			gdb_flash_program = 0;
-			return ERROR_OK;
-		}
-		else
-			LOG_WARNING("invalid gdb_flash_program configuration directive: %s", CMD_ARGV[0]);
-	}
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_flash_program);
 
 	return ERROR_COMMAND_SYNTAX_ERROR;
 }
@@ -2313,20 +2287,7 @@ COMMAND_HANDLER(handle_gdb_flash_program_command)
 COMMAND_HANDLER(handle_gdb_report_data_abort_command)
 {
 	if (CMD_ARGC == 1)
-	{
-		if (strcmp(CMD_ARGV[0], "enable") == 0)
-		{
-			gdb_report_data_abort = 1;
-			return ERROR_OK;
-		}
-		else if (strcmp(CMD_ARGV[0], "disable") == 0)
-		{
-			gdb_report_data_abort = 0;
-			return ERROR_OK;
-		}
-		else
-			LOG_WARNING("invalid gdb_report_data_abort configuration directive: %s", CMD_ARGV[0]);
-	}
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_report_data_abort);
 
 	return ERROR_COMMAND_SYNTAX_ERROR;
 }
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 37aa066..16c8a92 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2870,20 +2870,7 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 	}
 
 	if (CMD_ARGC > 0)
-	{
-		if (strcmp("enable", CMD_ARGV[0]) == 0)
-		{
-			arm7_9->use_dbgrq = 1;
-		}
-		else if (strcmp("disable", CMD_ARGV[0]) == 0)
-		{
-			arm7_9->use_dbgrq = 0;
-		}
-		else
-		{
-			command_print(CMD_CTX, "usage: arm7_9 dbgrq <enable | disable>");
-		}
-	}
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
 
 	command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
 
@@ -2902,20 +2889,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
 	}
 
 	if (CMD_ARGC > 0)
-	{
-		if (strcmp("enable", CMD_ARGV[0]) == 0)
-		{
-			arm7_9->fast_memory_access = 1;
-		}
-		else if (strcmp("disable", CMD_ARGV[0]) == 0)
-		{
-			arm7_9->fast_memory_access = 0;
-		}
-		else
-		{
-			command_print(CMD_CTX, "usage: arm7_9 fast_memory_access <enable | disable>");
-		}
-	}
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
 
 	command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
 
@@ -2934,20 +2908,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
 	}
 
 	if (CMD_ARGC > 0)
-	{
-		if (strcmp("enable", CMD_ARGV[0]) == 0)
-		{
-			arm7_9->dcc_downloads = 1;
-		}
-		else if (strcmp("disable", CMD_ARGV[0]) == 0)
-		{
-			arm7_9->dcc_downloads = 0;
-		}
-		else
-		{
-			command_print(CMD_CTX, "usage: arm7_9 dcc_downloads <enable | disable>");
-		}
-	}
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
 
 	command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
 
diff --git a/src/target/etm.c b/src/target/etm.c
index 3b5fa61..85cc6eb 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -1214,25 +1214,14 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	if (strcmp(CMD_ARGV[2], "enable") == 0)
+	bool etmv1_cycle_accurate;
+	COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
+	if (etmv1_cycle_accurate)
 		tracemode |= ETMV1_CYCLE_ACCURATE;
-	else if (strcmp(CMD_ARGV[2], "disable") == 0)
-		tracemode |= 0;
-	else
-	{
-		command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[2]);
-		return ERROR_INVALID_ARGUMENTS;
-	}
 
-	if (strcmp(CMD_ARGV[3], "enable") == 0)
+	bool etmv1_branch_output;
+	COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
 		tracemode |= ETMV1_BRANCH_OUTPUT;
-	else if (strcmp(CMD_ARGV[3], "disable") == 0)
-		tracemode |= 0;
-	else
-	{
-		command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[3]);
-		return ERROR_INVALID_ARGUMENTS;
-	}
 
 	/* IGNORED:
 	 *  - CPRT tracing (coprocessor register transfers)
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 09e6825..28f89f1 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3130,16 +3130,13 @@ COMMAND_HANDLER(xscale_handle_mmu_command)
 
 	if (CMD_ARGC >= 1)
 	{
-		if (strcmp("enable", CMD_ARGV[0]) == 0)
-		{
+		bool enable;
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+		if (enable)
 			xscale_enable_mmu_caches(target, 1, 0, 0);
-			xscale->armv4_5_mmu.mmu_enabled = 1;
-		}
-		else if (strcmp("disable", CMD_ARGV[0]) == 0)
-		{
+		else
 			xscale_disable_mmu_caches(target, 1, 0, 0);
-			xscale->armv4_5_mmu.mmu_enabled = 0;
-		}
+		xscale->armv4_5_mmu.mmu_enabled = enable;
 	}
 
 	command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
@@ -3151,10 +3148,8 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
-	int icache = 0, dcache = 0;
-	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	int retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -3164,38 +3159,28 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
 		return ERROR_OK;
 	}
 
-	if (strcmp(CMD_NAME, "icache") == 0)
-		icache = 1;
-	else if (strcmp(CMD_NAME, "dcache") == 0)
-		dcache = 1;
+	bool icache;
+	COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
 
 	if (CMD_ARGC >= 1)
 	{
-		if (strcmp("enable", CMD_ARGV[0]) == 0)
-		{
-			xscale_enable_mmu_caches(target, 0, dcache, icache);
-
-			if (icache)
-				xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
-			else if (dcache)
-				xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
-		}
-		else if (strcmp("disable", CMD_ARGV[0]) == 0)
-		{
-			xscale_disable_mmu_caches(target, 0, dcache, icache);
-
-			if (icache)
-				xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
-			else if (dcache)
-				xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-		}
+		bool enable;
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+		if (enable)
+			xscale_enable_mmu_caches(target, 1, 0, 0);
+		else
+			xscale_disable_mmu_caches(target, 1, 0, 0);
+		if (icache)
+			xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
+		else
+			xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
 	}
 
-	if (icache)
-		command_print(CMD_CTX, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
-
-	if (dcache)
-		command_print(CMD_CTX, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+	bool enabled = icache ?
+					xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
+					xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
+	const char *msg = enabled ? "enabled" : "disabled";
+	command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
 
 	return ERROR_OK;
 }

commit 75a37eb5b37386768327e9670acfedc7811d529f
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 05:22:44 2009 -0800

    use COMMAND_PARSE_ON_OFF where appropriate
    
    Updates all command parsing of "on" and "off" arguments.

diff --git a/src/flash/flash.c b/src/flash/flash.c
index 2c63b82..98e5ee0 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -577,7 +577,6 @@ COMMAND_HANDLER(handle_flash_protect_command)
 	uint32_t bank_nr;
 	uint32_t first;
 	uint32_t last;
-	int set;
 
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bank_nr);
 	struct flash_bank *p = get_flash_bank_by_num(bank_nr);
@@ -590,12 +589,8 @@ COMMAND_HANDLER(handle_flash_protect_command)
 	else
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
 
-	if (strcmp(CMD_ARGV[3], "on") == 0)
-		set = 1;
-	else if (strcmp(CMD_ARGV[3], "off") == 0)
-		set = 0;
-	else
-		return ERROR_COMMAND_SYNTAX_ERROR;
+	bool set;
+	COMMAND_PARSE_ON_OFF(CMD_ARGV[3], set);
 
 	int retval;
 	if ((retval = flash_check_sector_parameters(CMD_CTX,
diff --git a/src/jtag/parport.c b/src/jtag/parport.c
index 97f6458..b80626f 100644
--- a/src/jtag/parport.c
+++ b/src/jtag/parport.c
@@ -103,7 +103,7 @@ static struct cable cables[] =
 /* configuration */
 static char* parport_cable = NULL;
 static uint16_t parport_port;
-static int parport_exit = 0;
+static bool parport_exit = 0;
 static uint32_t parport_toggling_time_ns = 1000;
 static int wait_states;
 
@@ -453,10 +453,7 @@ COMMAND_HANDLER(parport_handle_write_on_exit_command)
 		return ERROR_OK;
 	}
 
-	if (strcmp(CMD_ARGV[0], "on") == 0)
-		parport_exit = 1;
-	else if (strcmp(CMD_ARGV[0], "off") == 0)
-		parport_exit = 0;
+	COMMAND_PARSE_ON_OFF(CMD_ARGV[0], parport_exit);
 
 	return ERROR_OK;
 }
diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index a509aee..206b362 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -236,18 +236,9 @@ int handle_power_command(struct command_context *cmd_ctx, char *cmd, char **args
 
 	if (argc == 1)
 	{
-		if (strcmp(args[0], "on") == 0)
-		{
-			setPower(1);
-		}
-		else if (strcmp(args[0], "off") == 0)
-		{
-			setPower(0);
-		} else
-		{
-			command_print(cmd_ctx, "arg is \"on\" or \"off\"");
-			return ERROR_INVALID_ARGUMENTS;
-		}
+		bool enable;
+		COMMAND_PARSE_ON_OFF(args[0], enable);
+		setPower(enable);
 	}
 
 	command_print(cmd_ctx, "Target power %s", savePower ? "on" : "off");
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 42f8ee0..e7b5110 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1898,18 +1898,11 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
 
 	if (CMD_ARGC > 0)
 	{
-		if (!strcmp(CMD_ARGV[0], "on"))
-		{
-			cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
-		}
-		else if (!strcmp(CMD_ARGV[0], "off"))
-		{
-			cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
-		}
-		else
-		{
-			command_print(CMD_CTX, "usage: cortex_m3 maskisr ['on'|'off']");
-		}
+		bool enable;
+		COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
+		uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
+		uint32_t mask_off = enable ? 0 : C_MASKINTS;
+		cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
 	}
 
 	command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
diff --git a/src/target/target.c b/src/target/target.c
index 98e7a40..f203913 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2003,23 +2003,14 @@ COMMAND_HANDLER(handle_poll_command)
 			return retval;
 		if ((retval = target_arch_state(target)) != ERROR_OK)
 			return retval;
-
 	}
 	else if (CMD_ARGC == 1)
 	{
-		if (strcmp(CMD_ARGV[0], "on") == 0)
-		{
-			jtag_poll_set_enabled(true);
-		}
-		else if (strcmp(CMD_ARGV[0], "off") == 0)
-		{
-			jtag_poll_set_enabled(false);
-		}
-		else
-		{
-			command_print(CMD_CTX, "arg is \"on\" or \"off\"");
-		}
-	} else
+		bool enable;
+		COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
+		jtag_poll_set_enabled(enable);
+	}
+	else
 	{
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}

commit bd5a1799ea63c2a863eae4aca2b55e41373d7528
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 05:19:34 2009 -0800

    add COMMAND_PARSE_BOOL macro and friends
    
    Adds several macros similar to COMMAND_PARSE_NUMBER, but for parsing
    boolean command arguments.  Two flavors are provided to provide
    drop-in compatibility with existing code, allow for the elimination
    of a lot of code bloat while improving the error checking and reporting.
    
    COMMAND_PARSE_ON_OFF parses "on"/"off" command parameters.
    COMMAND_PARSE_ENABLE parses "enable"/"disable" command parameters.
    
    Both print the error and return an error out of the calling function.

diff --git a/src/helper/command.h b/src/helper/command.h
index 05088b5..9f2d971 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -263,6 +263,34 @@ DECLARE_PARSE_WRAPPER(_s8, int8_t);
 		} \
 	} while (0)
 
+/**
+ * Parse the string @c as a binary parameter, storing the boolean value
+ * in @c out.  The strings @c on and @c off are used to match different
+ * strings for true and false options (e.g. "on" and "off" or
+ * "enable" and "disable").
+ */
+#define COMMAND_PARSE_BOOL(in, out, on, off) \
+	do { \
+		if (strcmp(in, on) == 0) \
+			out = true; \
+		else if (strcmp(in, off) == 0) \
+			out = false; \
+		else { \
+			command_print(CMD_CTX, stringify(out) \
+				" option value ('%s') is not valid", in); \
+			command_print(CMD_CTX, "  choices are '%s' or '%s'", \
+				on, off); \
+			return ERROR_COMMAND_SYNTAX_ERROR; \
+		} \
+	} while (0)
+
+/// parses an on/off command argument
+#define COMMAND_PARSE_ON_OFF(in, out) \
+		COMMAND_PARSE_BOOL(in, out, "on", "off")
+/// parses an enable/disable command argument
+#define COMMAND_PARSE_ENABLE(in, out) \
+		COMMAND_PARSE_BOOL(in, out, "enable", "disable")
+
 void script_debug(Jim_Interp *interp, const char *cmd,
 		unsigned argc, Jim_Obj *const *argv);
 

-----------------------------------------------------------------------

Summary of changes:
 src/flash/flash.c          |    9 +----
 src/flash/nand.c           |    9 +----
 src/hello.c                |   55 ++++++++++++++++++++++++++++++-
 src/helper/command.c       |   79 ++++++++++++++++++++++++++++----------------
 src/helper/command.h       |   34 ++++++++++++++++--
 src/jtag/parport.c         |    7 +---
 src/jtag/tcl.c             |   18 +++-------
 src/jtag/zy1000/zy1000.c   |   35 +++++++-------------
 src/server/gdb_server.c    |   45 ++-----------------------
 src/target/arm11.c         |   55 +++++-------------------------
 src/target/arm7_9_common.c |   49 +++------------------------
 src/target/cortex_m3.c     |   17 +++-------
 src/target/etm.c           |   21 +++---------
 src/target/target.c        |   19 +++--------
 src/target/xscale.c        |   61 +++++++++++++---------------------
 15 files changed, 213 insertions(+), 300 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-471-gbd9d05e

From: David B. <dbr...@us...> - 2009-11-19 00:31:48

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  bd9d05e14bd08352811561e2d59a7ef2d9f3ed25 (commit)
      from  f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit bd9d05e14bd08352811561e2d59a7ef2d9f3ed25
Author: David Brownell <dbr...@us...>
Date:   Wed Nov 18 15:31:24 2009 -0800

    ARM: rework "arm reg" output for new mode
    
    Change the layout to show the "Secure Monitor" registers too,
    when they're present.
    
    Instead of lining registers for each of six (or seven) modes up
    in adjacent vertical columns, display each mode's registers (or
    shadows) in a single block, avoiding duplicate value displays.
    
    This also lets us shrink the line length to fits in standard 80
    character lines ... six or seven 18-character columns can't fit.
    
    Relabel "r13" as "sp", so it's more meaningful.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index a4c704e..6c6f2bf 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -39,26 +39,59 @@
 static const char *armv4_5_core_reg_list[] =
 {
 	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-	"r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
+	"r8", "r9", "r10", "r11", "r12", "sp_usr", "lr_usr", "pc",
 
-	"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
+	"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq",
 
-	"r13_irq", "lr_irq",
+	"sp_irq", "lr_irq",
 
-	"r13_svc", "lr_svc",
+	"sp_svc", "lr_svc",
 
-	"r13_abt", "lr_abt",
+	"sp_abt", "lr_abt",
 
-	"r13_und", "lr_und",
+	"sp_und", "lr_und",
 
 	"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
 
-	"r13_mon", "lr_mon", "spsr_mon",
+	"sp_mon", "lr_mon", "spsr_mon",
+};
+
+static const uint8_t arm_usr_indices[17] = {
+	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
+};
+
+static const uint8_t arm_fiq_indices[8] = {
+	16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
+};
+
+static const uint8_t arm_irq_indices[3] = {
+	23, 24, ARMV4_5_SPSR_IRQ,
+};
+
+static const uint8_t arm_svc_indices[3] = {
+	25, 26, ARMV4_5_SPSR_SVC,
+};
+
+static const uint8_t arm_abt_indices[3] = {
+	27, 28, ARMV4_5_SPSR_ABT,
+};
+
+static const uint8_t arm_und_indices[3] = {
+	29, 30, ARMV4_5_SPSR_UND,
+};
+
+static const uint8_t arm_mon_indices[3] = {
+	37, 38, ARM_SPSR_MON,
 };
 
 static const struct {
 	const char *name;
-	unsigned psr;
+	unsigned short psr;
+	/* For user and system modes, these list indices for all registers.
+	 * otherwise they're just indices for the shadow registers and SPSR.
+	 */
+	unsigned short n_indices;
+	const uint8_t *indices;
 } arm_mode_data[] = {
 	/* Seven modes are standard from ARM7 on. "System" and "User" share
 	 * the same registers; other modes shadow from 3 to 8 registers.
@@ -66,30 +99,44 @@ static const struct {
 	{
 		.name = "User",
 		.psr = ARMV4_5_MODE_USR,
+		.n_indices = ARRAY_SIZE(arm_usr_indices),
+		.indices = arm_usr_indices,
 	},
 	{
 		.name = "FIQ",
 		.psr = ARMV4_5_MODE_FIQ,
+		.n_indices = ARRAY_SIZE(arm_fiq_indices),
+		.indices = arm_fiq_indices,
 	},
 	{
 		.name = "Supervisor",
 		.psr = ARMV4_5_MODE_SVC,
+		.n_indices = ARRAY_SIZE(arm_svc_indices),
+		.indices = arm_svc_indices,
 	},
 	{
 		.name = "Abort",
 		.psr = ARMV4_5_MODE_ABT,
+		.n_indices = ARRAY_SIZE(arm_abt_indices),
+		.indices = arm_abt_indices,
 	},
 	{
 		.name = "IRQ",
 		.psr = ARMV4_5_MODE_IRQ,
+		.n_indices = ARRAY_SIZE(arm_irq_indices),
+		.indices = arm_irq_indices,
 	},
 	{
-		.name = "Undefined" /* instruction */,
+		.name = "Undefined instruction",
 		.psr = ARMV4_5_MODE_UND,
+		.n_indices = ARRAY_SIZE(arm_und_indices),
+		.indices = arm_und_indices,
 	},
 	{
 		.name = "System",
 		.psr = ARMV4_5_MODE_SYS,
+		.n_indices = ARRAY_SIZE(arm_usr_indices),
+		.indices = arm_usr_indices,
 	},
 	/* TrustZone "Security Extensions" add a secure monitor mode.
 	 * This is distinct from a "debug monitor" which can support
@@ -98,6 +145,8 @@ static const struct {
 	{
 		.name = "Secure Monitor",
 		.psr = ARM_MODE_MON,
+		.n_indices = ARRAY_SIZE(arm_mon_indices),
+		.indices = arm_mon_indices,
 	},
 };
 
@@ -461,11 +510,10 @@ int armv4_5_arch_state(struct target *target)
 
 COMMAND_HANDLER(handle_armv4_5_reg_command)
 {
-	char output[128];
-	int output_len;
-	int mode, num;
 	struct target *target = get_current_target(CMD_CTX);
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	unsigned num_regs;
+	struct reg *regs;
 
 	if (!is_arm(armv4_5))
 	{
@@ -476,7 +524,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 	if (target->state != TARGET_HALTED)
 	{
 		command_print(CMD_CTX, "error: target must be halted for register accesses");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -488,31 +536,61 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 		return ERROR_FAIL;
 	}
 
-	for (num = 0; num <= 15; num++)
-	{
-		output_len = 0;
-		for (mode = 0; mode < 6; mode++)
-		{
-			if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
-			{
-				armv4_5->full_context(target);
-			}
-			output_len += snprintf(output + output_len,
-					       128 - output_len,
+	num_regs = armv4_5->core_cache->num_regs;
+	regs = armv4_5->core_cache->reg_list;
+
+	for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
+		const char *name;
+		char *sep = "\n";
+		char *shadow = "";
+
+		/* label this bank of registers (or shadows) */
+		switch (arm_mode_data[mode].psr) {
+		case ARMV4_5_MODE_SYS:
+			continue;
+		case ARMV4_5_MODE_USR:
+			name = "System and User";
+			sep = "";
+			break;
+		case ARM_MODE_MON:
+			if (armv4_5->core_type != ARM_MODE_MON)
+				continue;
+			/* FALLTHROUGH */
+		default:
+			name = arm_mode_data[mode].name;
+			shadow = "shadow ";
+			break;
+		}
+		command_print(CMD_CTX, "%s%s mode %sregisters",
+				sep, name, shadow);
+
+		/* display N rows of up to 4 registers each */
+		for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
+			char output[80];
+			int output_len = 0;
+
+			for (unsigned j = 0; j < 4; j++, i++) {
+				uint32_t value;
+				struct reg *reg = regs;
+
+				if (i >= arm_mode_data[mode].n_indices)
+					break;
+
+				reg += arm_mode_data[mode].indices[i];
+
+				/* REVISIT be smarter about faults... */
+				if (!reg->valid)
+					armv4_5->full_context(target);
+
+				value = buf_get_u32(reg->value, 0, 32);
+				output_len += snprintf(output + output_len,
+						sizeof(output) - output_len,
 					       "%8s: %8.8" PRIx32 " ",
-					       ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
-					       buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
+					       reg->name, value);
+			}
+			command_print(CMD_CTX, "%s", output);
 		}
-		command_print(CMD_CTX, "%s", output);
 	}
-	command_print(CMD_CTX,
-		      "    cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
-			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
-			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
-			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
-			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
-			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
-			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv4_5.c |  148 ++++++++++++++++++++++++++++++++++++++------------
 1 files changed, 113 insertions(+), 35 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-470-gf0c9e89

From: David B. <dbr...@us...> - 2009-11-19 00:05:25

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb (commit)
      from  94dba423137d25fbe898fe7b04c451c6225a0079 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit f0c9e89e1a1747bf2bf40d42f3c7e795f73d41bb
Author: David Brownell <dbr...@us...>
Date:   Wed Nov 18 15:04:58 2009 -0800

    Cortex-A8: xPSR handling updates
    
    When we read the CPSR on debug entry, update the CPSR cache in all
    cases, not just when the current processor state is User or System.
    
    Plus minor cleanup of how the (too-many) other registers' cache
    entries get updated.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 37e5e3e..fc78844 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -570,6 +570,7 @@ static int cortex_a8_debug_entry(struct target *target)
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
+	struct reg *reg;
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
@@ -606,6 +607,9 @@ static int cortex_a8_debug_entry(struct target *target)
 	/* First load register acessible through core debug port*/
 	if (!regfile_working_area)
 	{
+		/* FIXME we don't actually need all these registers;
+		 * reading them slows us down.  Just R0, PC, CPSR...
+		 */
 		for (i = 0; i <= 15; i++)
 			cortex_a8_dap_read_coreregister_u32(target,
 					&regfile[i], i);
@@ -619,33 +623,32 @@ static int cortex_a8_debug_entry(struct target *target)
 		target_free_working_area(target, regfile_working_area);
 	}
 
+	/* read Current PSR */
 	cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
 	pc = regfile[15];
 	dap_ap_select(swjdp, swjdp_debugap);
 	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
 	armv4_5->core_mode = cpsr & 0x1F;
-	armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
+	armv7a->core_state = (cpsr & 0x20)
+			? ARMV7A_STATE_THUMB
+			: ARMV7A_STATE_ARM;
+
+	/* update cache */
+	reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
+	buf_set_u32(reg->value, 0, 32, cpsr);
+	reg->valid = 1;
+	reg->dirty = 0;
 
 	for (i = 0; i <= ARM_PC; i++)
 	{
-		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, i).value,
-				0, 32, regfile[i]);
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, i).valid = 1;
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, i).dirty = 0;
-	}
+		reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, i);
 
-	/* FIXME for exception states, this caches CPSR as SPSR!! */
-	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 16).value,
-			0, 32, cpsr);
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 16).valid = 1;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 16).dirty = 0;
+		buf_set_u32(reg->value, 0, 32, regfile[i]);
+		reg->valid = 1;
+		reg->dirty = 0;
+	}
 
 	/* Fixup PC Resume Address */
 	if (armv7a->core_state == ARMV7A_STATE_THUMB)

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_a8.c |   37 ++++++++++++++++++++-----------------
 1 files changed, 20 insertions(+), 17 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-469-g94dba42

From: David B. <dbr...@us...> - 2009-11-18 23:49:37

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  94dba423137d25fbe898fe7b04c451c6225a0079 (commit)
      from  f5093e160534c269b8bc3590f5809ed3baead56f (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 94dba423137d25fbe898fe7b04c451c6225a0079
Author: David Brownell <dbr...@us...>
Date:   Wed Nov 18 14:49:22 2009 -0800

    ARM: add a default full_context() method
    
    If the core doesn't provide an optimized version of this
    method, provide one without core-specific optimizations.
    Use this to make Cortex-A8 support the "arm reg" command.
    
    Related: make the two register access methods properly static,
    have the "set" log a "not halted" error too, and make sure
    that the "valid" flag is set on successful reads.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 562dc1f..a4c704e 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -299,7 +299,7 @@ static void arm_gdb_dummy_init(void)
 	register_init_dummy(&arm_gdb_dummy_fps_reg);
 }
 
-int armv4_5_get_core_reg(struct reg *reg)
+static int armv4_5_get_core_reg(struct reg *reg)
 {
 	int retval;
 	struct armv4_5_core_reg *armv4_5 = reg->arch_info;
@@ -311,13 +311,14 @@ int armv4_5_get_core_reg(struct reg *reg)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	/* retval = armv4_5->armv4_5_common->full_context(target); */
 	retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
+	if (retval == ERROR_OK)
+		reg->valid = 1;
 
 	return retval;
 }
 
-int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
+static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 {
 	struct armv4_5_core_reg *armv4_5 = reg->arch_info;
 	struct target *target = armv4_5->target;
@@ -326,6 +327,7 @@ int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 
 	if (target->state != TARGET_HALTED)
 	{
+		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
@@ -1038,6 +1040,21 @@ int arm_blank_check_memory(struct target *target,
 	return ERROR_OK;
 }
 
+static int arm_full_context(struct target *target)
+{
+	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	unsigned num_regs = armv4_5->core_cache->num_regs;
+	struct reg *reg = armv4_5->core_cache->reg_list;
+	int retval = ERROR_OK;
+
+	for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
+		if (reg->valid)
+			continue;
+		retval = armv4_5_get_core_reg(reg);
+	}
+	return retval;
+}
+
 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
 {
 	target->arch_info = armv4_5;
@@ -1049,5 +1066,9 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
 	/* core_type may be overridden by subtype logic */
 	armv4_5->core_type = ARMV4_5_MODE_ANY;
 
+	/* default full_context() has no core-specific optimizations */
+	if (!armv4_5->full_context && armv4_5->read_core_reg)
+		armv4_5->full_context = arm_full_context;
+
 	return ERROR_OK;
 }
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index b69f182..37e5e3e 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1456,10 +1456,6 @@ int cortex_a8_init_arch_info(struct target *target,
 	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
-	/* REVISIT v7a setup should be in a v7a-specific routine */
-	armv4_5_init_arch_info(target, armv4_5);
-	armv7a->common_magic = ARMV7_COMMON_MAGIC;
-
 	/* Setup struct cortex_a8_common */
 	cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
 	armv4_5->arch_info = armv7a;
@@ -1503,12 +1499,10 @@ LOG_DEBUG(" ");
 
 	armv4_5->read_core_reg = cortex_a8_read_core_reg;
 	armv4_5->write_core_reg = cortex_a8_write_core_reg;
-//	armv4_5->full_context = arm7_9_full_context;
 
-//	armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
-//	armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
-//	armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
-//	armv4_5->write_core_reg = armv4_5_write_core_reg;
+	/* REVISIT v7a setup should be in a v7a-specific routine */
+	armv4_5_init_arch_info(target, armv4_5);
+	armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
 	target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv4_5.c   |   27 ++++++++++++++++++++++++---
 src/target/cortex_a8.c |   12 +++---------
 2 files changed, 27 insertions(+), 12 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-468-gf5093e1

From: David B. <dbr...@us...> - 2009-11-18 23:46:31

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  f5093e160534c269b8bc3590f5809ed3baead56f (commit)
      from  8a6d4ced4c0d17626c3875d5f8819efa3ac0f155 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit f5093e160534c269b8bc3590f5809ed3baead56f
Author: David Brownell <dbr...@us...>
Date:   Wed Nov 18 14:46:14 2009 -0800

    ARM: simplify ARMv7-A register handling
    
    ARMv7-A doesn't need to duplicate all the standard ARM code
    for register handling.
    
     - Switch Cortex-A8 to use the standard register code
     - Remove duplicated infrastructure from ARMv7-A
     - Have ARMv7-A arch_state() show CPSR, like other ARMs
    
    Add comments to show where the Cortex-A8 isn't actually doing
    the right thing for register reads/writes, unless core happens
    to be in the right mode to start with.  (Looks like maybe there
    may be generic confusion between saved/current PSR values in all
    the ARM code ...)
    
    Make related ARMv7-A and Cortex-A8 symbols properly static.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index e13b33b..6aa9d2f 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -34,108 +34,12 @@
 #include <unistd.h>
 
 
-char* armv7a_core_reg_list[] =
-{
-	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-	"r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
-	"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
-	"r13_irq", "lr_irq",
-	"r13_svc", "lr_svc",
-	"r13_abt", "lr_abt",
-	"r13_und", "lr_und",
-	"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
-	"r13_mon", "lr_mon", "spsr_mon"
-};
-
-char* armv7a_state_strings[] =
+static const char *armv7a_state_strings[] =
 {
 	"ARM", "Thumb", "Jazelle", "ThumbEE"
 };
 
-struct armv7a_core_reg armv7a_core_reg_list_arch_info[] =
-{
-	{0, ARMV4_5_MODE_ANY, NULL, NULL},
-	{1, ARMV4_5_MODE_ANY, NULL, NULL},
-	{2, ARMV4_5_MODE_ANY, NULL, NULL},
-	{3, ARMV4_5_MODE_ANY, NULL, NULL},
-	{4, ARMV4_5_MODE_ANY, NULL, NULL},
-	{5, ARMV4_5_MODE_ANY, NULL, NULL},
-	{6, ARMV4_5_MODE_ANY, NULL, NULL},
-	{7, ARMV4_5_MODE_ANY, NULL, NULL},
-	{8, ARMV4_5_MODE_ANY, NULL, NULL},
-	{9, ARMV4_5_MODE_ANY, NULL, NULL},
-	{10, ARMV4_5_MODE_ANY, NULL, NULL},
-	{11, ARMV4_5_MODE_ANY, NULL, NULL},
-	{12, ARMV4_5_MODE_ANY, NULL, NULL},
-	{13, ARMV4_5_MODE_USR, NULL, NULL},
-	{14, ARMV4_5_MODE_USR, NULL, NULL},
-	{15, ARMV4_5_MODE_ANY, NULL, NULL},
-
-	{8, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{9, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{10, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{11, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{12, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{13, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{14, ARMV4_5_MODE_FIQ, NULL, NULL},
-
-	{13, ARMV4_5_MODE_IRQ, NULL, NULL},
-	{14, ARMV4_5_MODE_IRQ, NULL, NULL},
-
-	{13, ARMV4_5_MODE_SVC, NULL, NULL},
-	{14, ARMV4_5_MODE_SVC, NULL, NULL},
-
-	{13, ARMV4_5_MODE_ABT, NULL, NULL},
-	{14, ARMV4_5_MODE_ABT, NULL, NULL},
-
-	{13, ARMV4_5_MODE_UND, NULL, NULL},
-	{14, ARMV4_5_MODE_UND, NULL, NULL},
-
-	{16, ARMV4_5_MODE_ANY, NULL, NULL},
-	{16, ARMV4_5_MODE_FIQ, NULL, NULL},
-	{16, ARMV4_5_MODE_IRQ, NULL, NULL},
-	{16, ARMV4_5_MODE_SVC, NULL, NULL},
-	{16, ARMV4_5_MODE_ABT, NULL, NULL},
-	{16, ARMV4_5_MODE_UND, NULL, NULL},
-
-	{13, ARMV7A_MODE_MON, NULL, NULL},
-	{14, ARMV7A_MODE_MON, NULL, NULL},
-	{16, ARMV7A_MODE_MON, NULL, NULL}
-};
-
-/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
-int armv7a_core_reg_map[8][17] =
-{
-	{	/* USR */
-		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
-	},
-	{	/* FIQ */
-		0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
-	},
-	{	/* IRQ */
-		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
-	},
-	{	/* SVC */
-		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
-	},
-	{	/* ABT */
-		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
-	},
-	{	/* UND */
-		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
-	},
-	{	/* SYS */
-		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
-	},
-	{	/* MON */
-		/* TODO Fix the register mapping for mon, we need r13_mon,
-		 * r14_mon and spsr_mon
-		 */
-		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
-	}
-};
-
-void armv7a_show_fault_registers(struct target *target)
+static void armv7a_show_fault_registers(struct target *target)
 {
 	uint32_t dfsr, ifsr, dfar, ifar;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -169,16 +73,14 @@ int armv7a_arch_state(struct target *target)
 	}
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			 "%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
+			 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			 "MMU: %s, D-Cache: %s, I-Cache: %s",
 		 armv7a_state_strings[armv7a->core_state],
 		 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 				target->debug_reason)->name,
 		 arm_mode_name(armv4_5->core_mode),
-		 armv7a_core_reg_list[armv7a_core_reg_map[
-			armv7a_mode_to_number(armv4_5->core_mode)][16]],
-		 buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 16).value, 0, 32),
+		 buf_get_u32(armv4_5->core_cache
+				->reg_list[ARMV4_5_CPSR].value, 0, 32),
 		 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 		 state[armv7a->armv4_5_mmu.mmu_enabled],
 		 state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index e781e72..b008361 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -45,15 +45,6 @@ typedef enum armv7a_state
 	ARMV7A_STATE_THUMBEE,
 } armv7a_state_t;
 
-extern char *armv7a_state_strings[];
-
-extern int armv7a_core_reg_map[8][17];
-
-#define ARMV7A_CORE_REG_MODE(cache, mode, num) \
-		cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
-#define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
-		cache->reg_list[armv7a_core_reg_map[mode][num]]
-
 enum
 {
 	ARM_PC  = 15,
@@ -102,9 +93,6 @@ struct armv7a_common
 	struct armv4_5_mmu_common armv4_5_mmu;
 	struct arm armv4_5_common;
 
-//	int (*full_context)(struct target *target);
-//	int (*read_core_reg)(struct target *target, int num, enum armv7a_mode mode);
-//	int (*write_core_reg)(struct target *target, int num, enum armv7a_mode mode, u32 value);
 	int (*read_cp15)(struct target *target,
 			uint32_t op1, uint32_t op2,
 			uint32_t CRn, uint32_t CRm, uint32_t *value);
@@ -149,44 +137,4 @@ struct reg_cache *armv7a_build_reg_cache(struct target *target,
 int armv7a_register_commands(struct command_context *cmd_ctx);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 
-/* map psr mode bits to linear number */
-static inline int armv7a_mode_to_number(enum armv7a_mode mode)
-{
-	switch (mode)
-	{
-		case ARMV7A_MODE_USR: return 0; break;
-		case ARMV7A_MODE_FIQ: return 1; break;
-		case ARMV7A_MODE_IRQ: return 2; break;
-		case ARMV7A_MODE_SVC: return 3; break;
-		case ARMV7A_MODE_ABT: return 4; break;
-		case ARMV7A_MODE_UND: return 5; break;
-		case ARMV7A_MODE_SYS: return 6; break;
-		case ARMV7A_MODE_MON: return 7; break;
-		case ARMV7A_MODE_ANY: return 0; break;	/* map MODE_ANY to user mode */
-		default:
-			LOG_ERROR("invalid mode value encountered, val %d", mode);
-			return -1;
-	}
-}
-
-/* map linear number to mode bits */
-static inline enum armv7a_mode armv7a_number_to_mode(int number)
-{
-	switch(number)
-	{
-		case 0: return ARMV7A_MODE_USR; break;
-		case 1: return ARMV7A_MODE_FIQ; break;
-		case 2: return ARMV7A_MODE_IRQ; break;
-		case 3: return ARMV7A_MODE_SVC; break;
-		case 4: return ARMV7A_MODE_ABT; break;
-		case 5: return ARMV7A_MODE_UND; break;
-		case 6: return ARMV7A_MODE_SYS; break;
-		case 7: return ARMV7A_MODE_MON; break;
-		default:
-			LOG_ERROR("mode index out of bounds");
-			return ARMV7A_MODE_ANY;
-	}
-};
-
-
 #endif /* ARMV4_5_H */
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index f8ff392..b69f182 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -242,16 +242,18 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 
 	if (reg < 15)
 	{
-		/* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+		/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
 		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
 	}
 	else if (reg == 15)
 	{
+		/* "MOV r0, r15"; then move r0 to DCCTX */
 		cortex_a8_exec_opcode(target, 0xE1A0000F);
 		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
 	}
 	else if (reg == 16)
 	{
+		/* "MRS r0, CPSR"; then move r0 to DCCTX */
 		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
 		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
 	}
@@ -480,7 +482,7 @@ static int cortex_a8_resume(struct target *target, int current,
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	resume_pc = buf_get_u32(
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 15).value,
 			0, 32);
 	if (!current)
@@ -501,12 +503,12 @@ static int cortex_a8_resume(struct target *target, int current,
 		resume_pc |= 0x1;
 	}
 	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 15).value,
 			0, 32, resume_pc);
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 			armv4_5->core_mode, 15).dirty = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 			armv4_5->core_mode, 15).valid = 1;
 
 	cortex_a8_restore_context(target);
@@ -627,19 +629,23 @@ static int cortex_a8_debug_entry(struct target *target)
 
 	for (i = 0; i <= ARM_PC; i++)
 	{
-		buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 					armv4_5->core_mode, i).value,
 				0, 32, regfile[i]);
-		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, i).valid = 1;
-		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, i).dirty = 0;
 	}
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+
+	/* FIXME for exception states, this caches CPSR as SPSR!! */
+	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 16).value,
 			0, 32, cpsr);
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+			armv4_5->core_mode, 16).valid = 1;
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+			armv4_5->core_mode, 16).dirty = 0;
 
 	/* Fixup PC Resume Address */
 	if (armv7a->core_state == ARMV7A_STATE_THUMB)
@@ -652,15 +658,15 @@ static int cortex_a8_debug_entry(struct target *target)
 		// ARM state
 		regfile[ARM_PC] -= 8;
 	}
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, ARM_PC).value,
 			0, 32, regfile[ARM_PC]);
 
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-		.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
+		.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 0).valid;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
-		.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
+		.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 15).valid;
 
 #if 0
@@ -738,13 +744,13 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	if (!current)
 	{
-		buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 					armv4_5->core_mode, ARM_PC).value,
 				0, 32, address);
 	}
 	else
 	{
-		address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+		address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 					armv4_5->core_mode, ARM_PC).value,
 				0, 32);
 	}
@@ -756,7 +762,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	handle_breakpoints = 1;
 	if (handle_breakpoints) {
 		breakpoint = breakpoint_find(target,
-				buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				buf_get_u32(ARMV4_5_CORE_REG_MODE(
+					armv4_5->core_cache,
 					armv4_5->core_mode, 15).value,
 			0, 32));
 		if (breakpoint)
@@ -812,10 +819,11 @@ static int cortex_a8_restore_context(struct target *target)
 
 	for (i = 15; i >= 0; i--)
 	{
-		if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+		if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 					armv4_5->core_mode, i).dirty)
 		{
-			value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
+						armv4_5->core_cache,
 						armv4_5->core_mode, i).value,
 					0, 32);
 			/* TODO Check return values */
@@ -859,13 +867,13 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num,
 
 	/* Register other than r0 - r14 uses r0 for access */
 	if (num > 14)
-		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 0).dirty =
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 0).valid;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 15).dirty =
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 15).valid;
 
 	return ERROR_OK;
@@ -895,9 +903,9 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
 		if (retval != ERROR_OK)
 		{
 			LOG_ERROR("JTAG failure %i", retval);
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 					armv4_5->core_mode, num).dirty =
-				ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 					armv4_5->core_mode, num).valid;
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -920,6 +928,8 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+	/* FIXME cortex may not be in "mode" ... */
+
 	cortex_a8_dap_read_coreregister_u32(target, &value, num);
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -927,28 +937,30 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
 		return retval;
 	}
 
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
 			mode, num).value, 0, 32, value);
 
 	return ERROR_OK;
 }
 
-int cortex_a8_write_core_reg(struct target *target, int num,
+static int cortex_a8_write_core_reg(struct target *target, int num,
 		enum armv4_5_mode mode, uint32_t value)
 {
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+	/* FIXME cortex may not be in "mode" ... */
+
 	cortex_a8_dap_write_coreregister_u32(target, value, num);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
 
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7a.c    |  108 ++---------------------------------------------
 src/target/armv7a.h    |   52 -----------------------
 src/target/cortex_a8.c |   78 ++++++++++++++++++++---------------
 3 files changed, 50 insertions(+), 188 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-467-g8a6d4ce

From: David B. <dbr...@us...> - 2009-11-18 22:23:49

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  8a6d4ced4c0d17626c3875d5f8819efa3ac0f155 (commit)
       via  bbebfd9e134ec84a29dd68bc3661ead57435a4c3 (commit)
      from  9b1f9810b090958bb4a669034173a01683c6e3e9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 8a6d4ced4c0d17626c3875d5f8819efa3ac0f155
Author: David Brownell <dbr...@us...>
Date:   Wed Nov 18 13:23:00 2009 -0800

    ARM: setup "secure monitor mode" shadow regs
    
    Teach the "armv4_5" register code to understand about the
    secure monitor mode:
    
     - Add the other three shadowed registers to the arrays
     - Support another internal mode number (sigh) in mappings
     - Catch malloc/calloc failures building that register cache
    
    This should kick in for Cortex-A8 and ARM1176.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 3e27ba4..562dc1f 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -38,7 +38,8 @@
 
 static const char *armv4_5_core_reg_list[] =
 {
-	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+	"r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
 
 	"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
 
@@ -50,7 +51,9 @@ static const char *armv4_5_core_reg_list[] =
 
 	"r13_und", "lr_und",
 
-	"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
+	"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
+
+	"r13_mon", "lr_mon", "spsr_mon",
 };
 
 static const struct {
@@ -139,6 +142,8 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode)
 		return 5;
 	case ARMV4_5_MODE_SYS:
 		return 6;
+	case ARM_MODE_MON:
+		return 7;
 	default:
 		LOG_ERROR("invalid mode value encountered %d", mode);
 		return -1;
@@ -163,6 +168,8 @@ enum armv4_5_mode armv4_5_number_to_mode(int number)
 		return ARMV4_5_MODE_UND;
 	case 6:
 		return ARMV4_5_MODE_SYS;
+	case 7:
+		return ARM_MODE_MON;
 	default:
 		LOG_ERROR("mode index out of bounds %d", number);
 		return ARMV4_5_MODE_ANY;
@@ -218,16 +225,20 @@ static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
 	{16, ARMV4_5_MODE_IRQ, NULL, NULL},
 	{16, ARMV4_5_MODE_SVC, NULL, NULL},
 	{16, ARMV4_5_MODE_ABT, NULL, NULL},
-	{16, ARMV4_5_MODE_UND, NULL, NULL}
+	{16, ARMV4_5_MODE_UND, NULL, NULL},
+
+	{13, ARM_MODE_MON, NULL, NULL},
+	{14, ARM_MODE_MON, NULL, NULL},
+	{16, ARM_MODE_MON, NULL, NULL},
 };
 
 /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
-const int armv4_5_core_reg_map[7][17] =
+const int armv4_5_core_reg_map[8][17] =
 {
 	{	/* USR */
 		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
 	},
-	{	/* FIQ */
+	{	/* FIQ (8 shadows of USR, vs normal 3) */
 		0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
 	},
 	{	/* IRQ */
@@ -242,8 +253,11 @@ const int armv4_5_core_reg_map[7][17] =
 	{	/* UND */
 		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
 	},
-	{	/* SYS */
+	{	/* SYS (same registers as USR) */
 		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
+	},
+	{	/* MON */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
 	}
 };
 
@@ -359,45 +373,62 @@ static const struct reg_arch_type arm_reg_type = {
 	.set = armv4_5_set_core_reg,
 };
 
+/** Marks the contents of the register cache as invalid (and clean). */
 int armv4_5_invalidate_core_regs(struct target *target)
 {
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	int i;
+	unsigned num_regs = armv4_5->core_cache->num_regs;
+	struct reg *reg = armv4_5->core_cache->reg_list;
 
-	for (i = 0; i < 37; i++)
-	{
-		armv4_5->core_cache->reg_list[i].valid = 0;
-		armv4_5->core_cache->reg_list[i].dirty = 0;
+	for (unsigned i = 0; i < num_regs; i++, reg++) {
+		reg->valid = 0;
+		reg->dirty = 0;
 	}
 
+	/* FIXME don't bother returning a value then */
 	return ERROR_OK;
 }
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
 {
-	int num_regs = 37;
+	int num_regs = ARRAY_SIZE(armv4_5_core_reg_list_arch_info);
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
-	struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
-	struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
+	struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
+	struct armv4_5_core_reg *arch_info = calloc(num_regs,
+					sizeof(struct armv4_5_core_reg));
 	int i;
 
-	cache->name = "arm v4/5 registers";
+	if (!cache || !reg_list || !arch_info) {
+		free(cache);
+		free(reg_list);
+		free(arch_info);
+		return NULL;
+	}
+
+	cache->name = "ARM registers";
 	cache->next = NULL;
 	cache->reg_list = reg_list;
-	cache->num_regs = num_regs;
+	cache->num_regs = 0;
 
-	for (i = 0; i < 37; i++)
+	for (i = 0; i < num_regs; i++)
 	{
+		/* Skip registers this core doesn't expose */
+		if (armv4_5_core_reg_list_arch_info[i].mode == ARM_MODE_MON
+				&& armv4_5_common->core_type != ARM_MODE_MON)
+			continue;
+
+		/* REVISIT handle Cortex-M, which only shadows R13/SP */
+
 		arch_info[i] = armv4_5_core_reg_list_arch_info[i];
 		arch_info[i].target = target;
 		arch_info[i].armv4_5_common = armv4_5_common;
 		reg_list[i].name = (char *) armv4_5_core_reg_list[i];
 		reg_list[i].size = 32;
 		reg_list[i].value = calloc(1, 4);
-		reg_list[i].dirty = 0;
-		reg_list[i].valid = 0;
 		reg_list[i].type = &arm_reg_type;
 		reg_list[i].arch_info = &arch_info[i];
+
+		cache->num_regs++;
 	}
 
 	return cache;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index f9aa4ba..e3d053c 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -56,7 +56,7 @@ typedef enum armv4_5_state
 
 extern char* armv4_5_state_strings[];
 
-extern const int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
@@ -69,7 +69,8 @@ enum
 	ARMV4_5_SPSR_IRQ = 33,
 	ARMV4_5_SPSR_SVC = 34,
 	ARMV4_5_SPSR_ABT = 35,
-	ARMV4_5_SPSR_UND = 36
+	ARMV4_5_SPSR_UND = 36,
+	ARM_SPSR_MON = 39,
 };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45

commit bbebfd9e134ec84a29dd68bc3661ead57435a4c3
Author: David Brownell <dbr...@us...>
Date:   Wed Nov 18 13:22:27 2009 -0800

    ARM: add "core_type" field to "struct arm"
    
    It's used to flag cores with the "TrustZone" extension,
    and is used in subsequent patches to set up support for
    the registers shadowed by its new secure monitor mode.
    
    The ARM1176 and Cortex-A8 both support this new mode.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 3a23585..6e007cf 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1780,6 +1780,11 @@ static int arm11_init_target(struct command_context *cmd_ctx,
 		struct target *target)
 {
 	/* Initialize anything we can set up without talking to the target */
+
+	/* FIXME Switch to use the standard build_reg_cache() not custom
+	 * code.  Do it from examine(), after we check whether we're
+	 * an arm1176 and thus support the Secure Monitor mode.
+	 */
 	return arm11_build_reg_cache(target);
 }
 
@@ -1787,7 +1792,7 @@ static int arm11_init_target(struct command_context *cmd_ctx,
 static int arm11_examine(struct target *target)
 {
 	int retval;
-
+	char *type;
 	FNC_INFO;
 	struct arm11_common *arm11 = target_to_arm11(target);
 
@@ -1818,13 +1823,21 @@ static int arm11_examine(struct target *target)
 
 	switch (arm11->device_id & 0x0FFFF000)
 	{
-	case 0x07B36000:	LOG_INFO("found ARM1136"); break;
-	case 0x07B56000:	LOG_INFO("found ARM1156"); break;
-	case 0x07B76000:	LOG_INFO("found ARM1176"); break;
+	case 0x07B36000:
+		type = "ARM1136";
+		break;
+	case 0x07B56000:
+		type = "ARM1156";
+		break;
+	case 0x07B76000:
+		arm11->arm.core_type = ARM_MODE_MON;
+		type = "ARM1176";
+		break;
 	default:
 		LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
 		return ERROR_FAIL;
 	}
+	LOG_INFO("found %s", type);
 
 	arm11->debug_version = (arm11->didr >> 16) & 0x0F;
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index d22e0f3..3e27ba4 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1015,5 +1015,8 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
 	armv4_5->core_state = ARMV4_5_STATE_ARM;
 	armv4_5->core_mode = ARMV4_5_MODE_USR;
 
+	/* core_type may be overridden by subtype logic */
+	armv4_5->core_type = ARMV4_5_MODE_ANY;
+
 	return ERROR_OK;
 }
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 81eac47..f9aa4ba 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -89,7 +89,15 @@ struct arm
 	int common_magic;
 	struct reg_cache *core_cache;
 
-	int /* armv4_5_mode */ core_mode;
+	/**
+	 * Indicates what registers are in the ARM state core register set.
+	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+	 * more registers are shadowed, for "Secure Monitor" mode.
+	 */
+	enum armv4_5_mode core_type;
+
+	enum armv4_5_mode core_mode;
 	enum armv4_5_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 04b3f87..f8ff392 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1423,6 +1423,8 @@ static void cortex_a8_build_reg_cache(struct target *target)
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+	armv4_5->core_type = ARM_MODE_MON;
+
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 	armv4_5->core_cache = (*cache_p);
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11.c     |   21 +++++++++++--
 src/target/armv4_5.c   |   72 +++++++++++++++++++++++++++++++++++------------
 src/target/armv4_5.h   |   15 ++++++++--
 src/target/cortex_a8.c |    2 +
 4 files changed, 84 insertions(+), 26 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-465-g9b1f981

From: Zach W. <zw...@us...> - 2009-11-18 21:03:19

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  9b1f9810b090958bb4a669034173a01683c6e3e9 (commit)
      from  5e229bbf87fbb5a809553526edf0186dd3dd5cf8 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 9b1f9810b090958bb4a669034173a01683c6e3e9
Author: Zachary T Welch <zw...@su...>
Date:   Wed Nov 18 11:56:24 2009 -0800

    fix segfault at startup
    
    The previous changes to move the startup TCL code resulted in segfaults
    during startup.  This seemingly innocuous patch fixes the problem.
    I would explain why changing from 'foo[]' to '*foo' caused this issue,
    but the difference seems superficial.  For now, this hot fix will do,
    but this issue might bear further scrutiny.

diff --git a/src/openocd.h b/src/openocd.h
index 70e3ee0..a91d46f 100644
--- a/src/openocd.h
+++ b/src/openocd.h
@@ -37,6 +37,6 @@ void openocd_sleep_prelude(void);
 void openocd_sleep_postlude(void);
 
 /// provides a hard-coded command environment setup
-extern const char *openocd_startup_tcl;
+extern const char openocd_startup_tcl[];
 
 #endif

-----------------------------------------------------------------------

Summary of changes:
 src/openocd.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-464-g5e229bb

From: Zach W. <zw...@us...> - 2009-11-18 16:41:38

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  5e229bbf87fbb5a809553526edf0186dd3dd5cf8 (commit)
       via  cb7dbc1af41068f826246beb53870c01d8973bb8 (commit)
       via  903daa796a226152fe56245758c8388b79d12988 (commit)
      from  59f32cbe53ccd8725e01968fcbc716cc5768a36b (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 5e229bbf87fbb5a809553526edf0186dd3dd5cf8
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 09:15:09 2009 -0800

    pass startup_tcl to command_init
    
    Removes external linkage from helper module, making the startup
    code a parameter to a new command context's initialization routine.

diff --git a/src/Makefile.am b/src/Makefile.am
index 7a88681..8f96b05 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -116,7 +116,7 @@ BIN2C = $(builddir)/helper/bin2char$(EXEEXT_FOR_BUILD)
 
 # Convert .tcl to cfile
 startup_tcl.c: startup.tcl $(BIN2C)
-	$(BIN2C) startup_tcl < $< > $@ || rm -f $@
+	$(BIN2C) openocd_startup_tcl < $< > $@ || rm -f $@
 
 # add startup_tcl.c to make clean list
 CLEANFILES = startup.tcl startup_tcl.c
diff --git a/src/helper/command.c b/src/helper/command.c
index ad09e3d..708a802 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -766,10 +766,9 @@ COMMAND_HANDLER(handle_fast_command)
 }
 
 
-struct command_context* command_init()
+struct command_context* command_init(const char *startup_tcl)
 {
 	struct command_context* context = malloc(sizeof(struct command_context));
-	extern const char startup_tcl[];
 	const char *HostOs;
 
 	context->mode = COMMAND_EXEC;
diff --git a/src/helper/command.h b/src/helper/command.h
index 62231fc..05088b5 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -190,7 +190,10 @@ struct command_context* copy_command_context(struct command_context* context);
 
 int command_context_mode(struct command_context *context, enum command_mode mode);
 
-struct command_context* command_init(void);
+/**
+ * Creates a new command context using the startup TCL provided.
+ */
+struct command_context* command_init(const char *startup_tcl);
 int command_done(struct command_context *context);
 
 void command_print(struct command_context *context, const char *format, ...)
diff --git a/src/openocd.c b/src/openocd.c
index 9edd611..b7781a6 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -28,6 +28,7 @@
 #include "config.h"
 #endif
 
+#include "openocd.h"
 #include "jtag.h"
 #include "configuration.h"
 #include "xsvf.h"
@@ -168,7 +169,7 @@ struct command_context *setup_command_handler(void)
 {
 	struct command_context *cmd_ctx;
 
-	global_cmd_ctx = cmd_ctx = command_init();
+	global_cmd_ctx = cmd_ctx = command_init(openocd_startup_tcl);
 
 	register_command(cmd_ctx, NULL, "version", handle_version_command,
 					 COMMAND_EXEC, "show OpenOCD version");
diff --git a/src/openocd.h b/src/openocd.h
index 1bf6b7e..70e3ee0 100644
--- a/src/openocd.h
+++ b/src/openocd.h
@@ -36,4 +36,7 @@ void openocd_sleep_prelude(void);
 /// used by the server_loop() function in src/server/server.c
 void openocd_sleep_postlude(void);
 
+/// provides a hard-coded command environment setup
+extern const char *openocd_startup_tcl;
+
 #endif

commit cb7dbc1af41068f826246beb53870c01d8973bb8
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 08:29:20 2009 -0800

    split startup.tcl file across modules
    
    Moves definitions for each layer into their own file, eliminating
    layering violations in the built-in TCL code.  Updates src/Makefile.am
    rules to include all files in the final startup.tcl input file, and
    others Makefile.am rules to distribute the new files in our packages.

diff --git a/src/Makefile.am b/src/Makefile.am
index 2f17ba4..7a88681 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -99,7 +99,11 @@ libopenocd_la_LIBADD += -lmicrohttpd
 endif
 
 STARTUP_TCL_SRCS = \
-	$(srcdir)/helper/startup.tcl
+	$(srcdir)/helper/startup.tcl \
+	$(srcdir)/jtag/startup.tcl \
+	$(srcdir)/target/startup.tcl \
+	$(srcdir)/flash/startup.tcl \
+	$(srcdir)/server/startup.tcl
 
 EXTRA_DIST = $(STARTUP_TCL_SRCS)
 
diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index bbcc34c..b687182 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -79,4 +79,6 @@ noinst_HEADERS = \
 	s3c24xx_nand.h \
 	s3c24xx_regs_nand.h
 
+EXTRA_DIST = startup.tcl
+
 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
new file mode 100644
index 0000000..fcebbe0
--- /dev/null
+++ b/src/flash/startup.tcl
@@ -0,0 +1,16 @@
+# Defines basic Tcl procs for OpenOCD flash module
+
+# Show flash in human readable form
+# This is an example of a human readable form of a low level fn
+proc flash_banks {} {
+	set i 0
+	set result ""
+	foreach {a} [ocd_flash_banks] {
+		if {$i > 0} {
+			set result "$result\n"
+		}
+		set result [format "$result#%d: %s at 0x%08x, size 0x%08x, buswidth %d, chipwidth %d" $i $a(name) $a(base) $a(size) $a(bus_width) $a(chip_width)]
+		set i [expr $i+1]
+	}
+	return $result
+}
diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am
index 9557f5b..22b3c33 100644
--- a/src/helper/Makefile.am
+++ b/src/helper/Makefile.am
@@ -50,6 +50,8 @@ noinst_HEADERS = \
 	system.h \
 	bin2char.c
 
+EXTRA_DIST = startup.tcl
+
 BIN2C = bin2char$(EXEEXT_FOR_BUILD)
 
 BUILT_SOURCES = $(BIN2C)
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index 096f03a..eefb690 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -1,11 +1,8 @@
-#
-# Defines basic Tcl procs that must be there for
-# OpenOCD to work.
+# Defines basic Tcl procs that must exist for OpenOCD scripts to work.
 #
 # Embedded into OpenOCD executable
 #
 
-
 # Help text list. A list of command + help text pairs.
 #
 # Commands can be more than one word and they are stored
@@ -22,21 +19,6 @@ proc get_help_text {} {
 }
 
 
-# Show flash in human readable form
-# This is an example of a human readable form of a low level fn
-proc flash_banks {} {
-	set i 0
-	set result ""
-	foreach {a} [ocd_flash_banks] {
-		if {$i > 0} {
-			set result "$result\n"
-		}
-		set result [format "$result#%d: %s at 0x%08x, size 0x%08x, buswidth %d, chipwidth %d" $i $a(name) $a(base) $a(size) $a(bus_width) $a(chip_width)]
-		set i [expr $i+1]
-	}
-	return $result
-}
-
 # We need to explicitly redirect this to the OpenOCD command
 # as Tcl defines the exit proc
 proc exit {} {
@@ -133,207 +115,6 @@ proc script {filename} {
 
 add_help_text script "<filename> - filename of OpenOCD script (tcl) to run"
 
-# Handle GDB 'R' packet. Can be overriden by configuration script,
-# but it's not something one would expect target scripts to do
-# normally
-proc ocd_gdb_restart {target_id} {
-	# Fix!!! we're resetting all targets here! Really we should reset only
-	# one target
-	reset halt
-}
-
-#########
-
-# Temporary migration aid.  May be removed starting in January 2011.
-proc armv4_5 params {
-	echo "DEPRECATED! use 'arm $params' not 'armv4_5 $params'"
-	arm $params
-}
-
-#########
-
-# This reset logic may be overridden by board/target/... scripts as needed
-# to provide a reset that, if possible, is close to a power-up reset.
-#
-# Exit requirements include:  (a) JTAG must be working, (b) the scan
-# chain was validated with "jtag arp_init" (or equivalent), (c) nothing
-# stays in reset.  No TAP-specific scans were performed.  It's OK if
-# some targets haven't been reset yet; they may need TAP-specific scans.
-#
-# The "mode" values include:  halt, init, run (from "reset" command);
-# startup (at OpenOCD server startup, when JTAG may not yet work); and
-# potentially more (for reset types like cold, warm, etc)
-proc init_reset { mode } {
-	jtag arp_init-reset
-}
-
-
-global in_process_reset
-set in_process_reset 0
-
-# Catch reset recursion
-proc ocd_process_reset { MODE } {
-	global in_process_reset
-	if {$in_process_reset} {
-		set in_process_reset 0
-		return -code error "'reset' can not be invoked recursively"
-	}
-
-	set in_process_reset 1
-	set success [expr [catch {ocd_process_reset_inner $MODE} result]==0]
-	set in_process_reset 0
-
-	if {$success} {
-		return $result
-	} else {
-		return -code error $result
-	}
-}
-
-proc ocd_process_reset_inner { MODE } {
-	set targets [target names]
-
-	# If this target must be halted...
-	set halt -1
-	if { 0 == [string compare $MODE halt] } {
-		set halt 1
-	}
-	if { 0 == [string compare $MODE init] } {
-		set halt 1;
-	}
-	if { 0 == [string compare $MODE run ] } {
-		set halt 0;
-	}
-	if { $halt < 0 } {
-		return -error "Invalid mode: $MODE, must be one of: halt, init, or run";
-	}
-
-	# Target event handlers *might* change which TAPs are enabled
-	# or disabled, so we fire all of them.  But don't issue any
-	# target "arp_*" commands, which may issue JTAG transactions,
-	# unless we know the underlying TAP is active.
-	#
-	# NOTE:  ARP == "Advanced Reset Process" ... "advanced" is
-	# relative to a previous restrictive scheme
-
-	foreach t $targets {
-		# New event script.
-		$t invoke-event reset-start
-	}
-
-	# Use TRST or TMS/TCK operations to reset all the tap controllers.
-	# TAP reset events get reported; they might enable some taps.
-	init_reset $MODE
-
-	# Examine all targets on enabled taps.
-	foreach t $targets {
-		if {[jtag tapisenabled [$t cget -chain-position]]} {
-			$t arp_examine
-		}
-	}
-
-	# Assert SRST, and report the pre/post events.
-	# Note:  no target sees SRST before "pre" or after "post".
-	foreach t $targets {
-		$t invoke-event reset-assert-pre
-	}
-	foreach t $targets {
-		# C code needs to know if we expect to 'halt'
-		if {[jtag tapisenabled [$t cget -chain-position]]} {
-			$t arp_reset assert $halt
-		}
-	}
-	foreach t $targets {
-		$t invoke-event reset-assert-post
-	}
-
-	# Now de-assert SRST, and report the pre/post events.
-	# Note:  no target sees !SRST before "pre" or after "post".
-	foreach t $targets {
-		$t invoke-event reset-deassert-pre
-	}
-	foreach t $targets {
-		# Again, de-assert code needs to know if we 'halt'
-		if {[jtag tapisenabled [$t cget -chain-position]]} {
-			$t arp_reset deassert $halt
-		}
-	}
-	foreach t $targets {
-		$t invoke-event reset-deassert-post
-	}
-
-	# Pass 1 - Now wait for any halt (requested as part of reset
-	# assert/deassert) to happen.  Ideally it takes effect without
-	# first executing any instructions.
-	if { $halt } {
-		foreach t $targets {
-			if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
-				continue
-			}
-
-			# Wait upto 1 second for target to halt.  Why 1sec? Cause
-			# the JTAG tap reset signal might be hooked to a slow
-			# resistor/capacitor circuit - and it might take a while
-			# to charge
-
-			# Catch, but ignore any errors.
-			catch { $t arp_waitstate halted 1000 }
-
-			# Did we succeed?
-			set s [$t curstate]
-
-			if { 0 != [string compare $s "halted" ] } {
-				return -error [format "TARGET: %s - Not halted" $t]
-			}
-		}
-	}
-
-	#Pass 2 - if needed "init"
-	if { 0 == [string compare init $MODE] } {
-		foreach t $targets {
-			if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
-				continue
-			}
-
-			set err [catch "$t arp_waitstate halted 5000"]
-			# Did it halt?
-			if { $err == 0 } {
-				$t invoke-event reset-init
-			}
-		}
-	}
-
-	foreach t $targets {
-		$t invoke-event reset-end
-	}
-}
-
-#########
-
-# REVISIT power_restore, power_dropout, srst_deasserted, srst_asserted
-# are currently neither documented nor supported except on ZY1000.
-
-proc power_restore {} {
-	puts "Sensed power restore."
-	reset init
-}
-
-add_help_text power_restore "Overridable procedure run when power restore is detected. Runs 'reset init' by default."
-
-proc power_dropout {} {
-	puts "Sensed power dropout."
-}
-
-proc srst_deasserted {} {
-	puts "Sensed nSRST deasserted."
-	reset init
-}
-add_help_text srst_deasserted "Overridable procedure run when srst deassert is detected. Runs 'reset init' by default."
-
-proc srst_asserted {} {
-	puts "Sensed nSRST asserted."
-}
-
 #########
 
 # catch any exceptions, capture output and return output
@@ -343,13 +124,3 @@ proc capture_catch {a} {
 	} result
 	return $result
 }
-
-
-# Executed during "init". Can be overridden
-# by board/target/... scripts
-proc jtag_init {} {
-	if {[catch {jtag arp_init} err]!=0} {
-		# try resetting additionally
-		init_reset startup
-	}
-}
diff --git a/src/jtag/Makefile.am b/src/jtag/Makefile.am
index ba722c6..85d98c0 100644
--- a/src/jtag/Makefile.am
+++ b/src/jtag/Makefile.am
@@ -94,4 +94,6 @@ noinst_HEADERS = \
 	rlink/st7.h \
 	minidummy/jtag_minidriver.h
 
+EXTRA_DIST = startup.tcl
+
 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
new file mode 100644
index 0000000..999f5d0
--- /dev/null
+++ b/src/jtag/startup.tcl
@@ -0,0 +1,41 @@
+# Defines basic Tcl procs for OpenOCD JTAG module
+
+# Executed during "init". Can be overridden
+# by board/target/... scripts
+proc jtag_init {} {
+	if {[catch {jtag arp_init} err]!=0} {
+		# try resetting additionally
+		init_reset startup
+	}
+}
+
+#########
+
+# TODO: power_restore and power_dropout are currently neither
+# documented nor supported except on ZY1000.
+
+proc power_restore {} {
+	puts "Sensed power restore."
+	reset init
+}
+
+add_help_text power_restore "Overridable procedure run when power restore is detected. Runs 'reset init' by default."
+
+proc power_dropout {} {
+	puts "Sensed power dropout."
+}
+
+#########
+
+# TODO: srst_deasserted and srst_asserted are currently neither
+# documented nor supported except on ZY1000.
+
+proc srst_deasserted {} {
+	puts "Sensed nSRST deasserted."
+	reset init
+}
+add_help_text srst_deasserted "Overridable procedure run when srst deassert is detected. Runs 'reset init' by default."
+
+proc srst_asserted {} {
+	puts "Sensed nSRST asserted."
+}
diff --git a/src/server/Makefile.am b/src/server/Makefile.am
index 6e52fdf..bb7d5ef 100644
--- a/src/server/Makefile.am
+++ b/src/server/Makefile.am
@@ -35,6 +35,7 @@ nobase_dist_pkgdata_DATA = \
 endif
 
 EXTRA_DIST = \
+	startup.tcl \
 	httpd/readme.txt \
 	httpd/menu.xml \
 	httpd/menu.xsl \
diff --git a/src/server/startup.tcl b/src/server/startup.tcl
new file mode 100644
index 0000000..677bb2d
--- /dev/null
+++ b/src/server/startup.tcl
@@ -0,0 +1,8 @@
+# Handle GDB 'R' packet. Can be overriden by configuration script,
+# but it's not something one would expect target scripts to do
+# normally
+proc ocd_gdb_restart {target_id} {
+	# Fix!!! we're resetting all targets here! Really we should reset only
+	# one target
+	reset halt
+}
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 9dd0bdc..23aea82 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -13,7 +13,9 @@ AM_CPPFLAGS = \
 BIN2C		= $(top_builddir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
 
 DEBUG_HANDLER	= $(srcdir)/xscale/debug_handler.bin
-EXTRA_DIST = $(DEBUG_HANDLER)
+EXTRA_DIST = \
+	startup.tcl \
+	$(DEBUG_HANDLER)
 
 DEBUG_HEADER	= xscale_debug.h
 BUILT_SOURCES = $(DEBUG_HEADER)
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
new file mode 100644
index 0000000..d480f33
--- /dev/null
+++ b/src/target/startup.tcl
@@ -0,0 +1,165 @@
+#########
+
+# This reset logic may be overridden by board/target/... scripts as needed
+# to provide a reset that, if possible, is close to a power-up reset.
+#
+# Exit requirements include:  (a) JTAG must be working, (b) the scan
+# chain was validated with "jtag arp_init" (or equivalent), (c) nothing
+# stays in reset.  No TAP-specific scans were performed.  It's OK if
+# some targets haven't been reset yet; they may need TAP-specific scans.
+#
+# The "mode" values include:  halt, init, run (from "reset" command);
+# startup (at OpenOCD server startup, when JTAG may not yet work); and
+# potentially more (for reset types like cold, warm, etc)
+proc init_reset { mode } {
+	jtag arp_init-reset
+}
+
+
+global in_process_reset
+set in_process_reset 0
+
+# Catch reset recursion
+proc ocd_process_reset { MODE } {
+	global in_process_reset
+	if {$in_process_reset} {
+		set in_process_reset 0
+		return -code error "'reset' can not be invoked recursively"
+	}
+
+	set in_process_reset 1
+	set success [expr [catch {ocd_process_reset_inner $MODE} result]==0]
+	set in_process_reset 0
+
+	if {$success} {
+		return $result
+	} else {
+		return -code error $result
+	}
+}
+
+proc ocd_process_reset_inner { MODE } {
+	set targets [target names]
+
+	# If this target must be halted...
+	set halt -1
+	if { 0 == [string compare $MODE halt] } {
+		set halt 1
+	}
+	if { 0 == [string compare $MODE init] } {
+		set halt 1;
+	}
+	if { 0 == [string compare $MODE run ] } {
+		set halt 0;
+	}
+	if { $halt < 0 } {
+		return -error "Invalid mode: $MODE, must be one of: halt, init, or run";
+	}
+
+	# Target event handlers *might* change which TAPs are enabled
+	# or disabled, so we fire all of them.  But don't issue any
+	# target "arp_*" commands, which may issue JTAG transactions,
+	# unless we know the underlying TAP is active.
+	#
+	# NOTE:  ARP == "Advanced Reset Process" ... "advanced" is
+	# relative to a previous restrictive scheme
+
+	foreach t $targets {
+		# New event script.
+		$t invoke-event reset-start
+	}
+
+	# Use TRST or TMS/TCK operations to reset all the tap controllers.
+	# TAP reset events get reported; they might enable some taps.
+	init_reset $MODE
+
+	# Examine all targets on enabled taps.
+	foreach t $targets {
+		if {[jtag tapisenabled [$t cget -chain-position]]} {
+			$t arp_examine
+		}
+	}
+
+	# Assert SRST, and report the pre/post events.
+	# Note:  no target sees SRST before "pre" or after "post".
+	foreach t $targets {
+		$t invoke-event reset-assert-pre
+	}
+	foreach t $targets {
+		# C code needs to know if we expect to 'halt'
+		if {[jtag tapisenabled [$t cget -chain-position]]} {
+			$t arp_reset assert $halt
+		}
+	}
+	foreach t $targets {
+		$t invoke-event reset-assert-post
+	}
+
+	# Now de-assert SRST, and report the pre/post events.
+	# Note:  no target sees !SRST before "pre" or after "post".
+	foreach t $targets {
+		$t invoke-event reset-deassert-pre
+	}
+	foreach t $targets {
+		# Again, de-assert code needs to know if we 'halt'
+		if {[jtag tapisenabled [$t cget -chain-position]]} {
+			$t arp_reset deassert $halt
+		}
+	}
+	foreach t $targets {
+		$t invoke-event reset-deassert-post
+	}
+
+	# Pass 1 - Now wait for any halt (requested as part of reset
+	# assert/deassert) to happen.  Ideally it takes effect without
+	# first executing any instructions.
+	if { $halt } {
+		foreach t $targets {
+			if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
+				continue
+			}
+
+			# Wait upto 1 second for target to halt.  Why 1sec? Cause
+			# the JTAG tap reset signal might be hooked to a slow
+			# resistor/capacitor circuit - and it might take a while
+			# to charge
+
+			# Catch, but ignore any errors.
+			catch { $t arp_waitstate halted 1000 }
+
+			# Did we succeed?
+			set s [$t curstate]
+
+			if { 0 != [string compare $s "halted" ] } {
+				return -error [format "TARGET: %s - Not halted" $t]
+			}
+		}
+	}
+
+	#Pass 2 - if needed "init"
+	if { 0 == [string compare init $MODE] } {
+		foreach t $targets {
+			if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
+				continue
+			}
+
+			set err [catch "$t arp_waitstate halted 5000"]
+			# Did it halt?
+			if { $err == 0 } {
+				$t invoke-event reset-init
+			}
+		}
+	}
+
+	foreach t $targets {
+		$t invoke-event reset-end
+	}
+}
+
+#########
+
+# Temporary migration aid.  May be removed starting in January 2011.
+proc armv4_5 params {
+	echo "DEPRECATED! use 'arm $params' not 'armv4_5 $params'"
+	arm $params
+}

commit 903daa796a226152fe56245758c8388b79d12988
Author: Zachary T Welch <zw...@su...>
Date:   Tue Nov 17 08:30:51 2009 -0800

    move startup.c to libopenocd
    
    Moves the creation of startup_tcl.c from src/helper/ to src/.
    Prepares to split the startup.tcl file into its per-module parts.

diff --git a/.gitignore b/.gitignore
index f8a5381..114fc05 100644
--- a/.gitignore
+++ b/.gitignore
@@ -13,6 +13,7 @@
 # editor files
 *.swp
 
+src/startup.tcl
 startup_tcl.c
 xscale_debug.h
 
diff --git a/src/Makefile.am b/src/Makefile.am
index 77ae5ae..2f17ba4 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -14,7 +14,8 @@ openocd_LDADD = libopenocd.la
 
 libopenocd_la_SOURCES = \
 	hello.c \
-	openocd.c
+	openocd.c \
+	startup_tcl.c
 
 noinst_HEADERS = \
 	openocd.h
@@ -97,6 +98,26 @@ if HTTPD
 libopenocd_la_LIBADD += -lmicrohttpd
 endif
 
+STARTUP_TCL_SRCS = \
+	$(srcdir)/helper/startup.tcl
+
+EXTRA_DIST = $(STARTUP_TCL_SRCS)
+
+BUILT_SOURCES = startup.tcl
+
+startup.tcl: $(STARTUP_TCL_SRCS)
+	cat $^ > $@
+
+BIN2C = $(builddir)/helper/bin2char$(EXEEXT_FOR_BUILD)
+
+# Convert .tcl to cfile
+startup_tcl.c: startup.tcl $(BIN2C)
+	$(BIN2C) startup_tcl < $< > $@ || rm -f $@
+
+# add startup_tcl.c to make clean list
+CLEANFILES = startup.tcl startup_tcl.c
+
+
 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
 
 # The "quick" target builds executables & reinstalls the executables
diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am
index 67250a1..9557f5b 100644
--- a/src/helper/Makefile.am
+++ b/src/helper/Makefile.am
@@ -23,8 +23,7 @@ libhelper_la_SOURCES = \
 	time_support.c \
 	replacements.c \
 	fileio.c \
-	membuf.c \
-	startup_tcl.c
+	membuf.c
 
 if IOUTIL
 libhelper_la_SOURCES += ioutil.c
@@ -49,7 +48,6 @@ noinst_HEADERS = \
 	jim.h \
 	jim-eventloop.h \
 	system.h \
-	startup.tcl \
 	bin2char.c
 
 BIN2C = bin2char$(EXEEXT_FOR_BUILD)
@@ -59,11 +57,6 @@ BUILT_SOURCES = $(BIN2C)
 $(BIN2C): bin2char.c
 	${CC_FOR_BUILD} ${CFLAGS_FOR_BUILD} $(srcdir)/bin2char.c -o $@
 
-# Convert .tcl to cfile
-startup_tcl.c: startup.tcl $(BIN2C)
-	./$(BIN2C) startup_tcl < $(srcdir)/startup.tcl > $@
-
-# add startup_tcl.c to make clean list
-CLEANFILES = startup_tcl.c bin2char$(EXEEXT_FOR_BUILD)
+CLEANFILES = bin2char$(EXEEXT_FOR_BUILD)
 
 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in

-----------------------------------------------------------------------

Summary of changes:
 .gitignore             |    1 +
 src/Makefile.am        |   27 ++++++-
 src/flash/Makefile.am  |    2 +
 src/flash/startup.tcl  |   16 ++++
 src/helper/Makefile.am |   13 +--
 src/helper/command.c   |    3 +-
 src/helper/command.h   |    5 +-
 src/helper/startup.tcl |  231 +-----------------------------------------------
 src/jtag/Makefile.am   |    2 +
 src/jtag/startup.tcl   |   41 +++++++++
 src/openocd.c          |    3 +-
 src/openocd.h          |    3 +
 src/server/Makefile.am |    1 +
 src/server/startup.tcl |    8 ++
 src/target/Makefile.am |    4 +-
 src/target/startup.tcl |  165 ++++++++++++++++++++++++++++++++++
 16 files changed, 280 insertions(+), 245 deletions(-)
 create mode 100644 src/flash/startup.tcl
 create mode 100644 src/jtag/startup.tcl
 create mode 100644 src/server/startup.tcl
 create mode 100644 src/target/startup.tcl


hooks/post-receive
-- 
Main OpenOCD repository

Flat | Threaded

<< < 1 .. 214 215 216 217 218 .. 289 > >> (Page 216 of 289)