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From: Øyvind H. <go...@us...> - 2010-06-09 17:13:54
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9ab7636ce6276d222662be431a1e6be96d9d34c0 (commit)
from 49e6c61bcc9a176119721c38004eca02b3e77f19 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9ab7636ce6276d222662be431a1e6be96d9d34c0
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Jun 9 17:12:52 2010 +0200
flash: add error message if image is too big for flash
replaced assert() w/error message if the image is
too big.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 1bd09b4..429bad6 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -636,7 +636,11 @@ int flash_write_unlock(struct target *target, struct image *image,
LOG_INFO("Padding image section %d with %d bytes", section_last-1, pad_bytes);
}
- assert (run_address + run_size - 1 <= c->base + c->size - 1);
+ if (run_address + run_size - 1 > c->base + c->size - 1)
+ {
+ LOG_ERROR("The image is too big for the flash");
+ return ERROR_FAIL;
+ }
/* If we're applying any sector automagic, then pad this
* (maybe-combined) segment to the end of its last sector.
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/core.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-06-09 16:02:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 49e6c61bcc9a176119721c38004eca02b3e77f19 (commit)
via c63468038473420bf4f25d2b93e3ce7620d0b572 (commit)
from f6236ade0e0b62129b4a16f0d7897f79756189f0 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 49e6c61bcc9a176119721c38004eca02b3e77f19
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Jun 9 16:01:10 2010 +0200
flash: flash erase_address takes unsigned arguments
fixed bug where address was parsed as a signed, rather
than unsigned it.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index b3dbd7b..cf1ca4a 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -199,8 +199,8 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
{
struct flash_bank *p;
int retval = ERROR_OK;
- int address;
- int length;
+ uint32_t address;
+ uint32_t length;
bool do_pad = false;
bool do_unlock = false;
struct target *target = get_current_target(CMD_CTX);
@@ -229,8 +229,8 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
return ERROR_COMMAND_SYNTAX_ERROR;
}
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], length);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
if (length <= 0)
{
commit c63468038473420bf4f25d2b93e3ce7620d0b572
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jun 7 16:14:51 2010 +0200
zy1000: fix optimisation gaffe
DCC optimisation was broken on targets w/multiple TAP's.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index f578058..13685f8 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -820,14 +820,35 @@ static void jtag_pre_post_bits(struct jtag_tap *tap, int *pre, int *post)
*post = post_bits;
}
+/*
+ static const int embeddedice_num_bits[] = {32, 6};
+ uint32_t values[2];
+
+ values[0] = value;
+ values[1] = (1 << 5) | reg_addr;
+
+ jtag_add_dr_out(tap,
+ 2,
+ embeddedice_num_bits,
+ values,
+ TAP_IDLE);
+*/
+
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count)
{
-
+#if 0
+ int i;
+ for (i = 0; i < count; i++)
+ {
+ embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+#else
int pre_bits;
int post_bits;
jtag_pre_post_bits(tap, &pre_bits, &post_bits);
- if (pre_bits + post_bits + 6 > 32)
+ if ((pre_bits > 32) || (post_bits + 6 > 32))
{
int i;
for (i = 0; i < count; i++)
@@ -837,18 +858,20 @@ void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer,
}
} else
{
- shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
int i;
- for (i = 0; i < count - 1; i++)
+ for (i = 0; i < count; i++)
{
/* Fewer pokes means we get to use the FIFO more efficiently */
+ shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
- shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits + pre_bits, (reg_addr | (1 << 5)));
+ /* Danger! here we need to exit into the TAP_IDLE state to make
+ * DCC pick up this value.
+ */
+ shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits, (reg_addr | (1 << 5)));
buffer += 4;
}
- shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
- shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits, (reg_addr | (1 << 5)));
}
+#endif
}
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/tcl.c | 8 ++++----
src/jtag/zy1000/zy1000.c | 37 ++++++++++++++++++++++++++++++-------
2 files changed, 34 insertions(+), 11 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-06-08 10:49:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 14c112e992c405442a751342bb6bca4adb0ae90a (commit)
from 31bbb3cf0c9cffb98dbda1a357356bbf519a456f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 14c112e992c405442a751342bb6bca4adb0ae90a
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed May 5 16:18:50 2010 +0200
cfi: fix GDB keep alive bug
Long running CFI writes could cause GDB timeout.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 8c1aaca..f0ab332 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1232,6 +1232,8 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
buffer += thisrun_count;
address += thisrun_count;
count -= thisrun_count;
+
+ keep_alive();
}
/* free up resources */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/cfi.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-06-08 10:47:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 31bbb3cf0c9cffb98dbda1a357356bbf519a456f (commit)
from 54f3f8e4c1477bec077e132cdccd8097938332e2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 31bbb3cf0c9cffb98dbda1a357356bbf519a456f
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed May 5 19:00:21 2010 +0200
verify: display up to 128 diff's
Showing up to 128 differences.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/target.c b/src/target/target.c
index c8c1012..01d9441 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2682,6 +2682,7 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify)
}
image_size = 0x0;
+ int diffs = 0;
retval = ERROR_OK;
for (i = 0; i < image.num_sections; i++)
{
@@ -2716,7 +2717,10 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify)
/* failed crc checksum, fall back to a binary compare */
uint8_t *data;
- command_print(CMD_CTX, "checksum mismatch - attempting binary compare");
+ if (diffs == 0)
+ {
+ LOG_ERROR("checksum mismatch - attempting binary compare");
+ }
data = (uint8_t*)malloc(buf_cnt);
@@ -2737,22 +2741,22 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify)
if (data[t] != buffer[t])
{
command_print(CMD_CTX,
- "Verify operation failed address 0x%08x. Was 0x%02x instead of 0x%02x\n",
+ "diff %d address 0x%08x. Was 0x%02x instead of 0x%02x",
+ diffs,
(unsigned)(t + image.sections[i].base_address),
data[t],
buffer[t]);
- free(data);
- free(buffer);
- retval = ERROR_FAIL;
- goto done;
- }
- if ((t%16384) == 0)
- {
- keep_alive();
+ if (diffs++ >= 127)
+ {
+ command_print(CMD_CTX, "More than 128 errors, the rest are not printed.");
+ free(data);
+ free(buffer);
+ goto done;
+ }
}
+ keep_alive();
}
}
-
free(data);
}
} else
@@ -2766,6 +2770,10 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify)
image_size += buf_cnt;
}
done:
+ if (diffs > 0)
+ {
+ retval = ERROR_FAIL;
+ }
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX, "verified %" PRIu32 " bytes "
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 30 +++++++++++++++++++-----------
1 files changed, 19 insertions(+), 11 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-06-08 10:38:29
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 54f3f8e4c1477bec077e132cdccd8097938332e2 (commit)
from 00635e28ba5c405742cae261d8551f165dc78ba3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 54f3f8e4c1477bec077e132cdccd8097938332e2
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jun 7 15:14:04 2010 +0200
gdb-server: fix error reporting bugs
GDB and OpenOCD has two different error number
spaces and no mapping exists between them.
If a specific error number is to be reported
to GDB then this has to be done at the calling
site, rather than as a generic routine that
tries to map "retval" to GDB error number speak.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index a84c618..029bdf8 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1219,29 +1219,14 @@ static int gdb_set_register_packet(struct connection *connection,
return ERROR_OK;
}
+/* No attempt is made to translate the "retval" to
+ * GDB speak. This has to be done at the calling
+ * site as no mapping really exists.
+ */
static int gdb_error(struct connection *connection, int retval)
{
- switch (retval)
- {
- case ERROR_TARGET_DATA_ABORT:
- gdb_send_error(connection, EIO);
- break;
- case ERROR_TARGET_TRANSLATION_FAULT:
- gdb_send_error(connection, EFAULT);
- break;
- case ERROR_TARGET_UNALIGNED_ACCESS:
- gdb_send_error(connection, EFAULT);
- break;
- case ERROR_TARGET_NOT_HALTED:
- gdb_send_error(connection, EFAULT);
- break;
- default:
- /* This could be that the target reset itself. */
- LOG_ERROR("unexpected error %i", retval);
- gdb_send_error(connection, EFAULT);
- break;
- }
-
+ LOG_DEBUG("Reporting %i to GDB as generic error", retval);
+ gdb_send_error(connection, EFAULT);
return ERROR_OK;
}
@@ -1719,7 +1704,7 @@ static int gdb_memory_map(struct connection *connection,
if (retval != ERROR_OK)
{
free(banks);
- gdb_send_error(connection, retval);
+ gdb_error(connection, retval);
return retval;
}
banks[i] = p;
@@ -1801,7 +1786,7 @@ static int gdb_memory_map(struct connection *connection,
xml_printf(&retval, &xml, &pos, &size, "</memory-map>\n");
if (retval != ERROR_OK) {
- gdb_send_error(connection, retval);
+ gdb_error(connection, retval);
return retval;
}
@@ -1952,7 +1937,7 @@ static int gdb_query_packet(struct connection *connection,
if (retval != ERROR_OK)
{
- gdb_send_error(connection, retval);
+ gdb_error(connection, retval);
return retval;
}
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 33 +++++++++------------------------
1 files changed, 9 insertions(+), 24 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-06-07 15:10:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 00635e28ba5c405742cae261d8551f165dc78ba3 (commit)
from a1cf1b52444c67b6c56ad58fe29be5a285b244cb (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 00635e28ba5c405742cae261d8551f165dc78ba3
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sat Jun 5 11:30:49 2010 +0200
jtag: rename JTAG_MOVESTATE to JTAG_TLR_RESET
JTAG_MOVESTATE is misleading, this cmd is only used
for reset.
JTAG_PATHMOVE should be used otherwise.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/jtag/commands.h b/src/jtag/commands.h
index 87bd9c5..d591814 100644
--- a/src/jtag/commands.h
+++ b/src/jtag/commands.h
@@ -139,7 +139,14 @@ union jtag_command_container {
*/
enum jtag_command_type {
JTAG_SCAN = 1,
- JTAG_STATEMOVE = 2,
+ /* JTAG_TLR_RESET's non-minidriver implementation is a
+ * vestige from a statemove cmd. The statemove command
+ * is obsolete and replaced by pathmove.
+ *
+ * pathmove does not support reset as one of it's states,
+ * hence the need for an explicit statemove command.
+ */
+ JTAG_TLR_RESET = 2,
JTAG_RUNTEST = 3,
JTAG_RESET = 4,
JTAG_PATHMOVE = 6,
diff --git a/src/jtag/drivers/amt_jtagaccel.c b/src/jtag/drivers/amt_jtagaccel.c
index 121649b..fca8cfe 100644
--- a/src/jtag/drivers/amt_jtagaccel.c
+++ b/src/jtag/drivers/amt_jtagaccel.c
@@ -356,7 +356,7 @@ static int amt_jtagaccel_execute_queue(void)
amt_jtagaccel_end_state(cmd->cmd.runtest->end_state);
amt_jtagaccel_runtest(cmd->cmd.runtest->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
#endif
diff --git a/src/jtag/drivers/arm-jtag-ew.c b/src/jtag/drivers/arm-jtag-ew.c
index e54c8c6..9d8b8b1 100644
--- a/src/jtag/drivers/arm-jtag-ew.c
+++ b/src/jtag/drivers/arm-jtag-ew.c
@@ -117,7 +117,7 @@ static int armjtagew_execute_queue(void)
armjtagew_runtest(cmd->cmd.runtest->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
armjtagew_end_state(cmd->cmd.statemove->end_state);
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index 6159ef7..4548cb5 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -304,7 +304,7 @@ int bitbang_execute_queue(void)
bitbang_stableclocks(cmd->cmd.stableclocks->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("statemove end in %s", tap_state_name(cmd->cmd.statemove->end_state));
#endif
diff --git a/src/jtag/drivers/bitq.c b/src/jtag/drivers/bitq.c
index 79ca349..a58f633 100644
--- a/src/jtag/drivers/bitq.c
+++ b/src/jtag/drivers/bitq.c
@@ -323,7 +323,7 @@ int bitq_execute_queue(void)
bitq_runtest(cmd->cmd.runtest->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
#endif
diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c
index 99210d2..1c433a9 100644
--- a/src/jtag/drivers/buspirate.c
+++ b/src/jtag/drivers/buspirate.c
@@ -146,7 +146,7 @@ static int buspirate_execute_queue(void)
buspirate_runtest(cmd->cmd.runtest
->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
DEBUG_JTAG_IO("statemove end in %s",
tap_state_name(cmd->cmd.statemove
->end_state));
diff --git a/src/jtag/drivers/driver.c b/src/jtag/drivers/driver.c
index 7f7f879..49f4024 100644
--- a/src/jtag/drivers/driver.c
+++ b/src/jtag/drivers/driver.c
@@ -338,7 +338,7 @@ int interface_jtag_add_tlr(void)
jtag_queue_command(cmd);
- cmd->type = JTAG_STATEMOVE;
+ cmd->type = JTAG_TLR_RESET;
cmd->cmd.statemove = cmd_queue_alloc(sizeof(struct statemove_command));
cmd->cmd.statemove->end_state = state;
diff --git a/src/jtag/drivers/ft2232.c b/src/jtag/drivers/ft2232.c
index 93d1c4a..2ac410a 100644
--- a/src/jtag/drivers/ft2232.c
+++ b/src/jtag/drivers/ft2232.c
@@ -1978,7 +1978,7 @@ static int ft2232_execute_command(struct jtag_command *cmd)
{
case JTAG_RESET: retval = ft2232_execute_reset(cmd); break;
case JTAG_RUNTEST: retval = ft2232_execute_runtest(cmd); break;
- case JTAG_STATEMOVE: retval = ft2232_execute_statemove(cmd); break;
+ case JTAG_TLR_RESET: retval = ft2232_execute_statemove(cmd); break;
case JTAG_PATHMOVE: retval = ft2232_execute_pathmove(cmd); break;
case JTAG_SCAN: retval = ft2232_execute_scan(cmd); break;
case JTAG_SLEEP: retval = ft2232_execute_sleep(cmd); break;
diff --git a/src/jtag/drivers/gw16012.c b/src/jtag/drivers/gw16012.c
index 0e9f3fe..cb29d33 100644
--- a/src/jtag/drivers/gw16012.c
+++ b/src/jtag/drivers/gw16012.c
@@ -344,7 +344,7 @@ static int gw16012_execute_queue(void)
gw16012_end_state(cmd->cmd.runtest->end_state);
gw16012_runtest(cmd->cmd.runtest->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
#endif
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 21dfab2..34fce38 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -202,7 +202,7 @@ static void jlink_execute_command(struct jtag_command *cmd)
switch (cmd->type)
{
case JTAG_RUNTEST: jlink_execute_runtest(cmd); break;
- case JTAG_STATEMOVE: jlink_execute_statemove(cmd); break;
+ case JTAG_TLR_RESET: jlink_execute_statemove(cmd); break;
case JTAG_PATHMOVE: jlink_execute_pathmove(cmd); break;
case JTAG_SCAN: jlink_execute_scan(cmd); break;
case JTAG_RESET: jlink_execute_reset(cmd); break;
diff --git a/src/jtag/drivers/rlink.c b/src/jtag/drivers/rlink.c
index 43f1940..0060baf 100644
--- a/src/jtag/drivers/rlink.c
+++ b/src/jtag/drivers/rlink.c
@@ -1398,7 +1398,7 @@ int rlink_execute_queue(void)
switch (cmd->type)
{
case JTAG_RUNTEST:
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
case JTAG_PATHMOVE:
case JTAG_SCAN:
break;
@@ -1430,7 +1430,7 @@ int rlink_execute_queue(void)
rlink_end_state(cmd->cmd.runtest->end_state);
rlink_runtest(cmd->cmd.runtest->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
#endif
diff --git a/src/jtag/drivers/usbprog.c b/src/jtag/drivers/usbprog.c
index 0d51b27..cc78555 100644
--- a/src/jtag/drivers/usbprog.c
+++ b/src/jtag/drivers/usbprog.c
@@ -131,7 +131,7 @@ static int usbprog_execute_queue(void)
usbprog_end_state(cmd->cmd.runtest->end_state);
usbprog_runtest(cmd->cmd.runtest->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
#endif
diff --git a/src/jtag/drivers/vsllink.c b/src/jtag/drivers/vsllink.c
index a985677..450ce06 100644
--- a/src/jtag/drivers/vsllink.c
+++ b/src/jtag/drivers/vsllink.c
@@ -165,7 +165,7 @@ static int vsllink_execute_queue(void)
vsllink_runtest(cmd->cmd.runtest->num_cycles);
break;
- case JTAG_STATEMOVE:
+ case JTAG_TLR_RESET:
DEBUG_JTAG_IO("statemove end in %s",
tap_state_name(cmd->cmd.statemove
->end_state));
-----------------------------------------------------------------------
Summary of changes:
src/jtag/commands.h | 9 ++++++++-
src/jtag/drivers/amt_jtagaccel.c | 2 +-
src/jtag/drivers/arm-jtag-ew.c | 2 +-
src/jtag/drivers/bitbang.c | 2 +-
src/jtag/drivers/bitq.c | 2 +-
src/jtag/drivers/buspirate.c | 2 +-
src/jtag/drivers/driver.c | 2 +-
src/jtag/drivers/ft2232.c | 2 +-
src/jtag/drivers/gw16012.c | 2 +-
src/jtag/drivers/jlink.c | 2 +-
src/jtag/drivers/rlink.c | 4 ++--
src/jtag/drivers/usbprog.c | 2 +-
src/jtag/drivers/vsllink.c | 2 +-
13 files changed, 21 insertions(+), 14 deletions(-)
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From: Øyvind H. <go...@us...> - 2010-06-03 20:42:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a1cf1b52444c67b6c56ad58fe29be5a285b244cb (commit)
from 631514724db1772f9e08e1dcb564fe9205def57e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit a1cf1b52444c67b6c56ad58fe29be5a285b244cb
Author: gcembed <gc...@gm...>
Date: Tue Jun 1 13:48:22 2010 +0200
stm32 : change returned value of mass_erase function
Hello,
"stm32x mass_erase" return ERROR_OK even if something goes wrong.
Here is a summary of changes :
* in stm32x_mass_erase : return ERROR_FLASH_OPERATION_FAILED when error
detected in FLASH_SR register;
* in COMMAND_HANDLER(stm32x_handle_mass_erase_command) : return the
returned value of stm32x_mass_erase().
I don't know if there is reason to always return ERROR_OK ?
Gaëtan
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index 8a3b832..47ed640 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -1196,13 +1196,13 @@ static int stm32x_mass_erase(struct flash_bank *bank)
if (status & FLASH_WRPRTERR)
{
LOG_ERROR("stm32x device protected");
- return ERROR_OK;
+ return ERROR_FLASH_OPERATION_FAILED;
}
if (status & FLASH_PGERR)
{
LOG_ERROR("stm32x device programming failed");
- return ERROR_OK;
+ return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
@@ -1223,7 +1223,8 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
if (ERROR_OK != retval)
return retval;
- if (stm32x_mass_erase(bank) == ERROR_OK)
+ retval = stm32x_mass_erase(bank);
+ if (retval == ERROR_OK)
{
/* set all sectors as erased */
for (i = 0; i < bank->num_sectors; i++)
@@ -1238,7 +1239,7 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
command_print(CMD_CTX, "stm32x mass erase failed");
}
- return ERROR_OK;
+ return retval;
}
static const struct command_registration stm32x_exec_command_handlers[] = {
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32x.c | 9 +++++----
1 files changed, 5 insertions(+), 4 deletions(-)
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From: Spencer O. <nt...@us...> - 2010-06-03 11:41:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 631514724db1772f9e08e1dcb564fe9205def57e (commit)
from d944a0bed73c63fe52cf546a7121823318e8b593 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 631514724db1772f9e08e1dcb564fe9205def57e
Author: Spencer Oliver <nt...@us...>
Date: Thu Jun 3 10:20:06 2010 +0100
NEWS: updates
Add new features since 0.4.0 release.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/NEWS b/NEWS
index a744da3..db4485d 100644
--- a/NEWS
+++ b/NEWS
@@ -13,10 +13,14 @@ JTAG Layer:
jtag_khz ... is now adapter_khz
jtag_nsrst_delay ... is now adapter_nsrst_delay
jtag_nsrst_assert_width ... is now adapter_nsrst_assert_width
+ Support Voipac VPACLink JTAG Adapter.
Boundary Scan:
Target Layer:
+ ARM:
+ - basic semihosting support (ARMv7M).
+ - renamed "armv7m" command prefix as "arm"
MIPS:
- "ejtag_srst" variant removed. The same functionality is
obtained by using "reset_config none".
@@ -31,9 +35,17 @@ Flash Layer:
re-enabling hardware debugging).
PIC32MX now uses algorithm for flash programming, this
has increased the performance by approx 96%.
+ New 'pic32mx unlock' cmd to remove readout protection.
+ New STM32 Value Line Support.
+ New 'virtual' flash driver, used to associate other addresses
+ with a flash bank. See pic32mx.cfg for usage.
+ New iMX27 NAND flash controller driver.
Board, Target, and Interface Configuration Scripts:
Support IAR LPC1768 kickstart board (by Olimex)
+ Support Voipac PXA270/PXA270M module.
+ New $PARPORTADDR tcl variable used to change default
+ parallel port address used.
Core Jim/TCL Scripting:
New "add_script_search_dir" command, behaviour is the same
-----------------------------------------------------------------------
Summary of changes:
NEWS | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: Øyvind H. <go...@us...> - 2010-05-31 07:15:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d944a0bed73c63fe52cf546a7121823318e8b593 (commit)
from 86e851e1e263c79f19eb9db52553de99f19b8bb9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d944a0bed73c63fe52cf546a7121823318e8b593
Author: Jon Povey <jon...@ra...>
Date: Mon May 31 11:56:42 2010 +0900
etm: print something when trace buffer empty
ETM analyze produced no output when the trace buffer was empty.
This patch provides users with a clue.
Signed-off-by: Jon Povey <jon...@ra...>
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/etm.c b/src/target/etm.c
index 4f4bf9a..61ee99a 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -882,6 +882,11 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
if (ctx->trace_depth == 0)
ctx->capture_driver->read_trace(ctx);
+ if (ctx->trace_depth == 0) {
+ command_print(cmd_ctx, "Trace is empty.");
+ return ERROR_OK;
+ }
+
/* start at the beginning of the captured trace */
ctx->pipe_index = 0;
ctx->data_index = 0;
-----------------------------------------------------------------------
Summary of changes:
src/target/etm.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
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--
Main OpenOCD repository
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From: Spencer O. <nt...@us...> - 2010-05-29 16:45:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 86e851e1e263c79f19eb9db52553de99f19b8bb9 (commit)
from 215353ef67434e41b13f8948dc7dceefc110e3fe (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 86e851e1e263c79f19eb9db52553de99f19b8bb9
Author: Spencer Oliver <nt...@us...>
Date: Sat May 29 15:43:42 2010 +0100
nor: fix memory leaks during probe
Fix similar memory leaks as per commit:
ef72484b785ec7462a0415afea679d08b864c7fb
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 7cdab51..8472d83 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -324,6 +324,12 @@ static int avrf_probe(struct flash_bank *bank)
if (avr_info != NULL)
{
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
// chip found
bank->base = 0x00000000;
bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 58009ae..2fe864d 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -560,6 +560,12 @@ static int pic32mx_probe(struct flash_bank *bank)
LOG_INFO("flash size = %" PRId32 "kbytes", num_pages / 1024);
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
/* calculate numbers of pages */
num_pages /= page_size;
bank->size = (num_pages * page_size);
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 38374ff..f7e2e8d 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -1065,6 +1065,12 @@ static int stellaris_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
/* provide this for the benefit of the NOR flash framework */
bank->size = 1024 * stellaris_info->num_pages;
bank->num_sectors = stellaris_info->num_pages;
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index d11a8ed..8a3b832 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -775,6 +775,12 @@ static int stm32x_probe(struct flash_bank *bank)
/* calculate numbers of pages */
num_pages /= (page_size / 1024);
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
bank->base = 0x08000000;
bank->size = (num_pages * page_size);
bank->num_sectors = num_pages;
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index c1681f1..343c43e 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -139,6 +139,12 @@ static int tms470_read_part_info(struct flash_bank *bank)
rom_flash = (device_ident_reg >> 10) & 1;
part_number = (device_ident_reg >> 3) & 0x7f;
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
/*
* If the part number is known, determine if the flash bank is valid
* based on the base address being within the known flash bank
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/avrf.c | 6 ++++++
src/flash/nor/pic32mx.c | 6 ++++++
src/flash/nor/stellaris.c | 6 ++++++
src/flash/nor/stm32x.c | 6 ++++++
src/flash/nor/tms470.c | 6 ++++++
5 files changed, 30 insertions(+), 0 deletions(-)
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From: Spencer O. <nt...@us...> - 2010-05-27 22:32:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 215353ef67434e41b13f8948dc7dceefc110e3fe (commit)
via ee4106ee995a1fc81778f4ebd496d6782e592b63 (commit)
via 94dc7c0a939c042c71767b5cbdc1e1327ccecbea (commit)
via 5319ccd7eb4761f1481dcbb041b256848efc005e (commit)
from ef72484b785ec7462a0415afea679d08b864c7fb (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 215353ef67434e41b13f8948dc7dceefc110e3fe
Author: Spencer Oliver <nt...@us...>
Date: Mon May 24 12:32:58 2010 +0100
flash: virtual driver update for get_flash_bank_by_name_noprobe
Make sure we do not probe a flash when getting info.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/flash/nor/virtual.c b/src/flash/nor/virtual.c
index 4908c0c..eb1885e 100644
--- a/src/flash/nor/virtual.c
+++ b/src/flash/nor/virtual.c
@@ -27,7 +27,7 @@ static struct flash_bank* virtual_get_master_bank(struct flash_bank *bank)
{
struct flash_bank* master_bank;
- master_bank = get_flash_bank_by_name(bank->driver_priv);
+ master_bank = get_flash_bank_by_name_noprobe(bank->driver_priv);
if (master_bank == NULL) {
LOG_ERROR("master flash bank '%s' does not exist", (char*)bank->driver_priv);
}
@@ -61,7 +61,7 @@ FLASH_BANK_COMMAND_HANDLER(virtual_flash_bank_command)
/* get the master flash bank */
const char *bank_name = CMD_ARGV[6];
- struct flash_bank *master_bank = get_flash_bank_by_name(bank_name);
+ struct flash_bank *master_bank = get_flash_bank_by_name_noprobe(bank_name);
if (master_bank == NULL)
{
commit ee4106ee995a1fc81778f4ebd496d6782e592b63
Author: Spencer Oliver <nt...@us...>
Date: Mon May 24 12:30:29 2010 +0100
nor: add get_flash_bank_by_name autoprobe
When a flash cmd is called using the flash name the autoprobe
function is not called. autoprobe is called if flash_command_get_bank
falls through to get_flash_bank_by_num.
This makes both get_flash_bank_by_name and get_flash_bank_by_num
behave the same.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 00f73f2..1bd09b4 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -178,7 +178,7 @@ int flash_get_bank_count(void)
return i;
}
-struct flash_bank *get_flash_bank_by_name(const char *name)
+struct flash_bank *get_flash_bank_by_name_noprobe(const char *name)
{
unsigned requested = get_flash_name_index(name);
unsigned found = 0;
@@ -197,6 +197,26 @@ struct flash_bank *get_flash_bank_by_name(const char *name)
return NULL;
}
+struct flash_bank *get_flash_bank_by_name(const char *name)
+{
+ struct flash_bank *bank;
+ int retval;
+
+ bank = get_flash_bank_by_name_noprobe(name);
+ if (bank != NULL)
+ {
+ retval = bank->driver->auto_probe(bank);
+
+ if (retval != ERROR_OK)
+ {
+ LOG_ERROR("auto_probe failed %d\n", retval);
+ return NULL;
+ }
+ }
+
+ return bank;
+}
+
int get_flash_bank_by_num(int num, struct flash_bank **bank)
{
struct flash_bank *p = get_flash_bank_by_num_noprobe(num);
@@ -660,7 +680,7 @@ int flash_write_unlock(struct target *target, struct image *image,
intptr_t diff = (intptr_t)sections[section] - (intptr_t)image->sections;
int t_section_num = diff / sizeof(struct imageection);
- LOG_DEBUG("image_read_section: section = %d, t_section_num = %d, section_offset = %d, buffer_size = %d, size_read = %d",
+ LOG_DEBUG("image_read_section: section = %d, t_section_num = %d, section_offset = %d, buffer_size = %d, size_read = %d",
(int)section,
(int)t_section_num, (int)section_offset, (int)buffer_size, (int)size_read);
if ((retval = image_read_section(image, t_section_num, section_offset,
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index a35f64f..17f1c53 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -170,7 +170,15 @@ int default_flash_mem_blank_check(struct flash_bank *bank);
*/
struct flash_bank *get_flash_bank_by_name(const char *name);
/**
- * Returns a flash bank by the specified flash_bank_s bank_number, @a num.
+ * Returns the flash bank specified by @a name, which matches the
+ * driver name and a suffix (option) specify the driver-specific
+ * bank number. The suffix consists of the '.' and the driver-specific
+ * bank number: when two str9x banks are defined, then 'str9x.1' refers
+ * to the second.
+ */
+struct flash_bank *get_flash_bank_by_name_noprobe(const char *name);
+/**
+ * Returns the flash bank like get_flash_bank_by_name(), without probing.
* @param num The flash bank number.
* @param bank returned bank if fn returns ERROR_OK
* @returns ERROR_OK if successful
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 80d9a27..b3dbd7b 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -796,7 +796,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
}
/* check the flash bank name is unique */
- if (get_flash_bank_by_name(bank_name) != NULL)
+ if (get_flash_bank_by_name_noprobe(bank_name) != NULL)
{
/* flash bank name already exists */
LOG_ERROR("flash bank name '%s' already exists", bank_name);
commit 94dc7c0a939c042c71767b5cbdc1e1327ccecbea
Author: Spencer Oliver <nt...@us...>
Date: Mon May 24 11:43:09 2010 +0100
cfg: add pic32 virtual banks
make use of the new virtual bank flash driver.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index 0b99cdb..202668b 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -69,8 +69,15 @@ $_TARGETNAME configure -event reset-init {
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
# For more information about the configuration files, take a look at:
# openocd.texi
commit 5319ccd7eb4761f1481dcbb041b256848efc005e
Author: Spencer Oliver <nt...@us...>
Date: Mon May 24 11:41:50 2010 +0100
flash: add virtual flash bank driver
This adds a virtual flash bank driver that allows virtual banks to
be defined that refer to an existing flash bank.
For example the real address for bank0 on the pic32 is 0x1fc00000
but the user program will either be in kseg0 (0xbfc00000) or
kseg1 (0x9fc00000).
This also means that gdb will be aware of all the read only flash
addresses.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index c95803a..a3ca124 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4672,6 +4672,26 @@ the flash clock.
@end deffn
@end deffn
+@deffn {Flash Driver} virtual
+This is a special driver that maps a previously defined bank to another
+address. All bank settings will be copied from the master physical bank.
+
+The @var{virtual} driver defines one mandatory parameters,
+
+@itemize
+@item @var{master_bank} The bank that this virtual address refers to.
+@end itemize
+
+So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
+the flash bank defined at address 0x1fc00000. Any cmds executed on
+the virtual banks are actually performed on the physical banks.
+@example
+flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+@end example
+@end deffn
+
@subsection str9xpec driver
@cindex str9xpec
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 5d0a4df..eec6f50 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -28,7 +28,8 @@ NOR_DRIVERS = \
str7x.c \
str9x.c \
str9xpec.c \
- tms470.c
+ tms470.c \
+ virtual.c
noinst_HEADERS = \
at91sam7.h \
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index 3e09a00..68f2f88 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -39,6 +39,7 @@ extern struct flash_driver ocl_flash;
extern struct flash_driver pic32mx_flash;
extern struct flash_driver avr_flash;
extern struct flash_driver faux_flash;
+extern struct flash_driver virtual_flash;
/**
* The list of built-in flash drivers.
@@ -63,6 +64,7 @@ static struct flash_driver *flash_drivers[] = {
&pic32mx_flash,
&avr_flash,
&faux_flash,
+ &virtual_flash,
NULL,
};
diff --git a/src/flash/nor/virtual.c b/src/flash/nor/virtual.c
new file mode 100644
index 0000000..4908c0c
--- /dev/null
+++ b/src/flash/nor/virtual.c
@@ -0,0 +1,244 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Spencer Oliver *
+ * sp...@sp... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+
+static struct flash_bank* virtual_get_master_bank(struct flash_bank *bank)
+{
+ struct flash_bank* master_bank;
+
+ master_bank = get_flash_bank_by_name(bank->driver_priv);
+ if (master_bank == NULL) {
+ LOG_ERROR("master flash bank '%s' does not exist", (char*)bank->driver_priv);
+ }
+
+ return master_bank;
+}
+
+static void virtual_update_bank_info(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+
+ if (master_bank == NULL) {
+ return;
+ }
+
+ /* update the info we do not have */
+ bank->size = master_bank->size;
+ bank->chip_width = master_bank->chip_width;
+ bank->bus_width = master_bank->bus_width;
+ bank->num_sectors = master_bank->num_sectors;
+ bank->sectors = master_bank->sectors;
+}
+
+FLASH_BANK_COMMAND_HANDLER(virtual_flash_bank_command)
+{
+ if (CMD_ARGC < 7)
+ {
+ LOG_WARNING("incomplete flash_bank virtual configuration");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* get the master flash bank */
+ const char *bank_name = CMD_ARGV[6];
+ struct flash_bank *master_bank = get_flash_bank_by_name(bank_name);
+
+ if (master_bank == NULL)
+ {
+ LOG_ERROR("master flash bank '%s' does not exist", bank_name);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* save master bank name - use this to get settings later */
+ bank->driver_priv = strdup(bank_name);
+
+ return ERROR_OK;
+}
+
+static int virtual_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->protect(master_bank, set,
+ first, last)) != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_protect_check(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->protect_check(master_bank)) != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_erase(struct flash_bank *bank, int first, int last)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->erase(master_bank,
+ first, last)) != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_write(struct flash_bank *bank, uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->write(master_bank, buffer,
+ offset, count)) != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_probe(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->probe(master_bank)) != ERROR_OK)
+ return retval;
+
+ /* update the info we do not have */
+ virtual_update_bank_info(bank);
+
+ return ERROR_OK;
+}
+
+static int virtual_auto_probe(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->auto_probe(master_bank)) != ERROR_OK)
+ return retval;
+
+ /* update the info we do not have */
+ virtual_update_bank_info(bank);
+
+ return ERROR_OK;
+}
+
+static int virtual_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ snprintf(buf, buf_size, "%s driver for flash bank %s at 0x%8.8" PRIx32 "",
+ bank->driver->name, master_bank->name, master_bank->base);
+
+ return ERROR_OK;
+}
+
+int virtual_blank_check(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->erase_check(master_bank)) != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+int virtual_flash_read(struct flash_bank *bank,
+ uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL) {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* call master handler */
+ if ((retval = master_bank->driver->read(master_bank, buffer,
+ offset, count)) != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+struct flash_driver virtual_flash = {
+ .name = "virtual",
+ .flash_bank_command = virtual_flash_bank_command,
+ .erase = virtual_erase,
+ .protect = virtual_protect,
+ .write = virtual_write,
+ .read = virtual_flash_read,
+ .probe = virtual_probe,
+ .auto_probe = virtual_auto_probe,
+ .erase_check = virtual_blank_check,
+ .protect_check = virtual_protect_check,
+ .info = virtual_info,
+};
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 20 ++++
src/flash/nor/Makefile.am | 3 +-
src/flash/nor/core.c | 24 ++++-
src/flash/nor/core.h | 10 ++-
src/flash/nor/drivers.c | 2 +
src/flash/nor/tcl.c | 2 +-
src/flash/nor/virtual.c | 244 +++++++++++++++++++++++++++++++++++++++++++++
tcl/target/pic32mx.cfg | 7 ++
8 files changed, 307 insertions(+), 5 deletions(-)
create mode 100644 src/flash/nor/virtual.c
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Spencer O. <nt...@us...> - 2010-05-26 12:09:26
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ef72484b785ec7462a0415afea679d08b864c7fb (commit)
from f1c1bed39a29ae7eca2a43bccdf8feab1033e35d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ef72484b785ec7462a0415afea679d08b864c7fb
Author: Antonio Borneo <bor...@gm...>
Date: Wed May 26 10:04:03 2010 +0800
NOR/CFI: fix memory leak; check malloc return value
Every time command "flash probe #" is executed, memory
structures are re-allocated without preventive free()
of former areas, causing memory leak.
Also, memory allocation does not check return value,
determining segmentation fault in case of out of memory.
Signed-off-by: Antonio Borneo <bor...@gm...>
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index b19b945..8c1aaca 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -355,8 +355,17 @@ static int cfi_read_intel_pri_ext(struct flash_bank *bank)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
+ struct cfi_intel_pri_ext *pri_ext;
+ if (cfi_info->pri_ext)
+ free(cfi_info->pri_ext);
+
+ pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
+ if (pri_ext == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
cfi_info->pri_ext = pri_ext;
pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
@@ -413,8 +422,17 @@ static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
+ struct cfi_spansion_pri_ext *pri_ext;
+ if (cfi_info->pri_ext)
+ free(cfi_info->pri_ext);
+
+ pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
+ if (pri_ext == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
cfi_info->pri_ext = pri_ext;
pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
@@ -476,7 +494,17 @@ static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
int retval;
struct cfi_atmel_pri_ext atmel_pri_ext;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
+ struct cfi_spansion_pri_ext *pri_ext;
+
+ if (cfi_info->pri_ext)
+ free(cfi_info->pri_ext);
+
+ pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
+ if (pri_ext == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
* but a different primary extended query table.
@@ -644,6 +672,8 @@ FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
cfi_info = malloc(sizeof(struct cfi_flash_bank));
cfi_info->probed = 0;
+ cfi_info->erase_region_info = 0;
+ cfi_info->pri_ext = NULL;
bank->driver_priv = cfi_info;
cfi_info->write_algorithm = NULL;
@@ -1426,6 +1456,11 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, ui
/* convert bus-width dependent algorithm code to correct endiannes */
target_code = malloc(target_code_size);
+ if (target_code == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
/* allocate working area */
@@ -2099,6 +2134,16 @@ static int cfi_probe(struct flash_bank *bank)
}
cfi_info->probed = 0;
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+ if(cfi_info->erase_region_info)
+ {
+ free(cfi_info->erase_region_info);
+ cfi_info->erase_region_info = NULL;
+ }
/* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
* while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/cfi.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++---
1 files changed, 48 insertions(+), 3 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Spencer O. <nt...@us...> - 2010-05-24 10:23:10
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f1c1bed39a29ae7eca2a43bccdf8feab1033e35d (commit)
via e2c9518eda9d8416894dabe9ecad3a8227f95d09 (commit)
via 9c3b4cfc5d47052df955d72e88fcb4d6a1e79a60 (commit)
via 0e4f4bacdc3a5237fbc358d968ee7a8d72868d74 (commit)
via 06df4664a928c5b6de78e6ccd28499a4589d80f8 (commit)
from 2e1eaaae35e506efe6190817876b1078885a83d7 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit f1c1bed39a29ae7eca2a43bccdf8feab1033e35d
Author: Freddie Chopin <fre...@op...>
Date: Sat May 22 09:51:07 2010 +0200
There are no variants of arm7tdmi target
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg
index 1e79dcb..714267f 100644
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -22,7 +22,7 @@ jtag_ntrst_delay 100
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
# 8kB of internal SRAM
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x2000 -work-area-backup 0
diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 082e312..c511589 100644
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -25,7 +25,7 @@ adapter_khz 1000
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index dedd714..103f18e 100644
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -23,7 +23,7 @@ jtag_ntrst_delay 100
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index 07ca929..cbf3058 100644
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -27,7 +27,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg
index fdec728..8ed6352 100644
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -21,7 +21,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash configuration
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index 7ff572d..65b554c 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -22,7 +22,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
# LPC2378 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x8000 -work-area-backup 0
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index aa1cbee..df46c10 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -22,7 +22,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
# LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 0
commit e2c9518eda9d8416894dabe9ecad3a8227f95d09
Author: Freddie Chopin <fre...@op...>
Date: Fri May 21 18:02:58 2010 +0200
All LPC2xxx chips are little endian and that cannot be changed - update config scripts
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg
index b0a66bc..1e79dcb 100644
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -6,12 +6,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc2103
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -28,7 +22,7 @@ jtag_ntrst_delay 100
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# 8kB of internal SRAM
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x2000 -work-area-backup 0
diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 259088d..082e312 100644
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -1,4 +1,4 @@
-#LPC-2124 CPU
+# NXP LPC2124
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -6,20 +6,12 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc2124
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
- # force an error till we get a good number
set _CPUTAPID 0x4f1f0f0f
}
-
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
@@ -33,11 +25,10 @@ adapter_khz 1000
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14745 calc_checksum
diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index 374a395..dedd714 100644
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -6,12 +6,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc2129
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -29,7 +23,7 @@ jtag_ntrst_delay 100
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index 2199abc..07ca929 100644
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -9,12 +9,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc2148
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -33,7 +27,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg
index 023b445..fdec728 100644
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -4,12 +4,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc2294
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -27,7 +21,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash configuration
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index a3c0992..7ff572d 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -6,12 +6,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc2378
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -28,7 +22,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# LPC2378 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x8000 -work-area-backup 0
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index c430e43..aa1cbee 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -6,12 +6,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc2478
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -28,7 +22,7 @@ reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 0
commit 9c3b4cfc5d47052df955d72e88fcb4d6a1e79a60
Author: Freddie Chopin <fre...@op...>
Date: Fri May 21 17:57:10 2010 +0200
add correct CPUTAPID value for LPC2129
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index 1ecf7d0..374a395 100644
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -1,5 +1,4 @@
-#LPC-2129 CPU
-
+# NXP LPC2129
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -16,11 +15,9 @@ if { [info exists ENDIAN] } {
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
+ set _CPUTAPID 0xcf1f0f0f
}
-
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
@@ -31,7 +28,6 @@ jtag_ntrst_delay 100
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
commit 0e4f4bacdc3a5237fbc358d968ee7a8d72868d74
Author: Freddie Chopin <fre...@op...>
Date: Fri May 21 17:52:25 2010 +0200
Update "flash bank" helper comments for LPC2xxx chips
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 82a097f..fc00d78 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -42,6 +42,7 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
# LPC1768 has 512kB of flash memory, managed by ROM code (including a
# boot loader which verifies the flash exception table's checksum).
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg
index 2ebe91a..b0a66bc 100644
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -34,6 +34,6 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x2000 -work-area-backup 0
# 32kB of internal Flash, core clocked with 12MHz crystal
-# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x8000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 1b60c15..259088d 100644
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -38,6 +38,6 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14745 calc_checksum
diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index 5b2a2f7..1ecf7d0 100644
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -37,6 +37,6 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index 502a355..2199abc 100644
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -51,6 +51,6 @@ $_TARGETNAME configure -event reset-init {
mwb 0xE01FC040 0x01
}
-# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME lpc2000_v2 14765 calc_checksum
diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg
index 9ac3c6c..023b445 100644
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -31,7 +31,7 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash configuration
-#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index 1a42e07..a3c0992 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -42,7 +42,7 @@ $_TARGETNAME configure -event reset-init {
# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
# After reset the chip uses its internal 4MHz RC oscillator
-#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 57aa36f..c430e43 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -42,7 +42,7 @@ $_TARGETNAME configure -event reset-init {
# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
# After reset the chip uses its internal 4MHz RC oscillator.
-# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
commit 06df4664a928c5b6de78e6ccd28499a4589d80f8
Author: Freddie Chopin <fre...@op...>
Date: Fri May 21 17:46:40 2010 +0200
LPC23xx and LPC24xx after reset run on internal 4MHz RC oscillator, so "flash bank" parameter should be 4000 (not 12000)
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 950ef63..57aa36f 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -44,7 +44,7 @@ $_TARGETNAME configure -event reset-init {
# After reset the chip uses its internal 4MHz RC oscillator.
# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
+flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
# Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 = 666kHz, so use 500.
jtag_rclk 500
-----------------------------------------------------------------------
Summary of changes:
tcl/target/lpc1768.cfg | 1 +
tcl/target/lpc2103.cfg | 10 ++--------
tcl/target/lpc2124.cfg | 15 +++------------
tcl/target/lpc2129.cfg | 18 ++++--------------
tcl/target/lpc2148.cfg | 10 ++--------
tcl/target/lpc2294.cfg | 10 ++--------
tcl/target/lpc2378.cfg | 10 ++--------
tcl/target/lpc2478.cfg | 12 +++---------
8 files changed, 19 insertions(+), 67 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-05-21 14:09:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2e1eaaae35e506efe6190817876b1078885a83d7 (commit)
from 82ef8472bf6986d09f595dbea151413502b42280 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2e1eaaae35e506efe6190817876b1078885a83d7
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri May 21 13:56:05 2010 +0200
at91sam9260: use RCLK
It might be possible to get this target going without
RCLK, but it would require more careful analysis and
usage of the reset events.
Enable fast memory accesses.
Tested on an at91sam9260 custom board w/external DRAM
and flash.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index d2bf66f..535ae0f 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -1,8 +1,4 @@
-
-
-
-adapter_khz 4
-
+jtag_rclk 4
######################################
# Target: Atmel AT91SAM9260
@@ -44,26 +40,29 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-$_TARGETNAME invoke-event halted
-
# Internal sram1 memory
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
scan_chain
-$_TARGETNAME configure -event reset-deassert-post {at91sam_init}
+$_TARGETNAME configure -event reset-start {
+ # at reset chip runs at 32khz
+ jtag_rclk 8
+}
+$_TARGETNAME configure -event reset-init {at91sam_init}
# Flash configuration
#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+# Faster memory downloads. This is disabled automatically during
+# reset init since all reset init sequences are too short for
+# fast memory access
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
proc at91sam_init { } {
-
- # at reset chip runs at 32khz
- adapter_khz 8
- halt
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
@@ -79,16 +78,13 @@ proc at91sam_init { } {
sleep 10 # wait 10 ms
# Now run at anything fast... ie: 10mhz!
- adapter_khz 10000 # Increase JTAG Speed to 6 MHz
- arm7_9 dcc_downloads enable # Enable faster DCC downloads
+ jtag_rclk 10000 # Increase JTAG Speed to 6 MHz
mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
mww 0xffffec08 0x00160016 # SMC_CYCLE0
mww 0xffffec0c 0x00161003 # SMC_MODE0
- flash probe 0 # Identify flash bank 0
-
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
@@ -123,6 +119,3 @@ proc at91sam_init { } {
mww 0x20000000 0
mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
}
-
-
-
-----------------------------------------------------------------------
Summary of changes:
tcl/target/at91sam9260_ext_RAM_ext_flash.cfg | 31 ++++++++++----------------
1 files changed, 12 insertions(+), 19 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Spencer O. <nt...@us...> - 2010-05-21 12:50:46
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 82ef8472bf6986d09f595dbea151413502b42280 (commit)
via c0cdb7c63189edf0d96a1b0242d80c94532b30e7 (commit)
from 72ba8ec90e42a3fc4470e7e0d1c0f8b1d060529a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 82ef8472bf6986d09f595dbea151413502b42280
Author: Spencer Oliver <nt...@us...>
Date: Fri May 21 11:45:40 2010 +0100
cfg: update stm32 performance stick config
- As this is a complete unit, including jtag we might as welli nclude
the jtag cfg.
- Add missing id for the str750 that is also in the jtag chain.
- Reduce jtag startup speed to 500kHz.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/board/hitex_stm32-performancestick.cfg b/tcl/board/hitex_stm32-performancestick.cfg
index 509f98a..515f7e0 100644
--- a/tcl/board/hitex_stm32-performancestick.cfg
+++ b/tcl/board/hitex_stm32-performancestick.cfg
@@ -1,9 +1,16 @@
# Hitex stm32 performance stick
+reset_config trst_and_srst
+
+source [find interface/stm32-stick.cfg]
+
set CHIPNAME stm32_hitex
source [find target/stm32.cfg]
# configure str750 connected to jtag chain
# FIXME -- source [find target/str750.cfg] after cleaning that up
-jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
+jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
+
+# for some reason this board like to startup @ 500kHz
+adapter_khz 500
commit c0cdb7c63189edf0d96a1b0242d80c94532b30e7
Author: Spencer Oliver <nt...@us...>
Date: Fri May 21 11:43:17 2010 +0100
arm_adi_v5: correct ahbap_debugport_init mem-ap id (bug #23)
We request a id register read at the end of ahbap_debugport_init
but we never actually run the queue. In some cases this causes a
segfault.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 8b18fa3..8f43f78 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -967,6 +967,9 @@ int ahbap_debugport_init(struct adiv5_dap *dap)
retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
+ if ((retval = dap_run(dap)) != ERROR_OK)
+ return retval;
+
LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
", Debug ROM Address 0x%" PRIx32,
dap->apsel, idreg, romaddr);
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_adi_v5.c | 3 +++
tcl/board/hitex_stm32-performancestick.cfg | 9 ++++++++-
2 files changed, 11 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-05-21 07:32:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 72ba8ec90e42a3fc4470e7e0d1c0f8b1d060529a (commit)
from f40faeb349e417e566bf100aa08a9246501a82c5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 72ba8ec90e42a3fc4470e7e0d1c0f8b1d060529a
Author: Jon Povey <jon...@ra...>
Date: Fri May 21 12:34:46 2010 +0900
board: dm355evm.cfg SDTIMR0/1 minor naming fix
Register name fix; ref. TI document sprueh7d
Signed-off-by: Jon Povey <jon...@ra...>
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index db47b8d..02c4c86 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -117,7 +117,7 @@ proc dm355evm_init {} {
mmw [expr $addr + 0x08] 0x00800000 0
mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
- # SDTIMR, SDTIMR2
+ # SDTIMR0, SDTIMR1
mww [expr $addr + 0x10] 0x2a923249
mww [expr $addr + 0x14] 0x4c17c763
-----------------------------------------------------------------------
Summary of changes:
tcl/board/dm355evm.cfg | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: Øyvind H. <go...@us...> - 2010-05-20 08:29:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f40faeb349e417e566bf100aa08a9246501a82c5 (commit)
from 8465e9944291a03a216fa15e0d7ed6eb9d44ba92 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit f40faeb349e417e566bf100aa08a9246501a82c5
Author: gcembed <gc...@gm...>
Date: Thu May 20 08:25:09 2010 +0200
nand : Add Freescale iMX27 nand flash controller support
This patch add support of iMX27 nand flash controller. This is based on
driver for imx31 nand flash controller.
OOB functionality is not fully working. As in mx31 controller, mx2 NFC
has a bug that swap two bytes between SPARE and MAIN buffer.
I used this driver for several months and no problems appear.
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index a495dfd..259a9cb 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -18,6 +18,7 @@ NAND_DRIVERS = \
nonce.c \
davinci.c \
lpc3180.c \
+ mx2.c \
mx3.c \
orion.c \
s3c24xx.c \
@@ -35,6 +36,7 @@ noinst_HEADERS = \
fileio.h \
imp.h \
lpc3180.h \
+ mx2.h \
mx3.h \
s3c24xx.h \
s3c24xx_regs.h
diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 1c28dbc..597d78a 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -37,6 +37,7 @@ extern struct nand_flash_controller s3c2412_nand_controller;
extern struct nand_flash_controller s3c2440_nand_controller;
extern struct nand_flash_controller s3c2443_nand_controller;
extern struct nand_flash_controller s3c6400_nand_controller;
+extern struct nand_flash_controller imx27_nand_flash_controller;
extern struct nand_flash_controller imx31_nand_flash_controller;
extern struct nand_flash_controller at91sam9_nand_controller;
@@ -53,6 +54,7 @@ static struct nand_flash_controller *nand_flash_controllers[] =
&s3c2440_nand_controller,
&s3c2443_nand_controller,
&s3c6400_nand_controller,
+ &imx27_nand_flash_controller,
&imx31_nand_flash_controller,
&at91sam9_nand_controller,
/* &boundary_scan_nand_controller, */
diff --git a/src/flash/nand/mx2.c b/src/flash/nand/mx2.c
new file mode 100644
index 0000000..83e1cb1
--- /dev/null
+++ b/src/flash/nand/mx2.c
@@ -0,0 +1,776 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Alexei Babich *
+ * Rezonans plc., Chelyabinsk, Russia *
+ * im...@ma... *
+ * *
+ * Copyright (C) 2010 by Gaetan CARLIER *
+ * Trump s.a., Belgium *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+/*
+ * Freescale iMX2* OpenOCD NAND Flash controller support.
+ * based on Freescale iMX3* OpenOCD NAND Flash controller support.
+ */
+
+/*
+ * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
+ * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
+ * "nand write # file 0", "nand verify"
+ *
+ * get_next_halfword_from_sram_buffer() not tested
+ * !! all function only tested with 2k page nand device; imx27_write_page
+ * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
+ * !! oob must be be used due to NFS bug
+*/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include "mx2.h"
+#include <target/target.h>
+
+/* This permits to print (in LOG_INFO) how much bytes
+ * has been written after a page read or write.
+ * This is useful when OpenOCD is used with a graphical
+ * front-end to estimate progression of the global read/write
+ */
+#undef _MX2_PRINT_STAT
+//#define _MX2_PRINT_STAT
+
+static const char target_not_halted_err_msg[] =
+ "target must be halted to use mx2 NAND flash controller";
+static const char data_block_size_err_msg[] =
+ "minimal granularity is one half-word, %" PRId32 " is incorrect";
+static const char sram_buffer_bounds_err_msg[] =
+ "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
+static const char get_status_register_err_msg[] = "can't get NAND status";
+static uint32_t in_sram_address;
+unsigned char sign_of_sequental_byte_read;
+
+static int initialize_nf_controller(struct nand_device *nand);
+static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value);
+static int get_next_halfword_from_sram_buffer(struct target * target,
+ uint16_t * value);
+static int poll_for_complete_op(struct target * target, const char *text);
+static int validate_target_state(struct nand_device *nand);
+static int do_data_output(struct nand_device *nand);
+
+static int imx27_command(struct nand_device *nand, uint8_t command);
+static int imx27_address(struct nand_device *nand, uint8_t address);
+static int imx27_controller_ready(struct nand_device *nand, int tout);
+
+NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
+{
+ struct mx2_nf_controller *mx2_nf_info;
+ int hwecc_needed;
+ int x;
+ mx2_nf_info = malloc(sizeof(struct mx2_nf_controller));
+ if (mx2_nf_info == NULL) {
+ LOG_ERROR("no memory for nand controller");
+ return ERROR_FAIL;
+ }
+
+ nand->controller_priv = mx2_nf_info;
+ mx2_nf_info->target = get_target(CMD_ARGV[1]);
+ if (mx2_nf_info->target == NULL) {
+ LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
+ return ERROR_FAIL;
+ }
+ if (CMD_ARGC < 3) {
+ LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
+ return ERROR_FAIL;
+ }
+ /*
+ * check hwecc requirements
+ */
+
+ hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
+ if (hwecc_needed == 0)
+ mx2_nf_info->flags.hw_ecc_enabled = 1;
+ else
+ mx2_nf_info->flags.hw_ecc_enabled = 0;
+
+ mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
+ mx2_nf_info->fin = MX2_NF_FIN_NONE;
+ mx2_nf_info->flags.target_little_endian =
+ (mx2_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
+ /*
+ * testing host endianess
+ */
+ x = 1;
+ if (*(char *) &x == 1)
+ mx2_nf_info->flags.host_little_endian = 1;
+ else
+ mx2_nf_info->flags.host_little_endian = 0;
+ return ERROR_OK;
+}
+
+static int imx27_init(struct nand_device *nand)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+
+ int validate_target_result;
+ uint16_t buffsize_register_content;
+ uint32_t pcsr_register_content;
+ int retval;
+ uint16_t nand_status_content;
+ /*
+ * validate target state
+ */
+ validate_target_result = validate_target_state(nand);
+ if (validate_target_result != ERROR_OK)
+ return validate_target_result;
+
+ target_read_u16(target, MX2_NF_BUFSIZ, &buffsize_register_content);
+ mx2_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
+
+ target_read_u32(target, MX2_FMCR, &pcsr_register_content);
+ if (!nand->bus_width) {
+ /* bus_width not yet defined. Read it from MX2_FMCR */
+ nand->bus_width =
+ (pcsr_register_content & MX2_FMCR_NF_16BIT_SEL) ? 16 : 8;
+ } else {
+ /* bus_width forced in soft. Sync it to MX2_FMCR */
+ pcsr_register_content |=
+ ((nand->bus_width == 16) ? MX2_FMCR_NF_16BIT_SEL : 0x00000000);
+ target_write_u32(target, MX2_FMCR, pcsr_register_content);
+ }
+ if (nand->bus_width == 16)
+ LOG_DEBUG("MX2_NF : bus is 16-bit width");
+ else
+ LOG_DEBUG("MX2_NF : bus is 8-bit width");
+
+ if (!nand->page_size) {
+ nand->page_size =
+ (pcsr_register_content & MX2_FMCR_NF_FMS) ? 2048 : 512;
+ } else {
+ pcsr_register_content |=
+ ((nand->page_size == 2048) ? MX2_FMCR_NF_FMS : 0x00000000);
+ target_write_u32(target, MX2_FMCR, pcsr_register_content);
+ }
+ if (mx2_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
+ LOG_ERROR("NAND controller have only 1 kb SRAM, so "
+ "pagesize 2048 is incompatible with it");
+ } else {
+ LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
+ }
+
+ initialize_nf_controller(nand);
+
+ retval = ERROR_OK;
+ retval |= imx27_command(nand, NAND_CMD_STATUS);
+ retval |= imx27_address(nand, 0x00);
+ retval |= do_data_output(nand);
+ if (retval != ERROR_OK) {
+ LOG_ERROR(get_status_register_err_msg);
+ return ERROR_FAIL;
+ }
+ target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
+ if (!(nand_status_content & 0x0080)) {
+ LOG_INFO("NAND read-only");
+ mx2_nf_info->flags.nand_readonly = 1;
+ } else {
+ mx2_nf_info->flags.nand_readonly = 0;
+ }
+ return ERROR_OK;
+}
+
+static int imx27_read_data(struct nand_device *nand, void *data)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ int validate_target_result;
+ int try_data_output_from_nand_chip;
+ /*
+ * validate target state
+ */
+ validate_target_result = validate_target_state(nand);
+ if (validate_target_result != ERROR_OK)
+ return validate_target_result;
+
+ /*
+ * get data from nand chip
+ */
+ try_data_output_from_nand_chip = do_data_output(nand);
+ if (try_data_output_from_nand_chip != ERROR_OK) {
+ LOG_ERROR("imx27_read_data : read data failed : '%x'",
+ try_data_output_from_nand_chip);
+ return try_data_output_from_nand_chip;
+ }
+
+ if (nand->bus_width == 16)
+ get_next_halfword_from_sram_buffer(target, data);
+ else
+ get_next_byte_from_sram_buffer(target, data);
+
+ return ERROR_OK;
+}
+
+static int imx27_write_data(struct nand_device *nand, uint16_t data)
+{
+ LOG_ERROR("write_data() not implemented");
+ return ERROR_NAND_OPERATION_FAILED;
+}
+
+static int imx27_nand_ready(struct nand_device *nand, int timeout)
+{
+ return imx27_controller_ready(nand, timeout);
+}
+
+static int imx27_reset(struct nand_device *nand)
+{
+ /*
+ * validate target state
+ */
+ int validate_target_result;
+ validate_target_result = validate_target_state(nand);
+ if (validate_target_result != ERROR_OK)
+ return validate_target_result;
+ initialize_nf_controller(nand);
+ return ERROR_OK;
+}
+
+static int imx27_command(struct nand_device *nand, uint8_t command)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ int validate_target_result;
+ int poll_result;
+ /*
+ * validate target state
+ */
+ validate_target_result = validate_target_state(nand);
+ if (validate_target_result != ERROR_OK)
+ return validate_target_result;
+
+ switch(command) {
+ case NAND_CMD_READOOB:
+ command = NAND_CMD_READ0;
+ /* set read point for data_read() and read_block_data() to
+ * spare area in SRAM buffer
+ */
+ in_sram_address = MX2_NF_SPARE_BUFFER0;
+ break;
+ case NAND_CMD_READ1:
+ command = NAND_CMD_READ0;
+ /*
+ * offset == one half of page size
+ */
+ in_sram_address =
+ MX2_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
+ break;
+ default:
+ in_sram_address = MX2_NF_MAIN_BUFFER0;
+ break;
+ }
+
+ target_write_u16(target, MX2_NF_FCMD, command);
+ /*
+ * start command input operation (set MX2_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FCI);
+ poll_result = poll_for_complete_op(target, "command");
+ if (poll_result != ERROR_OK)
+ return poll_result;
+ /*
+ * reset cursor to begin of the buffer
+ */
+ sign_of_sequental_byte_read = 0;
+ /* Handle special read command and adjust NF_CFG2(FDO) */
+ switch(command) {
+ case NAND_CMD_READID:
+ mx2_nf_info->optype = MX2_NF_DATAOUT_NANDID;
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ break;
+ case NAND_CMD_STATUS:
+ mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ target_write_u16 (target, MX2_NF_BUFADDR, 0);
+ in_sram_address = 0;
+ break;
+ case NAND_CMD_READ0:
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
+ break;
+ default:
+ /* Ohter command use the default 'One page data out' FDO */
+ mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
+ break;
+ }
+ return ERROR_OK;
+}
+
+static int imx27_address(struct nand_device *nand, uint8_t address)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ int validate_target_result;
+ int poll_result;
+ /*
+ * validate target state
+ */
+ validate_target_result = validate_target_state(nand);
+ if (validate_target_result != ERROR_OK)
+ return validate_target_result;
+
+ target_write_u16(target, MX2_NF_FADDR, address);
+ /*
+ * start address input operation (set MX2_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FAI);
+ poll_result = poll_for_complete_op(target, "address");
+ if (poll_result != ERROR_OK)
+ return poll_result;
+
+ return ERROR_OK;
+}
+
+static int imx27_controller_ready(struct nand_device *nand, int tout)
+{
+ uint16_t poll_complete_status;
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ int validate_target_result;
+
+ /*
+ * validate target state
+ */
+ validate_target_result = validate_target_state(nand);
+ if (validate_target_result != ERROR_OK)
+ return validate_target_result;
+
+ do {
+ target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
+ if (poll_complete_status & MX2_NF_BIT_OP_DONE)
+ return tout;
+
+ alive_sleep(1);
+ }
+ while (tout-- > 0);
+ return tout;
+}
+
+static int imx27_write_page(struct nand_device *nand, uint32_t page,
+ uint8_t * data, uint32_t data_size, uint8_t * oob,
+ uint32_t oob_size)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ int retval;
+ uint16_t nand_status_content;
+ uint16_t swap1, swap2, new_swap1;
+ int poll_result;
+ if (data_size % 2) {
+ LOG_ERROR(data_block_size_err_msg, data_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ if (oob_size % 2) {
+ LOG_ERROR(data_block_size_err_msg, oob_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ if (!data) {
+ LOG_ERROR("nothing to program");
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ /*
+ * validate target state
+ */
+ retval = validate_target_state(nand);
+ if (retval != ERROR_OK)
+ return retval;
+
+ in_sram_address = MX2_NF_MAIN_BUFFER0;
+ sign_of_sequental_byte_read = 0;
+ retval = ERROR_OK;
+ retval |= imx27_command(nand, NAND_CMD_SEQIN);
+ retval |= imx27_address(nand, 0); //col
+ retval |= imx27_address(nand, 0); //col
+ retval |= imx27_address(nand, page & 0xff); //page address
+ retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
+ retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
+
+ target_write_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
+ if (oob) {
+ if (mx2_nf_info->flags.hw_ecc_enabled) {
+ /*
+ * part of spare block will be overrided by hardware
+ * ECC generator
+ */
+ LOG_DEBUG("part of spare block will be overrided "
+ "by hardware ECC generator");
+ }
+ target_write_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
+ oob);
+ }
+ //BI-swap - work-around of imx27 NFC for NAND device with page == 2kb
+ target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
+ if (oob) {
+ LOG_ERROR("Due to NFC Bug, oob is not correctly implemented "
+ "in mx2 driver");
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ //target_read_u16 (target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
+ swap2 = 0xffff; //Spare buffer unused forced to 0xffff
+ new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
+ swap2 = (swap1 << 8) | (swap2 & 0xFF);
+
+ target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
+ target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
+ /*
+ * start data input operation (set MX2_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16(target, MX2_NF_BUFADDR, 0);
+ target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
+ poll_result = poll_for_complete_op(target, "data input");
+ if (poll_result != ERROR_OK)
+ return poll_result;
+
+ target_write_u16(target, MX2_NF_BUFADDR, 1);
+ target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
+ poll_result = poll_for_complete_op(target, "data input");
+ if (poll_result != ERROR_OK)
+ return poll_result;
+
+ target_write_u16(target, MX2_NF_BUFADDR, 2);
+ target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
+ poll_result = poll_for_complete_op(target, "data input");
+ if (poll_result != ERROR_OK)
+ return poll_result;
+
+ target_write_u16(target, MX2_NF_BUFADDR, 3);
+ target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
+ poll_result = poll_for_complete_op(target, "data input");
+ if (poll_result != ERROR_OK)
+ return poll_result;
+
+ retval |= imx27_command(nand, NAND_CMD_PAGEPROG);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /*
+ * check status register
+ */
+ retval = ERROR_OK;
+ retval |= imx27_command(nand, NAND_CMD_STATUS);
+ target_write_u16 (target, MX2_NF_BUFADDR, 0);
+ mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ retval |= do_data_output(nand);
+ if (retval != ERROR_OK) {
+ LOG_ERROR (get_status_register_err_msg);
+ return retval;
+ }
+ target_read_u16 (target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
+ if (nand_status_content & 0x0001) {
+ /*
+ * page not correctly written
+ */
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+#ifdef _MX2_PRINT_STAT
+ LOG_INFO("%d bytes newly written", data_size);
+#endif
+ return ERROR_OK;
+}
+
+static int imx27_read_page(struct nand_device *nand, uint32_t page,
+ uint8_t * data, uint32_t data_size, uint8_t * oob,
+ uint32_t oob_size)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ int retval;
+ uint16_t swap1, swap2, new_swap1;
+ if (data_size % 2) {
+ LOG_ERROR(data_block_size_err_msg, data_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ if (oob_size % 2) {
+ LOG_ERROR(data_block_size_err_msg, oob_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ /*
+ * validate target state
+ */
+ retval = validate_target_state(nand);
+ if (retval != ERROR_OK) {
+ return retval;
+ }
+ /* Reset address_cycles before imx27_command ?? */
+ retval = ERROR_OK;
+ retval |= imx27_command(nand, NAND_CMD_READ0);
+
+ retval |= imx27_address(nand, 0); //col
+ retval |= imx27_address(nand, 0); //col
+ retval |= imx27_address(nand, page & 0xff); //page address
+ retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
+ retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
+ retval |= imx27_command(nand, NAND_CMD_READSTART);
+
+ target_write_u16(target, MX2_NF_BUFADDR, 0);
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ retval = do_data_output(nand);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MX2_NF : Error reading page 0");
+ return retval;
+ }
+ //Test nand page size to know how much MAIN_BUFFER must be written
+ target_write_u16(target, MX2_NF_BUFADDR, 1);
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ retval = do_data_output(nand);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MX2_NF : Error reading page 1");
+ return retval;
+ }
+ target_write_u16(target, MX2_NF_BUFADDR, 2);
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ retval = do_data_output(nand);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MX2_NF : Error reading page 2");
+ return retval;
+ }
+ target_write_u16(target, MX2_NF_BUFADDR, 3);
+ mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
+ retval = do_data_output(nand);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("MX2_NF : Error reading page 3");
+ return retval;
+ }
+ //BI-swap - work-around of imx27 NFC for NAND device with page == 2k
+ target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
+ target_read_u16(target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
+ new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
+ swap2 = (swap1 << 8) | (swap2 & 0xFF);
+ target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
+ target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
+
+ if (data)
+ target_read_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
+ if (oob)
+ target_read_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
+ oob);
+#ifdef _MX2_PRINT_STAT
+ if (data_size > 0) {
+ /* When Operation Status is read (when page is erased),
+ * this function is used but data_size is null.
+ */
+ LOG_INFO("%d bytes newly read", data_size);
+ }
+#endif
+ return ERROR_OK;
+}
+
+static int initialize_nf_controller(struct nand_device *nand)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ uint16_t work_mode;
+ uint16_t temp;
+ /*
+ * resets NAND flash controller in zero time ? I dont know.
+ */
+ target_write_u16(target, MX2_NF_CFG1, MX2_NF_BIT_RESET_EN);
+ work_mode = MX2_NF_BIT_INT_DIS; /* disable interrupt */
+ if (target->endianness == TARGET_BIG_ENDIAN) {
+ LOG_DEBUG("MX2_NF : work in Big Endian mode");
+ work_mode |= MX2_NF_BIT_BE_EN;
+ } else {
+ LOG_DEBUG("MX2_NF : work in Little Endian mode");
+ }
+ if (mx2_nf_info->flags.hw_ecc_enabled) {
+ LOG_DEBUG("MX2_NF : work with ECC mode");
+ work_mode |= MX2_NF_BIT_ECC_EN;
+ } else {
+ LOG_DEBUG("MX2_NF : work without ECC mode");
+ }
+ target_write_u16(target, MX2_NF_CFG1, work_mode);
+ /*
+ * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
+ */
+ target_write_u16(target, MX2_NF_BUFCFG, 2);
+ target_read_u16(target, MX2_NF_FWP, &temp);
+ if ((temp & 0x0007) == 1) {
+ LOG_ERROR("NAND flash is tight-locked, reset needed");
+ return ERROR_FAIL;
+ }
+
+ /*
+ * unlock NAND flash for write
+ */
+ target_write_u16(target, MX2_NF_FWP, 4);
+ target_write_u16(target, MX2_NF_LOCKSTART, 0x0000);
+ target_write_u16(target, MX2_NF_LOCKEND, 0xFFFF);
+ /*
+ * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
+ */
+ target_write_u16(target, MX2_NF_BUFADDR, 0x0000);
+ /*
+ * address of SRAM buffer
+ */
+ in_sram_address = MX2_NF_MAIN_BUFFER0;
+ sign_of_sequental_byte_read = 0;
+ return ERROR_OK;
+}
+
+static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value)
+{
+ static uint8_t even_byte = 0;
+ uint16_t temp;
+ /*
+ * host-big_endian ??
+ */
+ if (sign_of_sequental_byte_read == 0)
+ even_byte = 0;
+
+ if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
+ LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
+ *value = 0;
+ sign_of_sequental_byte_read = 0;
+ even_byte = 0;
+ return ERROR_NAND_OPERATION_FAILED;
+ } else {
+ target_read_u16(target, in_sram_address, &temp);
+ if (even_byte) {
+ *value = temp >> 8;
+ even_byte = 0;
+ in_sram_address += 2;
+ } else {
+ *value = temp & 0xff;
+ even_byte = 1;
+ }
+ }
+ sign_of_sequental_byte_read = 1;
+ return ERROR_OK;
+}
+
+static int get_next_halfword_from_sram_buffer(struct target * target,
+ uint16_t * value)
+{
+ if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
+ LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
+ *value = 0;
+ return ERROR_NAND_OPERATION_FAILED;
+ } else {
+ target_read_u16(target, in_sram_address, value);
+ in_sram_address += 2;
+ }
+ return ERROR_OK;
+}
+
+static int poll_for_complete_op(struct target * target, const char *text)
+{
+ uint16_t poll_complete_status;
+ for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
+ target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
+ if (poll_complete_status & MX2_NF_BIT_OP_DONE)
+ break;
+
+ usleep(10);
+ }
+ if (!(poll_complete_status & MX2_NF_BIT_OP_DONE)) {
+ LOG_ERROR("%s sending timeout", text);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ return ERROR_OK;
+}
+
+static int validate_target_state(struct nand_device *nand)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR(target_not_halted_err_msg);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ if (mx2_nf_info->flags.target_little_endian !=
+ (target->endianness == TARGET_LITTLE_ENDIAN)) {
+ /*
+ * endianness changed after NAND controller probed
+ */
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ return ERROR_OK;
+}
+
+static int do_data_output(struct nand_device *nand)
+{
+ struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
+ struct target *target = mx2_nf_info->target;
+ int poll_result;
+ uint16_t ecc_status;
+ switch(mx2_nf_info->fin) {
+ case MX2_NF_FIN_DATAOUT:
+ /*
+ * start data output operation (set MX2_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info->optype));
+ poll_result = poll_for_complete_op(target, "data output");
+ if (poll_result != ERROR_OK)
+ return poll_result;
+
+ mx2_nf_info->fin = MX2_NF_FIN_NONE;
+ /*
+ * ECC stuff
+ */
+ if ((mx2_nf_info->optype == MX2_NF_DATAOUT_PAGE) && mx2_nf_info->flags.hw_ecc_enabled) {
+ target_read_u16(target, MX2_NF_ECCSTATUS, &ecc_status);
+ switch(ecc_status & 0x000c) {
+ case 1 << 2:
+ LOG_INFO("main area readed with 1 (correctable) error");
+ break;
+ case 2 << 2:
+ LOG_INFO("main area readed with more than 1 (incorrectable) error");
+ return ERROR_NAND_OPERATION_FAILED;
+ break;
+ }
+ switch(ecc_status & 0x0003) {
+ case 1:
+ LOG_INFO("spare area readed with 1 (correctable) error");
+ break;
+ case 2:
+ LOG_INFO("main area readed with more than 1 (incorrectable) error");
+ return ERROR_NAND_OPERATION_FAILED;
+ break;
+ }
+ }
+ break;
+ case MX2_NF_FIN_NONE:
+ break;
+ }
+ return ERROR_OK;
+}
+
+struct nand_flash_controller imx27_nand_flash_controller = {
+ .name = "imx27",
+ .nand_device_command = &imx27_nand_device_command,
+ .init = &imx27_init,
+ .reset = &imx27_reset,
+ .command = &imx27_command,
+ .address = &imx27_address,
+ .write_data = &imx27_write_data,
+ .read_data = &imx27_read_data,
+ .write_page = &imx27_write_page,
+ .read_page = &imx27_read_page,
+ .controller_ready = &imx27_controller_ready,
+ .nand_ready = &imx27_nand_ready,
+};
diff --git a/src/flash/nand/mx2.h b/src/flash/nand/mx2.h
new file mode 100644
index 0000000..5d0b942
--- /dev/null
+++ b/src/flash/nand/mx2.h
@@ -0,0 +1,120 @@
+
+/***************************************************************************
+ * Copyright (C) 2009 by Alexei Babich *
+ * Rezonans plc., Chelyabinsk, Russia *
+ * im...@ma... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+/*
+ * Freescale iMX2* OpenOCD NAND Flash controller support.
+ * based on Freescale iMX3* OpenOCD NAND Flash controller support.
+ *
+ * Many thanks to Ben Dooks for writing s3c24xx driver.
+ */
+
+#define MX2_NF_BASE_ADDR 0xd8000000
+#define MX2_NF_BUFSIZ (MX2_NF_BASE_ADDR + 0xe00)
+#define MX2_NF_BUFADDR (MX2_NF_BASE_ADDR + 0xe04)
+#define MX2_NF_FADDR (MX2_NF_BASE_ADDR + 0xe06)
+#define MX2_NF_FCMD (MX2_NF_BASE_ADDR + 0xe08)
+#define MX2_NF_BUFCFG (MX2_NF_BASE_ADDR + 0xe0a)
+#define MX2_NF_ECCSTATUS (MX2_NF_BASE_ADDR + 0xe0c)
+#define MX2_NF_ECCMAINPOS (MX2_NF_BASE_ADDR + 0xe0e)
+#define MX2_NF_ECCSPAREPOS (MX2_NF_BASE_ADDR + 0xe10)
+#define MX2_NF_FWP (MX2_NF_BASE_ADDR + 0xe12)
+#define MX2_NF_LOCKSTART (MX2_NF_BASE_ADDR + 0xe14)
+#define MX2_NF_LOCKEND (MX2_NF_BASE_ADDR + 0xe16)
+#define MX2_NF_FWPSTATUS (MX2_NF_BASE_ADDR + 0xe18)
+ /*
+ * all bits not marked as self-clearing bit
+ */
+#define MX2_NF_CFG1 (MX2_NF_BASE_ADDR + 0xe1a)
+#define MX2_NF_CFG2 (MX2_NF_BASE_ADDR + 0xe1c)
+
+#define MX2_NF_MAIN_BUFFER0 (MX2_NF_BASE_ADDR + 0x0000)
+#define MX2_NF_MAIN_BUFFER1 (MX2_NF_BASE_ADDR + 0x0200)
+#define MX2_NF_MAIN_BUFFER2 (MX2_NF_BASE_ADDR + 0x0400)
+#define MX2_NF_MAIN_BUFFER3 (MX2_NF_BASE_ADDR + 0x0600)
+#define MX2_NF_SPARE_BUFFER0 (MX2_NF_BASE_ADDR + 0x0800)
+#define MX2_NF_SPARE_BUFFER1 (MX2_NF_BASE_ADDR + 0x0810)
+#define MX2_NF_SPARE_BUFFER2 (MX2_NF_BASE_ADDR + 0x0820)
+#define MX2_NF_SPARE_BUFFER3 (MX2_NF_BASE_ADDR + 0x0830)
+#define MX2_NF_MAIN_BUFFER_LEN 512
+#define MX2_NF_SPARE_BUFFER_LEN 16
+#define MX2_NF_LAST_BUFFER_ADDR ((MX2_NF_SPARE_BUFFER3) + MX2_NF_SPARE_BUFFER_LEN - 2)
+
+/* bits in MX2_NF_CFG1 register */
+#define MX2_NF_BIT_SPARE_ONLY_EN (1<<2)
+#define MX2_NF_BIT_ECC_EN (1<<3)
+#define MX2_NF_BIT_INT_DIS (1<<4)
+#define MX2_NF_BIT_BE_EN (1<<5)
+#define MX2_NF_BIT_RESET_EN (1<<6)
+#define MX2_NF_BIT_FORCE_CE (1<<7)
+
+/* bits in MX2_NF_CFG2 register */
+
+/*Flash Command Input*/
+#define MX2_NF_BIT_OP_FCI (1<<0)
+ /*
+ * Flash Address Input
+ */
+#define MX2_NF_BIT_OP_FAI (1<<1)
+ /*
+ * Flash Data Input
+ */
+#define MX2_NF_BIT_OP_FDI (1<<2)
+
+/* see "enum mx_dataout_type" below */
+#define MX2_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
+#define MX2_NF_BIT_OP_DONE (1<<15)
+
+#define MX2_CCM_CGR2 0x53f80028
+#define MX2_GPR 0x43fac008
+//#define MX2_PCSR 0x53f8000c
+#define MX2_FMCR 0x10027814
+#define MX2_FMCR_NF_16BIT_SEL (1<<4)
+#define MX2_FMCR_NF_FMS (1<<5)
+
+enum mx_dataout_type
+{
+ MX2_NF_DATAOUT_PAGE = 1,
+ MX2_NF_DATAOUT_NANDID = 2,
+ MX2_NF_DATAOUT_NANDSTATUS = 4,
+};
+enum mx_nf_finalize_action
+{
+ MX2_NF_FIN_NONE,
+ MX2_NF_FIN_DATAOUT,
+};
+
+struct mx2_nf_flags
+{
+ unsigned host_little_endian:1;
+ unsigned target_little_endian:1;
+ unsigned nand_readonly:1;
+ unsigned one_kb_sram:1;
+ unsigned hw_ecc_enabled:1;
+};
+
+struct mx2_nf_controller
+{
+ struct target *target;
+ enum mx_dataout_type optype;
+ enum mx_nf_finalize_action fin;
+ struct mx2_nf_flags flags;
+};
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/Makefile.am | 2 +
src/flash/nand/driver.c | 2 +
src/flash/nand/mx2.c | 776 ++++++++++++++++++++++++++++++++++++++++++++
src/flash/nand/mx2.h | 120 +++++++
4 files changed, 900 insertions(+), 0 deletions(-)
create mode 100644 src/flash/nand/mx2.c
create mode 100644 src/flash/nand/mx2.h
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2010-05-19 07:37:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8465e9944291a03a216fa15e0d7ed6eb9d44ba92 (commit)
via b80d0501b66002cba1b3bc97a027d4f79932f20d (commit)
from c86d7bdad4418f4fc3d81a68398187c6480316fa (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 8465e9944291a03a216fa15e0d7ed6eb9d44ba92
Author: Gary Carlson <gca...@ca...>
Date: Tue May 18 20:59:07 2010 -0700
reset: fix reset halt bug
I was finally able to figure out the cause of this problem. There are two
parts to the patch. The first patch modifies the configuration file I
originally generated for the Atmel AT91SAM9G20 board and achieves the
following:
+++ Splits the reset-init handler into a reset-start handler for some of the
initial configuration activities and keeps the remainder in the reset-init
handler as was the case before. This was the real issue that was causing
the timing problems I identified before. This solution was confirmed with
an o-scope on actual target hardware.
+++ Adds a new instruction in the reset-start handler to disable fast memory
accesses in the reset-start handler. When the target jtag clock is started
out at 2 kHz during system clock initialization, memory writes (i.e.
register write to enable external reset pin -- basically to RSTC_MR) are
naturally slow and cause GDB keep-alive issues (refer to PATCH 2/2 for
additional fixes).
+++ Modifies the configuration file to use srst_only reset action. The
reset-start/reset-init handler split also now allows the correct behavior to
be used in the configuration file (previously had to use both SRST and TRST
even though only SRST is actually used and connected on the evaluation
board).
+++ Adds external NandFlash configuration support to take advantage of flash
driver added earlier. Doesn't fix any bugs but adds functionality that was
marked as TBD before and thrown in when I did other work on the
configuration file.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index c3eb952..b50e8c8 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -13,16 +13,15 @@
# the AT91SAM9260 and shares the same tap ID as it.
set _CHIPNAME at91sam9g20
+set _FLASHTYPE nandflash_cs3
set _ENDIAN little
set _CPUTAPID 0x0792603f
-# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. In theory this script
-# therefore should require "srst_only". With some J-Link debuggers at least, "srst_only" causes a temporary USB
-# communication fault. This appears to be more likely attributed to an internal proprietary firmware quirk inside the
-# dongle itself. Using "trst_and_srst" works fine, however. So if you can't beat them -- join them. If you are using
-# something other the a J-Link dongle you may be able to change this back to "srst_only".
+# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore
+# the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is
+# added to the board to connect the trst signal, then this parameter may need to be changed.
-reset_config trst_and_srst
+reset_config srst_only
# Set up the CPU and generate a new jtag tap for AT91SAM9G20.
@@ -55,10 +54,16 @@ $_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-a
# an event handler where these special activities can take place.
scan_chain
-$_TARGETNAME configure -event reset-init {at91sam9g20_init}
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
# NandFlash configuration and definition
-# Future TBD
+
+nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
proc read_register {register} {
set result ""
@@ -66,7 +71,22 @@ proc read_register {register} {
return $result(0)
}
-proc at91sam9g20_init { } {
+proc at91sam9g20_reset_start { } {
+
+ # Make sure that the the jtag is running slow, since there are a number of different ways the board
+ # can be configured coming into this state that can cause communication problems with the jtag
+ # adapter. Also since this call can be made following a "reset init" where fast memory accesses
+ # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
+ # jtag speed without causing GDB keep alive problem.
+
+ arm7_9 fast_memory_access disable
+ adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
+ halt # Make sure processor is halted, or error will result in following steps.
+ wait_halt 10000
+ mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
+}
+
+proc at91sam9g20_reset_init { } {
# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
# a number of steps that must be carefully performed. The process outline below follows the
@@ -77,9 +97,6 @@ proc at91sam9g20_init { } {
# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
- adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
- halt # Make sure processor is halted, or error will result in following steps.
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
@@ -114,9 +131,10 @@ proc at91sam9g20_init { } {
adapter_khz 0
- # Enable faster DCC downloads.
+ # Enable faster DCC downloads and memory accesses.
arm7_9 dcc_downloads enable
+ arm7_9 fast_memory_access enable
# To be able to use external SDRAM, several peripheral configuration registers must
# be modified. The first change is made to PIO_ASR to select peripheral functions
@@ -134,16 +152,34 @@ proc at91sam9g20_init { } {
# The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics
# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
- # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
-
- mww 0xffffec30 0x00020002
- mww 0xffffec34 0x04040404
- mww 0xffffec38 0x00070007
- mww 0xffffec3c 0x00030003
-
- # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
-
-# nand probe 0
+ # a number of registers. The first step involves setting up the general I/O pins on the processor
+ # to be able to interface and support the external memory.
+
+ mww 0xfffffc10 0x00000010 # PMC_PCER : enable PIOC clock
+ mww 0xfffff800 0x00006000 # PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+ mww 0xfffff810 0x00004000 # PIOC_OER : enable output on 14
+ mww 0xfffff814 0x00002000 # PIOC_ODR : disable output on 13
+ mww 0xfffff830 0x00004000 # PIOC_SODR : set 14 to disable NAND
+
+ # The exact physical timing characteristics for the memory type used on the current board
+ # (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3,
+ # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers
+ # is a little tedious to do here. If you have questions about how to do this, Atmel has
+ # a decent application note #6255B that covers this process.
+
+ mww 0xffffec30 0x00020002 # SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+ mww 0xffffec34 0x04040404 # SMC_PULSE3 : 4 clock cycle pulse for all signals
+ mww 0xffffec38 0x00070006 # SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+ mww 0xffffec3C 0x00020003 # SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
+ mww 0xffffe800 0x00000001 # ECC_CR : reset the ECC parity registers
+ mww 0xffffe804 0x00000002 # ECC_MR : page size is 2112 words (word is 8 bits)
+
+ # Identify NandFlash bank 0.
+
+ nand probe nandflash_cs3
+
+ # The AT91SAM9G20-EK evaluation board has build-in serial data flash also.
# Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
commit b80d0501b66002cba1b3bc97a027d4f79932f20d
Author: Gary Carlson <gca...@ca...>
Date: Tue May 18 20:59:00 2010 -0700
target: slow targets could cause GDB to time out
This second half of the patch is proposed to clean up some GDB keep alive
issues on arm7_9 targets that start up with very slow clocks. If an attempt
is made to write to key registers on the processor with a slow jtag speed,
GDB timeout warnings appear on the console (at least mine) when "reset halt"
or "reset init" commands are issued from the gdb client:
*** BEFORE PATCH ***
(gdb) monitor reset init
fast memory access is disabled
2 kHz
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1026). Workaround: increase "set remotetimeout" in GDB
JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f (mfg: 0x01f, part:
0x7926, ver: 0x0)
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1027). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1006). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1006). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1006). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1004). Workaround: increase "set remotetimeout" in GDB
RCLK - adaptive
dcc downloads are enabled
fast memory access is enabled
NAND flash device 'NAND 256MiB 3,3V 8-bit' found
(gdb)
I added additional keep alive steps in areas that troubleshooting revealed
were causing problems. I only did this however for non-fast write memory
accesses. I don't think most people would be using fast memory accesses to
write to memory when the jtag and system clocks are slow anyway.
If you disagree with my feeling, think there is a more elegant way to handle
the problem, or think the patch will cause other unforeseen problems with
other targets, let me know. As you can see below, the patch does eliminate
the problem on my development station and I suspect that it will benefit
others.
*** AFTER PATCH ***
(gdb) monitor reset init
fast memory access is disabled
2 kHz
JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f (mfg: 0x01f, part:
0x7926, ver: 0x0)
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
RCLK - adaptive
dcc downloads are enabled
fast memory access is enabled
NAND flash device 'NAND 256MiB 3,3V 8-bit' found
(gdb)
Gary Carlson
Gary Carlson, MSEE
Principal Engineer
Carlson-Minot Inc.
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index ac18b37..abe0c2f 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2463,7 +2463,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
+ {
retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
@@ -2499,7 +2512,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
+ {
retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
@@ -2534,7 +2560,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
- retval = arm7_9_execute_sys_speed(target);
+ {
+ retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/target/arm7_9_common.c | 41 ++++++++++++++++++++-
tcl/board/at91sam9g20-ek.cfg | 82 ++++++++++++++++++++++++++++++------------
2 files changed, 99 insertions(+), 24 deletions(-)
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From: Øyvind H. <go...@us...> - 2010-05-18 12:48:01
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from e804a34a632345effd706872605a0cc382a4da70 (commit)
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- Log -----------------------------------------------------------------
commit c86d7bdad4418f4fc3d81a68398187c6480316fa
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue May 18 12:34:12 2010 +0200
jim: fix bug in tcl "puts"
tcl "puts" didn't work because the logging code sensored strings
that did not include a '\n'. The correct thing is to sensor
empty strings, which are used to keep gdb connection alive.
The tcl "puts" code broke apart strings which do contain '\n' in
order to implement the -nonewline argument, which is how it
got hurt by the bug in log.c
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/helper/log.c b/src/helper/log.c
index 7ace930..da227bd 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -139,7 +139,7 @@ static void log_puts(enum log_levels level, const char *file, int line, const ch
if (f != NULL)
file = f + 1;
- if (strchr(string, '\n') != NULL)
+ if (strlen(string) > 0)
{
if (debug_level >= LOG_LVL_DEBUG)
{
@@ -163,17 +163,12 @@ static void log_puts(enum log_levels level, const char *file, int line, const ch
{
/* if we are using gdb through pipes then we do not want any output
* to the pipe otherwise we get repeated strings */
- if (strcmp(string, "\n") != 0)
- {
- /* print human readable output - but skip empty lines */
- fprintf(log_output, "%s%s",
- (level > LOG_LVL_USER)?log_strings[level + 1]:"", string);
- }
+ fprintf(log_output, "%s%s",
+ (level > LOG_LVL_USER)?log_strings[level + 1]:"", string);
}
} else
{
- /* only entire lines are logged. Otherwise it's
- * single chars intended for the log callbacks. */
+ /* Empty strings are sent to log callbacks to keep e.g. gdbserver alive, here we do nothing. */
}
fflush(log_output);
-----------------------------------------------------------------------
Summary of changes:
src/helper/log.c | 13 ++++---------
1 files changed, 4 insertions(+), 9 deletions(-)
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From: Øyvind H. <go...@us...> - 2010-05-18 12:32:58
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e804a34a632345effd706872605a0cc382a4da70 (commit)
from e92b203a768731fdbc1499c59b0a60e1a2b290a7 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit e804a34a632345effd706872605a0cc382a4da70
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue May 18 12:10:24 2010 +0200
zy1000: fix false positive warning about unitialized local variable
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index b3f94e5..442a09f 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -181,7 +181,7 @@ void zy1000_reset(int trst, int srst)
(!srst && !trst && (jtag_get_reset_config() & RESET_TRST_PULLS_SRST)))
{
bool first = true;
- long long start;
+ long long start = 0;
long total = 0;
for (;;)
{
-----------------------------------------------------------------------
Summary of changes:
src/jtag/zy1000/zy1000.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
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From: Øyvind H. <go...@us...> - 2010-05-18 11:48:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e92b203a768731fdbc1499c59b0a60e1a2b290a7 (commit)
from dc464ad88e7b7c5e0014a1784edcdb2fdcb448fd (commit)
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- Log -----------------------------------------------------------------
commit e92b203a768731fdbc1499c59b0a60e1a2b290a7
Author: Marc Pignat <mar...@he...>
Date: Tue May 18 11:38:01 2010 +0200
at91rm9200 : reset_config should go to the board config file
Let other boards do other things with srst and trst.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg
index 402ed05..f484fde 100644
--- a/tcl/board/at91rm9200-dk.cfg
+++ b/tcl/board/at91rm9200-dk.cfg
@@ -5,6 +5,9 @@
#
# It has atmel at91rm9200 chip.
source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg
index e2972d7..a9cda19 100644
--- a/tcl/target/at91rm9200.cfg
+++ b/tcl/target/at91rm9200.cfg
@@ -1,8 +1,6 @@
# Atmel AT91rm9200
# http://atmel.com/products/at91/
-reset_config trst_and_srst
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
-----------------------------------------------------------------------
Summary of changes:
tcl/board/at91rm9200-dk.cfg | 3 +++
tcl/target/at91rm9200.cfg | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
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Main OpenOCD repository
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From: Øyvind H. <go...@us...> - 2010-05-18 09:25:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via dc464ad88e7b7c5e0014a1784edcdb2fdcb448fd (commit)
from fafed75d9831c8038c5504fc94e941f0ee9770e5 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit dc464ad88e7b7c5e0014a1784edcdb2fdcb448fd
Author: Jon Povey <jon...@ra...>
Date: Mon May 17 16:16:22 2010 +0900
NAND/davinci: Fix segfault for hwecc4_infix reads
Page reads using hwecc4_infix layout segfaulted for check_bad_blocks because
the read assumed a valid data buffer, which check_bad_blocks does not use
(it only passes a 6 byte buffer for the start of OOB).
This version copes with undersized or missing data or oob buffers and uses
random read commands within the page to skip unwanted areas of data/OOB for
speed.
NOTE: Running check_bad_blocks with this layout will be reading infix
OOB locations, not manufacturer bad block markers. This means that if you
check blocks written in infix layout they will appear good, but manufacturer-
marked bad blocks may also appear good.
If you want to scan for manufactuer-marked bad blocks, you need to enable
raw_access before running check_bad_blocks, or use the non-infix layout.
Signed-off-by: Jon Povey <jon...@ra...>
CC: David Brownell <dbr...@us...>
diff --git a/src/flash/nand/davinci.c b/src/flash/nand/davinci.c
index 96cbfea..90219c6 100644
--- a/src/flash/nand/davinci.c
+++ b/src/flash/nand/davinci.c
@@ -338,6 +338,27 @@ static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_
target_write_u8(target, info->addr, page >> 24);
}
+static int davinci_seek_column(struct nand_device *nand, uint16_t column)
+{
+ struct davinci_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+
+ /* Random read, we must have issued a page read already */
+ target_write_u8(target, info->cmd, NAND_CMD_RNDOUT);
+
+ target_write_u8(target, info->addr, column);
+
+ if (nand->page_size > 512) {
+ target_write_u8(target, info->addr, column >> 8);
+ target_write_u8(target, info->cmd, NAND_CMD_RNDOUTSTART);
+ }
+
+ if (!davinci_nand_ready(nand, 100))
+ return ERROR_NAND_OPERATION_TIMEOUT;
+
+ return ERROR_OK;
+}
+
static int davinci_writepage_tail(struct nand_device *nand,
uint8_t *oob, uint32_t oob_size)
{
@@ -599,6 +620,10 @@ static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
+ int read_size;
+ int want_col, at_col;
+ int ret;
+
davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
/* large page devices need a start command */
@@ -610,18 +635,43 @@ static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
/* NOTE: not bothering to compute and use ECC data for now */
- do {
- /* write 512 bytes */
- davinci_read_block_data(nand, data, 512);
- data += 512;
- data_size -= 512;
-
- /* read this "out-of-band" data -- infix */
- davinci_read_block_data(nand, oob, 16);
- oob += 16;
- oob_size -= 16;
- } while (data_size);
-
+ want_col = 0;
+ at_col = 0;
+ while ((data && data_size) || (oob && oob_size)) {
+
+ if (data && data_size) {
+ if (want_col != at_col) {
+ /* Reads are slow, so seek past them when we can */
+ ret = davinci_seek_column(nand, want_col);
+ if (ret != ERROR_OK)
+ return ret;
+ at_col = want_col;
+ }
+ /* read 512 bytes or data_size, whichever is smaller*/
+ read_size = data_size > 512 ? 512 : data_size;
+ davinci_read_block_data(nand, data, read_size);
+ data += read_size;
+ data_size -= read_size;
+ at_col += read_size;
+ }
+ want_col += 512;
+
+ if (oob && oob_size) {
+ if (want_col != at_col) {
+ ret = davinci_seek_column(nand, want_col);
+ if (ret != ERROR_OK)
+ return ret;
+ at_col = want_col;
+ }
+ /* read this "out-of-band" data -- infix */
+ read_size = oob_size > 16 ? 16 : oob_size;
+ davinci_read_block_data(nand, oob, read_size);
+ oob += read_size;
+ oob_size -= read_size;
+ at_col += read_size;
+ }
+ want_col += 16;
+ }
return ERROR_OK;
}
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/davinci.c | 74 ++++++++++++++++++++++++++++++++++++++-------
1 files changed, 62 insertions(+), 12 deletions(-)
hooks/post-receive
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From: Øyvind H. <go...@us...> - 2010-05-18 09:23:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via fafed75d9831c8038c5504fc94e941f0ee9770e5 (commit)
from 3ecc191b361d913d3bdf156568454de57f093aee (commit)
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- Log -----------------------------------------------------------------
commit fafed75d9831c8038c5504fc94e941f0ee9770e5
Author: Jon Povey <jon...@ra...>
Date: Mon May 17 16:15:35 2010 +0900
NAND: catch read errors when building BBT
nand_build_bbt() was ignoring the return value from nand_read_page() and
blindly continuing.
It now passes the return value up to the caller if the read fails.
Signed-off-by: Jon Povey <jon...@ra...>
diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
index 44b13ce..b3220e2 100644
--- a/src/flash/nand/core.c
+++ b/src/flash/nand/core.c
@@ -226,6 +226,7 @@ int nand_build_bbt(struct nand_device *nand, int first, int last)
int i;
int pages_per_block = (nand->erase_size / nand->page_size);
uint8_t oob[6];
+ int ret;
if ((first < 0) || (first >= nand->num_blocks))
first = 0;
@@ -236,7 +237,9 @@ int nand_build_bbt(struct nand_device *nand, int first, int last)
page = first * pages_per_block;
for (i = first; i <= last; i++)
{
- nand_read_page(nand, page, NULL, 0, oob, 6);
+ ret = nand_read_page(nand, page, NULL, 0, oob, 6);
+ if (ret != ERROR_OK)
+ return ret;
if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
|| (((nand->page_size == 512) && (oob[5] != 0xff)) ||
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/core.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
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From: Spencer O. <nt...@us...> - 2010-05-17 11:19:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 5fd1c2db9ad43cc893d6287549262f82e6932e90 (commit)
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- Log -----------------------------------------------------------------
commit 3ecc191b361d913d3bdf156568454de57f093aee
Author: Spencer Oliver <nt...@us...>
Date: Mon May 17 10:17:21 2010 +0100
gdbserver: gdb cmds returning failure on success
The gdb_memory_map cmd for example fell through and returned
ERROR_COMMAND_SYNTAX_ERROR on success - behaviour is now as expected.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 5b4fb7a..a84c618 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2503,26 +2503,29 @@ COMMAND_HANDLER(handle_gdb_port_command)
COMMAND_HANDLER(handle_gdb_memory_map_command)
{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_use_memory_map);
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- return ERROR_COMMAND_SYNTAX_ERROR;
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_use_memory_map);
+ return ERROR_OK;
}
COMMAND_HANDLER(handle_gdb_flash_program_command)
{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_flash_program);
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- return ERROR_COMMAND_SYNTAX_ERROR;
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_flash_program);
+ return ERROR_OK;
}
COMMAND_HANDLER(handle_gdb_report_data_abort_command)
{
- if (CMD_ARGC == 1)
- COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_report_data_abort);
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- return ERROR_COMMAND_SYNTAX_ERROR;
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], gdb_report_data_abort);
+ return ERROR_OK;
}
/* gdb_breakpoint_override */
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 21 ++++++++++++---------
1 files changed, 12 insertions(+), 9 deletions(-)
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Main OpenOCD repository
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From: Øyvind H. <go...@us...> - 2010-05-16 13:55:57
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- Log -----------------------------------------------------------------
commit 5fd1c2db9ad43cc893d6287549262f82e6932e90
Author: Jon Povey <jon...@ra...>
Date: Thu May 13 12:20:20 2010 +0900
Change kb/s to KiB/s in messages about kibibytes
Change download rate messages about kibibytes from "kb/s" to "KiB/s" units.
See: http://en.wikipedia.org/wiki/Data_rate_units
Signed-off-by: Jon Povey <jon...@ra...>
diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c
index 86dbd67..1272bf6 100644
--- a/src/flash/nand/tcl.c
+++ b/src/flash/nand/tcl.c
@@ -309,7 +309,7 @@ COMMAND_HANDLER(handle_nand_write_command)
if (nand_fileio_finish(&s))
{
command_print(CMD_CTX, "wrote file %s to NAND flash %s up to "
- "offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
+ "offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)",
CMD_ARGV[1], CMD_ARGV[0], s.address, duration_elapsed(&s.bench),
duration_kbps(&s.bench, total_bytes));
}
@@ -369,7 +369,7 @@ COMMAND_HANDLER(handle_nand_verify_command)
if (nand_fileio_finish(&file) == ERROR_OK)
{
command_print(CMD_CTX, "verified file %s in NAND flash %s "
- "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
+ "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)",
CMD_ARGV[1], CMD_ARGV[0], dev.address, duration_elapsed(&file.bench),
duration_kbps(&file.bench, dev.size));
}
@@ -409,7 +409,7 @@ COMMAND_HANDLER(handle_nand_dump_command)
if (nand_fileio_finish(&s) == ERROR_OK)
{
- command_print(CMD_CTX, "dumped %ld bytes in %fs (%0.3f kb/s)",
+ command_print(CMD_CTX, "dumped %ld bytes in %fs (%0.3f KiB/s)",
(long)s.fileio.size, duration_elapsed(&s.bench),
duration_kbps(&s.bench, s.fileio.size));
}
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index af655c6..80d9a27 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -263,7 +263,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX, "erased address 0x%8.8x (length %i)"
- " in %fs (%0.3f kb/s)", address, length,
+ " in %fs (%0.3f KiB/s)", address, length,
duration_elapsed(&bench), duration_kbps(&bench, length));
}
@@ -448,7 +448,7 @@ COMMAND_HANDLER(handle_flash_write_image_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX, "wrote %" PRIu32 " bytes from file %s "
- "in %fs (%0.3f kb/s)", written, CMD_ARGV[0],
+ "in %fs (%0.3f KiB/s)", written, CMD_ARGV[0],
duration_elapsed(&bench), duration_kbps(&bench, written));
}
@@ -582,7 +582,7 @@ COMMAND_HANDLER(handle_flash_fill_command)
if (duration_measure(&bench) == ERROR_OK)
{
command_print(CMD_CTX, "wrote %" PRIu32 " bytes to 0x%8.8" PRIx32
- " in %fs (%0.3f kb/s)", wrote, address,
+ " in %fs (%0.3f KiB/s)", wrote, address,
duration_elapsed(&bench), duration_kbps(&bench, wrote));
}
@@ -634,7 +634,7 @@ COMMAND_HANDLER(handle_flash_write_bank_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX, "wrote %ld bytes from file %s to flash bank %u"
- " at offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
+ " at offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)",
(long)fileio.size, CMD_ARGV[1], p->bank_number, offset,
duration_elapsed(&bench), duration_kbps(&bench, fileio.size));
}
diff --git a/src/target/target.c b/src/target/target.c
index 37e515a..c8c1012 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2560,7 +2560,7 @@ COMMAND_HANDLER(handle_load_image_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX, "downloaded %" PRIu32 " bytes "
- "in %fs (%0.3f kb/s)", image_size,
+ "in %fs (%0.3f KiB/s)", image_size,
duration_elapsed(&bench), duration_kbps(&bench, image_size));
}
@@ -2626,7 +2626,7 @@ COMMAND_HANDLER(handle_dump_image_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX,
- "dumped %ld bytes in %fs (%0.3f kb/s)", (long)fileio.size,
+ "dumped %ld bytes in %fs (%0.3f KiB/s)", (long)fileio.size,
duration_elapsed(&bench), duration_kbps(&bench, fileio.size));
}
@@ -2769,7 +2769,7 @@ done:
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX, "verified %" PRIu32 " bytes "
- "in %fs (%0.3f kb/s)", image_size,
+ "in %fs (%0.3f KiB/s)", image_size,
duration_elapsed(&bench), duration_kbps(&bench, image_size));
}
@@ -4949,7 +4949,7 @@ COMMAND_HANDLER(handle_fast_load_image_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX, "Loaded %" PRIu32 " bytes "
- "in %fs (%0.3f kb/s)", image_size,
+ "in %fs (%0.3f KiB/s)", image_size,
duration_elapsed(&bench), duration_kbps(&bench, image_size));
command_print(CMD_CTX,
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/tcl.c | 6 +++---
src/flash/nor/tcl.c | 8 ++++----
src/target/target.c | 8 ++++----
3 files changed, 11 insertions(+), 11 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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