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From: Nathan M. <npm...@gm...> - 2025-11-11 19:10:29
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Hello all, I'm trying to work with a platform targeting the MIMXRT533, and I'm coming up against a perceived limitation of OpenOCD that I wanted to get advice on. I'm trying to enable debug mode which requires writing to the command and status word (CSW, base address 0x4010f000) register with CSW[RESYNCH_REQ] = 1 and CSW[CHIP_RESET_REQ] = 1 which I do with mww 0x4010f000 0x21.This causes the device to reset as expected, and then there are other steps in the process that need to be executed according to the datasheet to fully enable debug mode. However, since this first register write causes a reset that OpenOCD does not expect, I get: "Error: Failed to write memory at 0x4010f004" Which indicates that OpenOCD is trying to access some memory beyond what I need (I assume for caching purposes?). This fails since the device is in reset. It seems that OpenOCD needs a special memory write command that expects a subsequent hardware reset to occur for this kind of use case. This isn't the first time I've had this issue. I had a similar problem when trying to define a custom NVIC reset process for a DA1469x platform. Is there a feature already in OpenOCD that I'm missing that could accommodate this use case, or would that require a new feature to be added? Thanks in advance, Nathan |