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[PATCH]: cd0ac18f12 target: align switch and case statements
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From: <ge...@op...> - 2025-07-26 17:40:11
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This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9051 -- gerrit commit cd0ac18f12123df6f627f25031e69fe6faed9717 Author: Antonio Borneo <bor...@gm...> Date: Sat Jul 26 15:46:26 2025 +0200 target: align switch and case statements The coding style requires the 'case' to be at the same indentation level of its 'switch' statement. Align the code accordingly. While there: - add space around the operators; - drop useless empty line. Skip all riscv code, as it is going to be updated soon from the external fork. No changes are reported by git log -p -w --ignore-blank-lines --patience Change-Id: I2691dfdd2b6734143e14160b46183623e9773539 Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 101cb14408..87b02fea32 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -613,22 +613,22 @@ static int aarch64_restore_one(struct target *target, bool current, * kill the return address */ switch (arm->core_state) { - case ARM_STATE_ARM: - resume_pc &= 0xFFFFFFFC; - break; - case ARM_STATE_AARCH64: - resume_pc &= 0xFFFFFFFFFFFFFFFCULL; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - resume_pc |= 0x1; - break; - case ARM_STATE_JAZELLE: - LOG_ERROR("How do I resume into Jazelle state??"); - return ERROR_FAIL; + case ARM_STATE_ARM: + resume_pc &= 0xFFFFFFFC; + break; + case ARM_STATE_AARCH64: + resume_pc &= 0xFFFFFFFFFFFFFFFCULL; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + resume_pc |= 0x1; + break; + case ARM_STATE_JAZELLE: + LOG_ERROR("How do I resume into Jazelle state??"); + return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc); buf_set_u64(arm->pc->value, 0, 64, resume_pc); @@ -3027,14 +3027,14 @@ COMMAND_HANDLER(aarch64_handle_disassemble_command) target_addr_t address; switch (CMD_ARGC) { - case 2: - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); - /* FALL THROUGH */ - case 1: - COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 2: + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); + /* FALL THROUGH */ + case 1: + COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return a64_disassemble(CMD, target, address, count); diff --git a/src/target/arc.c b/src/target/arc.c index f2482c25ef..638e22099e 100644 --- a/src/target/arc.c +++ b/src/target/arc.c @@ -1892,18 +1892,18 @@ static int arc_set_watchpoint(struct target *target, int enable = AP_AC_TT_DISABLE; switch (watchpoint->rw) { - case WPT_READ: - enable = AP_AC_TT_READ; - break; - case WPT_WRITE: - enable = AP_AC_TT_WRITE; - break; - case WPT_ACCESS: - enable = AP_AC_TT_READWRITE; - break; - default: - LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access"); - return ERROR_FAIL; + case WPT_READ: + enable = AP_AC_TT_READ; + break; + case WPT_WRITE: + enable = AP_AC_TT_WRITE; + break; + case WPT_ACCESS: + enable = AP_AC_TT_READWRITE; + break; + default: + LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access"); + return ERROR_FAIL; } int retval = arc_configure_actionpoint(target, wp_num, diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c index bf8a8aa28b..2e42398d28 100644 --- a/src/target/arc_cmd.c +++ b/src/target/arc_cmd.c @@ -709,29 +709,29 @@ COMMAND_HANDLER(arc_handle_get_reg_field) int retval = arc_reg_get_field(target, reg_name, field_name, &value); switch (retval) { - case ERROR_OK: - break; - case ERROR_ARC_REGISTER_NOT_FOUND: - command_print(CMD, - "Register `%s' has not been found.", reg_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - case ERROR_ARC_REGISTER_IS_NOT_STRUCT: - command_print(CMD, - "Register `%s' must have 'struct' type.", reg_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - case ERROR_ARC_REGISTER_FIELD_NOT_FOUND: - command_print(CMD, - "Field `%s' has not been found in register `%s'.", - field_name, reg_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - case ERROR_ARC_FIELD_IS_NOT_BITFIELD: - command_print(CMD, - "Field `%s' is not a 'bitfield' field in a structure.", - field_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - default: - /* Pass through other errors. */ - return retval; + case ERROR_OK: + break; + case ERROR_ARC_REGISTER_NOT_FOUND: + command_print(CMD, + "Register `%s' has not been found.", reg_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + case ERROR_ARC_REGISTER_IS_NOT_STRUCT: + command_print(CMD, + "Register `%s' must have 'struct' type.", reg_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + case ERROR_ARC_REGISTER_FIELD_NOT_FOUND: + command_print(CMD, + "Field `%s' has not been found in register `%s'.", + field_name, reg_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + case ERROR_ARC_FIELD_IS_NOT_BITFIELD: + command_print(CMD, + "Field `%s' is not a 'bitfield' field in a structure.", + field_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + default: + /* Pass through other errors. */ + return retval; } command_print(CMD, "0x%" PRIx32, value); diff --git a/src/target/arm11.c b/src/target/arm11.c index 8ba0812d8d..6b88e69c44 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -414,19 +414,19 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, bool current, * kill the return address */ switch (arm11->arm.core_state) { - case ARM_STATE_ARM: - address &= 0xFFFFFFFC; - break; - case ARM_STATE_THUMB: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - address |= 0x1; - break; - - /* catch-all for JAZELLE and THUMB_EE */ - default: - break; + case ARM_STATE_ARM: + address &= 0xFFFFFFFC; + break; + case ARM_STATE_THUMB: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + address |= 0x1; + break; + + /* catch-all for JAZELLE and THUMB_EE */ + default: + break; } buf_set_u32(value, 0, 32, address); @@ -819,44 +819,44 @@ static int arm11_read_memory_inner(struct target *target, return retval; switch (size) { - case 1: - arm11->arm.core_cache->reg_list[1].dirty = true; + case 1: + arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) { - /* ldrb r1, [r0], #1 */ - /* ldrb r1, [r0] */ - CHECK_RETVAL(arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)); + for (size_t i = 0; i < count; i++) { + /* ldrb r1, [r0], #1 */ + /* ldrb r1, [r0] */ + CHECK_RETVAL(arm11_run_instr_no_data1(arm11, + !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)); - uint32_t res; - /* MCR p14,0,R1,c0,c5,0 */ - CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); + uint32_t res; + /* MCR p14,0,R1,c0,c5,0 */ + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); - *buffer++ = res; - } + *buffer++ = res; + } - break; + break; - case 2: - arm11->arm.core_cache->reg_list[1].dirty = true; + case 2: + arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) { - /* ldrh r1, [r0], #2 */ - CHECK_RETVAL(arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)); + for (size_t i = 0; i < count; i++) { + /* ldrh r1, [r0], #2 */ + CHECK_RETVAL(arm11_run_instr_no_data1(arm11, + !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)); - uint32_t res; + uint32_t res; - /* MCR p14,0,R1,c0,c5,0 */ - CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); + /* MCR p14,0,R1,c0,c5,0 */ + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); - uint16_t svalue = res; - memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); - } + uint16_t svalue = res; + memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); + } - break; + break; - case 4: + case 4: { uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ @@ -925,52 +925,52 @@ static int arm11_write_memory_inner(struct target *target, bool burst = arm11->memwrite_burst && (count > 1); switch (size) { - case 1: - arm11->arm.core_cache->reg_list[1].dirty = true; - - for (size_t i = 0; i < count; i++) { - /* load r1 from DCC with byte data */ - /* MRC p14,0,r1,c0,c5,0 */ - retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); - if (retval != ERROR_OK) - return retval; - - /* write r1 to memory */ - /* strb r1, [r0], #1 */ - /* strb r1, [r0] */ - retval = arm11_run_instr_no_data1(arm11, - !no_increment ? 0xe4c01001 : 0xe5c01000); - if (retval != ERROR_OK) - return retval; - } + case 1: + arm11->arm.core_cache->reg_list[1].dirty = true; - break; + for (size_t i = 0; i < count; i++) { + /* load r1 from DCC with byte data */ + /* MRC p14,0,r1,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); + if (retval != ERROR_OK) + return retval; - case 2: - arm11->arm.core_cache->reg_list[1].dirty = true; - - for (size_t i = 0; i < count; i++) { - uint16_t value; - memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); - - /* load r1 from DCC with halfword data */ - /* MRC p14,0,r1,c0,c5,0 */ - retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); - if (retval != ERROR_OK) - return retval; - - /* write r1 to memory */ - /* strh r1, [r0], #2 */ - /* strh r1, [r0] */ - retval = arm11_run_instr_no_data1(arm11, - !no_increment ? 0xe0c010b2 : 0xe1c010b0); - if (retval != ERROR_OK) - return retval; - } + /* write r1 to memory */ + /* strb r1, [r0], #1 */ + /* strb r1, [r0] */ + retval = arm11_run_instr_no_data1(arm11, + !no_increment ? 0xe4c01001 : 0xe5c01000); + if (retval != ERROR_OK) + return retval; + } - break; + break; + + case 2: + arm11->arm.core_cache->reg_list[1].dirty = true; - case 4: + for (size_t i = 0; i < count; i++) { + uint16_t value; + memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); + + /* load r1 from DCC with halfword data */ + /* MRC p14,0,r1,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); + if (retval != ERROR_OK) + return retval; + + /* write r1 to memory */ + /* strh r1, [r0], #2 */ + /* strh r1, [r0] */ + retval = arm11_run_instr_no_data1(arm11, + !no_increment ? 0xe0c010b2 : 0xe1c010b0); + if (retval != ERROR_OK) + return retval; + } + + break; + + case 4: { /* stream word data through DCC directly to memory */ /* increment: STC p14,c5,[R0],#4 */ @@ -1159,34 +1159,34 @@ static int arm11_examine(struct target *target) /* assume the manufacturer id is ok; check the part # */ switch ((device_id >> 12) & 0xFFFF) { - case 0x7B36: - type = "ARM1136"; - break; - case 0x7B37: - type = "ARM11 MPCore"; - break; - case 0x7B56: - type = "ARM1156"; - break; - case 0x7B76: - arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT; - /* NOTE: could default arm11->hardware_step to true */ - type = "ARM1176"; - break; - default: - LOG_ERROR("unexpected ARM11 ID code"); - return ERROR_FAIL; + case 0x7B36: + type = "ARM1136"; + break; + case 0x7B37: + type = "ARM11 MPCore"; + break; + case 0x7B56: + type = "ARM1156"; + break; + case 0x7B76: + arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT; + /* NOTE: could default arm11->hardware_step to true */ + type = "ARM1176"; + break; + default: + LOG_ERROR("unexpected ARM11 ID code"); + return ERROR_FAIL; } LOG_INFO("found %s", type); /* unlikely this could ever fail, but ... */ switch ((didr >> 16) & 0x0F) { - case ARM11_DEBUG_V6: - case ARM11_DEBUG_V61: /* supports security extensions */ - break; - default: - LOG_ERROR("Only ARM v6 and v6.1 debug supported."); - return ERROR_FAIL; + case ARM11_DEBUG_V6: + case ARM11_DEBUG_V61: /* supports security extensions */ + break; + default: + LOG_ERROR("Only ARM v6 and v6.1 debug supported."); + return ERROR_FAIL; } arm11->brp = ((didr >> 24) & 0x0F) + 1; @@ -1250,13 +1250,13 @@ COMMAND_HANDLER(arm11_handle_vcr) struct arm11_common *arm11 = target_to_arm11(target); switch (CMD_ARGC) { - case 0: - break; - case 1: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr); diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 4c7211365b..4c2fedaeb2 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -85,30 +85,30 @@ static const char *arm11_ir_to_string(uint8_t ir) const char *s = "unknown"; switch (ir) { - case ARM11_EXTEST: - s = "EXTEST"; - break; - case ARM11_SCAN_N: - s = "SCAN_N"; - break; - case ARM11_RESTART: - s = "RESTART"; - break; - case ARM11_HALT: - s = "HALT"; - break; - case ARM11_INTEST: - s = "INTEST"; - break; - case ARM11_ITRSEL: - s = "ITRSEL"; - break; - case ARM11_IDCODE: - s = "IDCODE"; - break; - case ARM11_BYPASS: - s = "BYPASS"; - break; + case ARM11_EXTEST: + s = "EXTEST"; + break; + case ARM11_SCAN_N: + s = "SCAN_N"; + break; + case ARM11_RESTART: + s = "RESTART"; + break; + case ARM11_HALT: + s = "HALT"; + break; + case ARM11_INTEST: + s = "INTEST"; + break; + case ARM11_ITRSEL: + s = "ITRSEL"; + break; + case ARM11_IDCODE: + s = "IDCODE"; + break; + case ARM11_BYPASS: + s = "BYPASS"; + break; } return s; } @@ -1061,17 +1061,17 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, action[1].value = control; switch (index_t) { - case 0 ... 15: - action[0].address = ARM11_SC7_BVR0 + index_t; - action[1].address = ARM11_SC7_BCR0 + index_t; - break; - case 16 ... 32: - index_t -= 16; - action[0].address = ARM11_SC7_WVR0 + index_t; - action[1].address = ARM11_SC7_WCR0 + index_t; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + action[0].address = ARM11_SC7_BVR0 + index_t; + action[1].address = ARM11_SC7_BCR0 + index_t; + break; + case 16 ... 32: + index_t -= 16; + action[0].address = ARM11_SC7_WVR0 + index_t; + action[1].address = ARM11_SC7_WCR0 + index_t; + break; + default: + return ERROR_FAIL; } arm11->bpwp_n += 2; @@ -1090,15 +1090,15 @@ static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t) action[0].value = 0; switch (index_t) { - case 0 ... 15: - action[0].address = ARM11_SC7_BCR0 + index_t; - break; - case 16 ... 32: - index_t -= 16; - action[0].address = ARM11_SC7_WCR0 + index_t; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + action[0].address = ARM11_SC7_BCR0 + index_t; + break; + case 16 ... 32: + index_t -= 16; + action[0].address = ARM11_SC7_WCR0 + index_t; + break; + default: + return ERROR_FAIL; } arm11->bpwp_n += 1; diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index f67e02bdbd..06041f8432 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2138,18 +2138,49 @@ int arm7_9_read_memory(struct target *target, int j = 0; switch (size) { - case 4: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + case 4: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + if (last_reg <= thisrun_accesses) + last_reg = thisrun_accesses; + + arm7_9->load_word_regs(target, reg_list); + + /* fast memory reads are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) + retval = arm7_9_execute_fast_sys_speed(target); + else + retval = arm7_9_execute_sys_speed(target); + if (retval != ERROR_OK) + return retval; - if (last_reg <= thisrun_accesses) - last_reg = thisrun_accesses; + arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4); - arm7_9->load_word_regs(target, reg_list); + /* advance buffer, count number of accesses */ + buffer += thisrun_accesses * 4; + num_accesses += thisrun_accesses; + if ((j++ % 1024) == 0) + keep_alive(); + } + break; + case 2: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + arm7_9->load_hword_reg(target, i); /* fast memory reads are only safe when the target is running * from a sufficiently high clock (32 kHz is usually too slow) */ @@ -2160,81 +2191,50 @@ int arm7_9_read_memory(struct target *target, if (retval != ERROR_OK) return retval; - arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4); - - /* advance buffer, count number of accesses */ - buffer += thisrun_accesses * 4; - num_accesses += thisrun_accesses; - - if ((j++%1024) == 0) - keep_alive(); } - break; - case 2: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - arm7_9->load_hword_reg(target, i); - /* fast memory reads are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) - */ - if (arm7_9->fast_memory_access) - retval = arm7_9_execute_fast_sys_speed(target); - else - retval = arm7_9_execute_sys_speed(target); - if (retval != ERROR_OK) - return retval; - } - - arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2); + arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2); - /* advance buffer, count number of accesses */ - buffer += thisrun_accesses * 2; - num_accesses += thisrun_accesses; + /* advance buffer, count number of accesses */ + buffer += thisrun_accesses * 2; + num_accesses += thisrun_accesses; - if ((j++%1024) == 0) - keep_alive(); + if ((j++ % 1024) == 0) + keep_alive(); + } + break; + case 1: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + arm7_9->load_byte_reg(target, i); + /* fast memory reads are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) + retval = arm7_9_execute_fast_sys_speed(target); + else + retval = arm7_9_execute_sys_speed(target); + if (retval != ERROR_OK) + return retval; } - break; - case 1: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - arm7_9->load_byte_reg(target, i); - /* fast memory reads are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) - */ - if (arm7_9->fast_memory_access) - retval = arm7_9_execute_fast_sys_speed(target); - else - retval = arm7_9_execute_sys_speed(target); - if (retval != ERROR_OK) - return retval; - } - arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); + arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); - /* advance buffer, count number of accesses */ - buffer += thisrun_accesses * 1; - num_accesses += thisrun_accesses; + /* advance buffer, count number of accesses */ + buffer += thisrun_accesses * 1; + num_accesses += thisrun_accesses; - if ((j++%1024) == 0) - keep_alive(); - } - break; + if ((j++ % 1024) == 0) + keep_alive(); + } + break; } if (!is_arm_mode(arm->core_mode)) @@ -2313,23 +2313,67 @@ int arm7_9_write_memory(struct target *target, embeddedice_store_reg(dbg_ctrl); switch (size) { - case 4: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - reg[i] = target_buffer_get_u32(target, buffer); - buffer += 4; - } + case 4: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + reg[i] = target_buffer_get_u32(target, buffer); + buffer += 4; + } - arm7_9->write_core_regs(target, reg_list, reg); + arm7_9->write_core_regs(target, reg_list, reg); - arm7_9->store_word_regs(target, reg_list); + arm7_9->store_word_regs(target, reg_list); + + /* fast memory writes are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) { + retval = arm7_9_execute_fast_sys_speed(target); + } else { + retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + + if (retval != ERROR_OK) + return retval; + + num_accesses += thisrun_accesses; + } + break; + case 2: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + reg[i] = target_buffer_get_u16(target, buffer) & 0xffff; + buffer += 2; + } + + arm7_9->write_core_regs(target, reg_list, reg); + + for (i = 1; i <= thisrun_accesses; i++) { + arm7_9->store_hword_reg(target, i); /* fast memory writes are only safe when the target is running * from a sufficiently high clock (32 kHz is usually too slow) @@ -2352,99 +2396,55 @@ int arm7_9_write_memory(struct target *target, if (retval != ERROR_OK) return retval; + } - num_accesses += thisrun_accesses; + num_accesses += thisrun_accesses; + } + break; + case 1: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + reg[i] = *buffer++ & 0xff; } - break; - case 2: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - reg[i] = target_buffer_get_u16(target, buffer) & 0xffff; - buffer += 2; - } - arm7_9->write_core_regs(target, reg_list, reg); + arm7_9->write_core_regs(target, reg_list, reg); - for (i = 1; i <= thisrun_accesses; i++) { - arm7_9->store_hword_reg(target, i); + for (i = 1; i <= thisrun_accesses; i++) { + arm7_9->store_byte_reg(target, i); + /* fast memory writes are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) { + retval = arm7_9_execute_fast_sys_speed(target); + } else { + retval = arm7_9_execute_sys_speed(target); - /* fast memory writes are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. */ - if (arm7_9->fast_memory_access) { - retval = arm7_9_execute_fast_sys_speed(target); - } else { - retval = arm7_9_execute_sys_speed(target); - - /* - * if memory writes are made when the clock is running slow - * (i.e. 32 kHz) which is necessary in some scripts to reconfigure - * processor operations after a "reset halt" or "reset init", - * need to immediately stroke the keep alive or will end up with - * gdb "keep alive not sent error message" problem. - */ - - keep_alive(); - } - if (retval != ERROR_OK) - return retval; - } - - num_accesses += thisrun_accesses; - } - break; - case 1: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - reg[i] = *buffer++ & 0xff; + keep_alive(); } - arm7_9->write_core_regs(target, reg_list, reg); - - for (i = 1; i <= thisrun_accesses; i++) { - arm7_9->store_byte_reg(target, i); - /* fast memory writes are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) - */ - if (arm7_9->fast_memory_access) { - retval = arm7_9_execute_fast_sys_speed(target); - } else { - retval = arm7_9_execute_sys_speed(target); - - /* - * if memory writes are made when the clock is running slow - * (i.e. 32 kHz) which is necessary in some scripts to reconfigure - * processor operations after a "reset halt" or "reset init", - * need to immediately stroke the keep alive or will end up with - * gdb "keep alive not sent error message" problem. - */ - - keep_alive(); - } - - if (retval != ERROR_OK) - return retval; - - } + if (retval != ERROR_OK) + return retval; - num_accesses += thisrun_accesses; } - break; + + num_accesses += thisrun_accesses; + } + break; } /* Re-Set DBGACK */ diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 2f59254afd..fea6a3ff2a 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -327,15 +327,15 @@ static void arm7tdmi_read_core_regs_target_buffer(struct target *target, /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */ if (mask & (1 << i)) { switch (size) { - case 4: - arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); - break; - case 2: - arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); - break; - case 1: - arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); - break; + case 4: + arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); + break; + case 2: + arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); + break; + case 1: + arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); + break; } } } diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 0531106562..5f759f2162 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -220,88 +220,88 @@ static int arm926ejs_examine_debug_reason(struct target *target) debug_reason = buf_get_u32(dbg_stat->value, 6, 4); switch (debug_reason) { - case 0: - LOG_DEBUG("no *NEW* debug entry (?missed one?)"); - /* ... since last restart or debug reset ... */ - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 1: - LOG_DEBUG("breakpoint from EICE unit 0"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 2: - LOG_DEBUG("breakpoint from EICE unit 1"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 3: - LOG_DEBUG("soft breakpoint (BKPT instruction)"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 4: - LOG_DEBUG("vector catch breakpoint"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 5: - LOG_DEBUG("external breakpoint"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 6: - LOG_DEBUG("watchpoint from EICE unit 0"); - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - case 7: - LOG_DEBUG("watchpoint from EICE unit 1"); - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - case 8: - LOG_DEBUG("external watchpoint"); - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - case 9: - LOG_DEBUG("internal debug request"); - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 10: - LOG_DEBUG("external debug request"); - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 11: - LOG_DEBUG("debug re-entry from system speed access"); - /* This is normal when connecting to something that's - * already halted, or in some related code paths, but - * otherwise is surprising (and presumably wrong). - */ - switch (target->debug_reason) { - case DBG_REASON_DBGRQ: - break; - default: - LOG_ERROR("unexpected -- debug re-entry"); - /* FALLTHROUGH */ - case DBG_REASON_UNDEFINED: - target->debug_reason = DBG_REASON_DBGRQ; - break; - } - break; - case 12: - /* FIX!!!! here be dragons!!! We need to fail here so - * the target will interpreted as halted but we won't - * try to talk to it right now... a resume + halt seems - * to sync things up again. Please send an email to - * openocd development mailing list if you have hardware - * to donate to look into this problem.... - */ - LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt."); - target->debug_reason = DBG_REASON_DBGRQ; + case 0: + LOG_DEBUG("no *NEW* debug entry (?missed one?)"); + /* ... since last restart or debug reset ... */ + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 1: + LOG_DEBUG("breakpoint from EICE unit 0"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 2: + LOG_DEBUG("breakpoint from EICE unit 1"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 3: + LOG_DEBUG("soft breakpoint (BKPT instruction)"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 4: + LOG_DEBUG("vector catch breakpoint"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 5: + LOG_DEBUG("external breakpoint"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 6: + LOG_DEBUG("watchpoint from EICE unit 0"); + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + case 7: + LOG_DEBUG("watchpoint from EICE unit 1"); + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + case 8: + LOG_DEBUG("external watchpoint"); + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + case 9: + LOG_DEBUG("internal debug request"); + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 10: + LOG_DEBUG("external debug request"); + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 11: + LOG_DEBUG("debug re-entry from system speed access"); + /* This is normal when connecting to something that's + * already halted, or in some related code paths, but + * otherwise is surprising (and presumably wrong). + */ + switch (target->debug_reason) { + case DBG_REASON_DBGRQ: break; default: - LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason); - /* Oh agony! should we interpret this as a halt request or - * that the target stopped on it's own accord? - */ + LOG_ERROR("unexpected -- debug re-entry"); + /* FALLTHROUGH */ + case DBG_REASON_UNDEFINED: target->debug_reason = DBG_REASON_DBGRQ; - /* if we fail here, we won't talk to the target and it will - * be reported to be in the halted state */ break; + } + break; + case 12: + /* FIX!!!! here be dragons!!! We need to fail here so + * the target will interpreted as halted but we won't + * try to talk to it right now... a resume + halt seems + * to sync things up again. Please send an email to + * openocd development mailing list if you have hardware + * to donate to look into this problem.... + */ + LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt."); + target->debug_reason = DBG_REASON_DBGRQ; + break; + default: + LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason); + /* Oh agony! should we interpret this as a halt request or + * that the target stopped on it's own accord? + */ + target->debug_reason = DBG_REASON_DBGRQ; + /* if we fail here, we won't talk to the target and it will + * be reported to be in the halted state */ + break; } return ERROR_OK; diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 8ab12de320..34b4ba2cea 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -398,15 +398,15 @@ static void arm9tdmi_read_core_regs_target_buffer(struct target *target, if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ switch (size) { - case 4: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); - break; - case 2: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); - break; - case 1: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); - break; + case 4: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); + break; + case 2: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); + break; + case 1: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); + break; } } } diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c index be5e63c7ca..5ba5e1c387 100644 --- a/src/target/arm_dap.c +++ b/src/target/arm_dap.c @@ -442,28 +442,28 @@ COMMAND_HANDLER(handle_dap_info_command) } switch (CMD_ARGC) { - case 0: - apsel = dap->apsel; - break; - case 1: - if (!strcmp(CMD_ARGV[0], "root")) { - if (!is_adiv6(dap)) { - command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP"); - return ERROR_COMMAND_ARGUMENT_INVALID; - } - int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel); - if (retval != ERROR_OK) { - command_print(CMD, "Failed reading DAP baseptr"); - return retval; - } - break; + case 0: + apsel = dap->apsel; + break; + case 1: + if (!strcmp(CMD_ARGV[0], "root")) { + if (!is_adiv6(dap)) { + command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel); + if (retval != ERROR_OK) { + command_print(CMD, "Failed reading DAP baseptr"); + return retval; } - COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel); - if (!is_ap_num_valid(dap, apsel)) - return ERROR_COMMAND_SYNTAX_ERROR; break; - default: + } + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel); + if (!is_ap_num_valid(dap, apsel)) return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } struct adiv5_ap *ap = dap_get_ap(dap, apsel); diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 8619f8f82e..5b8ecc91a0 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -248,39 +248,39 @@ static int evaluate_srs(uint32_t opcode, const char *mode = ""; switch ((opcode >> 23) & 0x3) { - case 0: - mode = "DA"; - break; - case 1: - /* "IA" is default */ - break; - case 2: - mode = "DB"; - break; - case 3: - mode = "IB"; - break; + case 0: + mode = "DA"; + break; + case 1: + /* "IA" is default */ + break; + case 2: + mode = "DB"; + break; + case 3: + mode = "IB"; + break; } switch (opcode & 0x0e500000) { - case 0x08400000: - snprintf(instruction->text, 128, "0x%8.8" PRIx32 - "\t0x%8.8" PRIx32 - "\tSRS%s\tSP%s, #%" PRIu32, - address, opcode, - mode, wback, - opcode & 0x1f); - break; - case 0x08100000: - snprintf(instruction->text, 128, "0x%8.8" PRIx32 - "\t0x%8.8" PRIx32 - "\tRFE%s\tr%" PRIu32 "%s", - address, opcode, - mode, - (opcode >> 16) & 0xf, wback); - break; - default: - return evaluate_unknown(opcode, address, instruction); + case 0x08400000: + snprintf(instruction->text, 128, "0x%8.8" PRIx32 + "\t0x%8.8" PRIx32 + "\tSRS%s\tSP%s, #%" PRIu32, + address, opcode, + mode, wback, + opcode & 0x1f); + break; + case 0x08100000: + snprintf(instruction->text, 128, "0x%8.8" PRIx32 + "\t0x%8.8" PRIx32 + "\tRFE%s\tr%" PRIu32 "%s", + address, opcode, + mode, + (opcode >> 16) & 0xf, wback); + break; + default: + return evaluate_unknown(opcode, address, instruction); } return ERROR_OK; } @@ -631,21 +631,21 @@ static int evaluate_load_store(uint32_t opcode, snprintf(offset, 32, ", %sr%i", (u) ? "" : "-", rm); else { /* +-<Rm>, <Shift>, #<shift_imm> */ switch (shift) { - case 0x0: /* LSL */ - snprintf(offset, 32, ", %sr%i, LSL #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x1: /* LSR */ - snprintf(offset, 32, ", %sr%i, LSR #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x2: /* ASR */ - snprintf(offset, 32, ", %sr%i, ASR #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x3: /* ROR */ - snprintf(offset, 32, ", %sr%i, ROR #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x4: /* RRX */ - snprintf(offset, 32, ", %sr%i, RRX", (u) ? "" : "-", rm); - break; + case 0x0: /* LSL */ + snprintf(offset, 32, ", %sr%i, LSL #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x1: /* LSR */ + snprintf(offset, 32, ", %sr%i, LSR #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x2: /* ASR */ + snprintf(offset, 32, ", %sr%i, ASR #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x3: /* ROR */ + snprintf(offset, 32, ", %sr%i, ROR #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x4: /* RRX */ + snprintf(offset, 32, ", %sr%i, RRX", (u) ? "" : "-", rm); + break; } } } @@ -707,33 +707,33 @@ static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp) char *type, *rot; switch ((opcode >> 24) & 0x3) { - case 0: - type = "B16"; - break; - case 1: - sprintf(cp, "UNDEFINED"); - return ARM_UNDEFINED_INSTRUCTION; - case 2: - type = "B"; - break; - default: - type = "H"; - break; + case 0: + type = "B16"; + break; + case 1: + sprintf(cp, "UNDEFINED"); + return ARM_UNDEFINED_INSTRUCTION; + case 2: + type = "B"; + break; + default: + type = "H"; + break; } switch ((opcode >> 10) & 0x3) { - case 0: - rot = ""; - break; - case 1: - rot = ", ROR #8"; - break; - case 2: - rot = ", ROR #16"; - break; - default: - rot = ", ROR #24"; - break; + case 0: + rot = ""; + break; + case 1: + rot = ", ROR #8"; + break; + case 2: + rot = ", ROR #16"; + break; + default: + rot = ", ROR #24"; + break; } if (rn == 0xf) { @@ -758,55 +758,55 @@ static int evaluate_p_add_sub(uint32_t opcode, uint32_t address, char *cp) int type; switch ((opcode >> 20) & 0x7) { - case 1: - prefix = "S"; - break; - case 2: - prefix = "Q"; - break; - case 3: - prefix = "SH"; - break; - case 5: - prefix = "U"; - break; - case 6: - prefix = "UQ"; - break; - case 7: - prefix = "UH"; - break; - default: - goto undef; + case 1: + prefix = "S"; + break; + case 2: + prefix = "Q"; + break; + case 3: + prefix = "SH"; + break; + case 5: + prefix = "U"; + break; + case 6: + prefix = "UQ"; + break; + case 7: + prefix = "UH"; + break; + default: + goto undef; } switch ((opcode >> 5) & 0x7) { - case 0: - op = "ADD16"; - type = ARM_ADD; - break; - case 1: - op = "ADDSUBX"; - type = ARM_ADD; - break; - case 2: - op = "SUBADDX"; - type = ARM_SUB; - break; - case 3: - op = "SUB16"; - type = ARM_SUB; - break; - case 4: - op = "ADD8"; - type = ARM_ADD; - break; - case 7: - op = "SUB8"; - type = ARM_SUB; - break; - default: - goto undef; + case 0: + op = "ADD16"; + type = ARM_ADD; + break; + case 1: + op = "ADDSUBX"; + type = ARM_ADD; + break; + case 2: + op = "SUBADDX"; + type = ARM_SUB; + break; + case 3: + op = "SUB16"; + type = ARM_SUB; + break; + case 4: + op = "ADD8"; + type = ARM_ADD; + break; + case 7: + op = "SUB8"; + type = ARM_SUB; + break; + default: + goto undef; } sprintf(cp, "%s%s%s\tr%d, r%d, r%d", prefix, op, COND(opcode), @@ -928,14 +928,14 @@ static int evaluate_media(uint32_t opcode, uint32_t address, unsigned int rn = (opcode >> 12) & 0xf; switch (opcode & 0xc0) { - case 3: - if (rn == 0xf) - goto undef; - /* FALL THROUGH */ - case 0: - break; - default: + case 3: + if (rn == 0xf) goto undef; + /* FALL THROUGH */ + case 0: + break; + default: + goto undef; } if (rn != 0xf) @@ -959,46 +959,46 @@ static int evaluate_media(uint32_t opcode, uint32_t address, /* simple matches against the remaining decode bits */ switch (opcode & 0x01f000f0) { - case 0x00a00030: - case 0x00e00030: - /* parallel halfword saturate */ - sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d", - (opcode & (1 << 22)) ? 'U' : 'S', - COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf); - return ERROR_OK; - case 0x00b00030: - mnemonic = "REV"; - break; - case 0x00b000b0: - mnemonic = "REV16"; - break; - case 0x00f000b0: - mnemonic = "REVSH"; - break; - case 0x008000b0: - /* select bytes */ - sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf); - return ERROR_OK; - case 0x01800010: - /* unsigned sum of absolute differences */ - if (((opcode >> 12) & 0xf) == 0xf) - sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode), - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf); - else - sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode), - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf, - (int) (opcode >> 12) & 0xf); - return ERROR_OK; + case 0x00a00030: + case 0x00e00030: + /* parallel halfword saturate */ + sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d", + (opcode & (1 << 22)) ? 'U' : 'S', + COND(opcode), + (int)(opcode >> 12) & 0xf, + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf); + return ERROR_OK; + case 0x00b00030: + mnemonic = "REV"; + break; + case 0x00b000b0: + mnemonic = "REV16"; + break; + case 0x00f000b0: + mnemonic = "REVSH"; + break; + case 0x008000b0: + /* select bytes */ + sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode), + (int)(opcode >> 12) & 0xf, + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf); + return ERROR_OK; + case 0x01800010: + /* unsigned sum of absolute differences */ + if (((opcode >> 12) & 0xf) == 0xf) + sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode), + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf, + (int)(opcode >> 8) & 0xf); + else + sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode), + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf, + (int)(opcode >> 8) & 0xf, + (int)(opcode >> 12) & 0xf); + return ERROR_OK; } if (mnemonic) { unsigned int rm = (opcode >> 0) & 0xf; @@ -1280,22 +1280,22 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, s = (opcode & 0x00100000) >> 20; switch ((opcode & 0x00600000) >> 21) { - case 0x0: - instruction->type = ARM_UMULL; - mnemonic = "UMULL"; - break; - case 0x1: - instruction->type = ARM_UMLAL; - mnemonic = "UMLAL"; - break; - case 0x2: - instruction->type = ARM_SMULL; - mnemonic = "SMULL"; - break; - case 0x3: - instruction->type = ARM_SMLAL; - mnemonic = "SMLAL"; - break; + case 0x0: + instruction->type = ARM_UMULL; + mnemonic = "UMULL"; + break; + case 0x1: + instruction->type = ARM_UMLAL; + mnemonic = "UMLAL"; + break; + case 0x2: + instruction->type = ARM_SMULL; + mnemonic = "SMULL"; + break; + case 0x3: + instruction->type = ARM_SMLAL; + mnemonic = "SMLAL"; + break; } snprintf(instruction->text, @@ -1480,22 +1480,22 @@ static int evaluate_misc_instr(uint32_t opcode, rn = (opcode & 0xf0000) >> 16; switch ((opcode & 0x00600000) >> 21) { - case 0x0: - instruction->type = ARM_QADD; - mnemonic = "QADD"; - break; - case 0x1: - instruction->type = ARM_QSUB; - mnemonic = "QSUB"; - break; - case 0x2: - instruction->type = ARM_QDADD; - mnemonic = "QDADD"; - break; - case 0x3: - instruction->type = ARM_QDSUB; - mnemonic = "QDSUB"; - break; + case 0x0: + instruction->type = ARM_QADD; + mnemonic = "QADD"; + break; + case 0x1: + instruction->type = ARM_QSUB; + mnemonic = "QSUB"; + break; + case 0x2: + instruction->type = ARM_QDADD; + mnemonic = "QDADD"; + break; + case 0x3: + instruction->type = ARM_QDSUB; + mnemonic = "QDSUB"; + break; } snprintf(instruction->text, @@ -1527,21 +1527,21 @@ static int evaluate_misc_instr(uint32_t opcode, char *mnemonic = NULL; switch ((opcode & 0x600000) >> 21) { - case 0x1: - instruction->type = ARM_BKPT; - mnemonic = "BRKT"; - immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); - break; - case 0x2: - instruction->type = ARM_HVC; - mnemonic = "HVC"; - immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); - break; - case 0x3: - instruction->type = ARM_SMC; - mnemonic = "SMC"; - immediate = (opcode & 0xf); - break; + case 0x1: + instruction->type = ARM_BKPT; + mnemonic = "BRKT"; + immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); + break; + case 0x2: + instruction->type = ARM_HVC; + mnemonic = "HVC"; + immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); + break; + case 0x3: + instruction->type = ARM_SMC; + mnemonic = "SMC"; + immediate = (opcode & 0xf); + break; } snprintf(instruction->text, @@ -1717,70 +1717,70 @@ static int evaluate_data_proc(uint32_t opcode, instruction->info.data_proc.s = s; switch (op) { - case 0x0: - instruction->type = ARM_AND; - mnemonic = "AND"; - break; - case 0x1: - instruction->type = ARM_EOR; - mnemonic = "EOR"; - break; - case 0x2: - instruction->type = ARM_SUB; - mnemonic = "SUB"; - break; - case 0x3: - instruction->type = ARM_RSB; - mnemonic = "RSB"; - break; - case 0x4: - instruction->type = ARM_ADD; - mnemonic = "ADD"; - break; - case 0x5: - instruction->type = ARM_ADC; - mnemonic = "ADC"; - break; - case 0x6: - instruction->type = ARM_SBC; - mnemonic = "SBC"; - break; - case 0x7: - instruction->type = ARM_RSC; - mnemonic = "RSC"; - break; - case 0x8: - instruction->type = ARM_TST; - mnemonic = "TST"; - break; - case 0x9: - instruction->type = ARM_TEQ; - mnemonic = "TEQ"; - break; - case 0xa: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - break; - case 0xb: - instruction->type = ARM_CMN; - mnemonic = "CMN"; - break; - case 0xc: - instruction->type = ARM_ORR; - mnemonic = "ORR"; - break; - case 0xd: - instruction->type = ARM_MOV; - mnemonic = "MOV"; - break; - case 0xe: - instruction->type = ARM_BIC; - mnemonic = "BIC"; - break; - case 0xf: - instruction->type = ARM_MVN; - mnemonic = "MVN"; - break; + case 0x0: + instruction->type = ARM_AND; + mnemonic = "AND"; + break; + case 0x1: + instruction->type = ARM_EOR; + mnemonic = "EOR"; + break; + case 0x2: + instruction->type = ARM_SUB; + mnemonic = "SUB"; + break; + case 0x3: + instruction->type = ARM_RSB; + mnemonic = "RSB"; + break; + case 0x4: + instruction->type = ARM_ADD; + mnemonic = "ADD"; + break; + case 0x5: + instruction->type = ARM_ADC; + mnemonic = "ADC"; + break; + case 0x6: + instruction->type = ARM_SBC; + mnemonic = "SBC"; + break; + case 0x7: + instruction->type = ARM_RSC; + mnemonic = "RSC"; + break; + case 0x8: + instruction->type = ARM_TST; + mnemonic = "TST"; + break; + case 0x9: + instruction->type = ARM_TEQ; + mnemonic = "TEQ"; + break; + case 0xa: + instruction->type = ARM_CMP; + mnemonic = "CMP"; + break; + case 0xb: + instruction->type = ARM_CMN; + mnemonic = "CMN"; + break; + case 0xc: + instruction->type = ARM_ORR; + mnemonic = "ORR"; + break; + case 0xd: + instruction->type = ARM_MOV; + mnemonic = "MOV"; + break; + case 0xe: + instruction->type = ARM_BIC; + mnemonic = "BIC"; + break; + case 0xf: + instruction->type = ARM_MVN; + mnemonic = "MVN"; + break; } if (i) {/* immediate shifter operand (#<immediate>)*/ @@ -2065,28 +2065,28 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode, target_address = address + 4 + (offset << 1); switch (opc) { - /* unconditional branch */ - case 0: - instruction->type = ARM_B; - mnemonic = "B"; - break; - /* BLX suffix */ - case 1: - instruction->type = ARM_BLX; - mnemonic = "BLX"; - target_address &= 0xfffffffc; - break; - /* BL/BLX prefix */ - case 2: - instruction->type = ARM_UNKNOWN_INSTRUCTION; - mnemonic = "prefix"; - target_address = offset << 12; - break; - /* BL suffix */ - case 3: - instruction->type = ARM_BL; - mnemonic = "BL"; - break; + /* unconditional branch */ + case 0: + instruction->type = ARM_B; + mnemonic = "B"; + break; + /* BLX suffix */ + case 1: + instruction->type = ARM_BLX; + mnemonic = "BLX"; + target_address &= 0xfffffffc; + break; + /* BL/BLX prefix */ + case 2: + instruction->type = ARM_UNKNOWN_INSTRUCTION; + mnemonic = "prefix"; + target_address = offset << 12; + break; + /* BL suffix */ + case 3: + instruction->type = ARM_BL; + mnemonic = "BL"; + break; } /* TODO: deal correctly with dual opcode (prefixed) BL/BLX; @@ -2158,21 +2158,21 @@ static int evaluate_shift_imm_thumb(uint16_t opcode, char *mnemonic = NULL; switch (opc) { - case 0: - instruction->type = ARM_MOV; - mnemonic = "LSLS"; - instruction->info.data_proc.shifter_operand.immediate_shift.shift = 0; - break; - case 1: - instruction->type = ARM_MOV; - mnemonic = "LSRS"; - instruction->info.data_proc.shifter_operand.immediate_shift.shift = 1; - break; - case 2: - instruction->type = ARM_MOV; - mnemonic = "ASRS"; - instruction->info.data_proc.shifter_operand.immediate_shift.shift = 2; - break; + case 0: + instruction->type = ARM_MOV; + mnemonic = "LSLS"; + instruction->info.data_proc.shifter_operand.immediate_shift.shift = 0; + break; + case 1: + instruction->type = ARM_MOV; + mnemonic = "LSRS"; + instruction->info.data_proc.shifter_operand.immediate_shift.shift = 1; + break; + case 2: + instruction->type = ARM_MOV; + mnemonic = "ASRS"; + instruction->info.data_proc.shifter_operand.immediate_shift.shift = 2; + break; } if ((imm == 0) && (opc != 0)) @@ -2208,24 +2208,24 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, instruction->info.data_proc.shifter_operand.immediate.immediate = imm; switch (opc) { - case 0: - instruction->type = ARM_MOV; - mnemonic = "MOVS"; - instruction->info.data_proc.rn = -1; - break; - case 1: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - instruction->info.data_proc.rd = -1; - break; - case 2: - instruction->type = ARM_ADD; - mnemonic = "ADDS"; - break; - case 3: - instruction->type = ARM_SUB; - mnemonic = "SUBS"; - break; + case 0: + instruction->type = ARM_MOV; + mnemonic = "MOVS"; + instruction->info.data_proc.rn = -1; + break; + case 1: + instruction->type = ARM_CMP; + mnemonic = "CMP"; + instruction->info.data_proc.rd = -1; + break; + case 2: + instruction->type = ARM_ADD; + mnemonic = "ADDS"; + break; + case 3: + instruction->type = ARM_SUB; + mnemonic = "SUBS"; + break; } snprintf(instruction->text, 128, @@ -2262,131 +2262,131 @@ static int evaluate_data_proc_thumb(uint16_t opcode, op >>= 2; switch (op) { - case 0x0: - instruction->type = ARM_ADD; - mnemonic = "ADD"; - break; - case 0x1: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - break; - case 0x2: - instruction->type = ARM_MOV; - mnemonic = "MOV"; - if (rd == rm) - nop = true; - break; - case 0x3: - if ((opcode & 0x7) == 0x0) { - instruction->info.b_bl_bx_blx.reg_operand = rm; - if (h1) { - instruction->type = ARM_BLX; - snprintf(instruction->text, 128, - "0x%8.8" PRIx32 - " 0x%4.4x \tBLX\tr%i", - address, opcode, rm); - } else { - instruction->type = ARM_BX; - snprintf(instruction->text, 128, - "0x%8.8" PRIx32 - " 0x%4.4x \tBX\tr%i", - address, opcode, rm); - } + case 0x0: + instruction->type = ARM_ADD; + mnemonic = "ADD"; + break; + case 0x1: + instruction->type = ARM_CMP; + mnemonic = "CMP"; + break; + case 0x2: + instruction->type = ARM_MOV; + mnemonic = "MOV"; + if (rd == rm) + nop = true; + break; + case 0x3: + if ((opcode & 0x7) == 0x0) { + instruction->info.b_bl_bx_blx.reg_operand = rm; + if (h1) { + instruction->type = ARM_BLX; + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 + " 0x%4.4x \tBLX\tr%i", + address, opcode, rm); } else { - instruction->type = ARM_UNDEFINED_INSTRUCTION; + instruction->type = ARM_BX; snprintf(instruction->text, 128, "0x%8.8" PRIx32 - " 0x%4.4x \t" - "UNDEFINED INSTRUCTION", - address, opcode); + " 0x%4.4x \tBX\tr%i", + address, opcode, rm); } - return ERROR_OK; + } else { + instruction->type = ARM_UNDEFINED_INSTRUCTION; + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 + " 0x%4.4x \t" + "UNDEFINED INSTRUCTION", + address, opcode); + } + return ERROR_OK; } } else { switch (op) { - case 0x0: - instruction->type = ARM_AND; - mnemonic = "ANDS"; - break; - case 0x1: - instruction->type = ARM_EOR; - mnemonic = "EORS"; - break; - case 0x2: - instruction->type = ARM_MOV; - mnemonic = "LSLS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 0; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x3: - instruction->type = ARM_MOV; - mnemonic = "LSRS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 1; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x4: - instruction->type = ARM_MOV; - mnemonic = "ASRS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 2; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x5: - instruction->type = ARM_ADC; - mnemonic = "ADCS"; - break; - case 0x6: - instruction->type = ARM_SBC; - mnemonic = "SBCS"; - break; - case 0x7: - instruction->type = ARM_MOV; - mnemonic = "RORS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 3; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x8: - instruction->type = ARM_TST; - mnemonic = "TST"; - break; - case 0x9: - instruction->type = ARM_RSB; - mnemonic = "RSBS"; - instruction->info.data_proc.variant = 0 /*immediate*/; - instruction->info.data_proc.shifter_operand.immediate.immediate = 0; - instruction->info.data_proc.rn = rm; - break; - case 0xA: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - break; - case 0xB: - instruction->type = ARM_CMN; - mnemonic = "CMN"; - break; - case 0xC: - instruction->type = ARM_ORR; - mnemonic = "ORRS"; - break; - case 0xD: - instruction->type = ARM_MUL; - mnemonic = "MULS"; - break; - case 0xE: - instruction->type = ARM_BIC; - mnemonic = "BICS"; - break; - case 0xF: - instruction->type = ARM_MVN; - mnemonic = "MVNS"; - break; + case 0x0: + instruction->type = ARM_AND; + mnemonic = "ANDS"; + break; + case 0x1: + instruction->type = ARM_EOR; + mnemonic = "EORS"; + break; + case 0x2: + instruction->type = ARM_MOV; + mnemonic = "LSLS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 0; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; + break; + case 0x3: + instruction->type = ARM_MOV; + mnemonic = "LSRS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 1; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; + break; + case 0x4: + instruction->type = ARM_MOV; + mnemonic = "ASRS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 2; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; + break; + case 0x5: + instruction->type = ARM_ADC; + mnemonic = "ADCS"; + break; + case 0x6: + instruction->type = ARM_SBC; + mnemonic = "SBCS"; + break; + case 0x7: + instruction->type = ARM_MOV; + mnemonic = "RORS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 3; + instructi... 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