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[PATCH]: b194adaad1 flash: nor: align switch and case statements
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From: <ge...@op...> - 2025-07-25 18:29:19
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This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9034 -- gerrit commit b194adaad1b020119852659ff2dd3526e57d3235 Author: Antonio Borneo <bor...@gm...> Date: Sat Jun 28 11:21:26 2025 +0200 flash: nor: align switch and case statements The coding style requires the 'case' to be at the same indentation level of its 'switch' statement. Align the code accordingly. No changes are reported by git log -p -w --ignore-blank-lines --patience Change-Id: I6be44efd5189b671caabcf6753bb82ef44521440 Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c index 67cc6b68a7..cb9fa5ed77 100644 --- a/src/flash/nor/ambiqmicro.c +++ b/src/flash/nor/ambiqmicro.c @@ -190,37 +190,36 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank) ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24; switch (ambiqmicro_info->target_class) { - case 1: /* 1 - Apollo */ - case 5: /* 5 - Apollo Bootloader */ - bank->base = bank->bank_number * 0x40000; - ambiqmicro_info->pagesize = 2048; - ambiqmicro_info->flshsiz = + case 1: /* 1 - Apollo */ + case 5: /* 5 - Apollo Bootloader */ + bank->base = bank->bank_number * 0x40000; + ambiqmicro_info->pagesize = 2048; + ambiqmicro_info->flshsiz = apollo_flash_size[(part_num & 0x00F00000) >> 20]; - ambiqmicro_info->sramsiz = + ambiqmicro_info->sramsiz = apollo_sram_size[(part_num & 0x000F0000) >> 16]; - ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / - ambiqmicro_info->pagesize; - if (ambiqmicro_info->num_pages > 128) { - ambiqmicro_info->num_pages = 128; - ambiqmicro_info->flshsiz = 1024 * 256; - } - break; + ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / + ambiqmicro_info->pagesize; + if (ambiqmicro_info->num_pages > 128) { + ambiqmicro_info->num_pages = 128; + ambiqmicro_info->flshsiz = 1024 * 256; + } + break; - default: - LOG_INFO("Unknown Class. Using Apollo-64 as default."); + default: + LOG_INFO("Unknown Class. Using Apollo-64 as default."); - bank->base = bank->bank_number * 0x40000; - ambiqmicro_info->pagesize = 2048; - ambiqmicro_info->flshsiz = apollo_flash_size[1]; - ambiqmicro_info->sramsiz = apollo_sram_size[0]; - ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / + bank->base = bank->bank_number * 0x40000; + ambiqmicro_info->pagesize = 2048; + ambiqmicro_info->flshsiz = apollo_flash_size[1]; + ambiqmicro_info->sramsiz = apollo_sram_size[0]; + ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz / ambiqmicro_info->pagesize; - if (ambiqmicro_info->num_pages > 128) { - ambiqmicro_info->num_pages = 128; - ambiqmicro_info->flshsiz = 1024 * 256; - } - break; - + if (ambiqmicro_info->num_pages > 128) { + ambiqmicro_info->num_pages = 128; + ambiqmicro_info->flshsiz = 1024 * 256; + } + break; } if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts)) diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 4042d32dec..5f551681d5 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -2040,40 +2040,39 @@ do_retry: /* Check command & argument */ switch (command) { - - case AT91C_EFC_FCMD_WP: - case AT91C_EFC_FCMD_WPL: - case AT91C_EFC_FCMD_EWP: - case AT91C_EFC_FCMD_EWPL: - /* case AT91C_EFC_FCMD_EPL: */ - /* case AT91C_EFC_FCMD_EPA: */ - case AT91C_EFC_FCMD_SLB: - case AT91C_EFC_FCMD_CLB: - n = (private->size_bytes / private->page_size); - if (argument >= n) - LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); - break; - - case AT91C_EFC_FCMD_SFB: - case AT91C_EFC_FCMD_CFB: - if (argument >= private->chip->details.n_gpnvms) { - LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", - private->chip->details.n_gpnvms); - } - break; - - case AT91C_EFC_FCMD_GETD: - case AT91C_EFC_FCMD_EA: - case AT91C_EFC_FCMD_GLB: - case AT91C_EFC_FCMD_GFB: - case AT91C_EFC_FCMD_STUI: - case AT91C_EFC_FCMD_SPUI: - if (argument != 0) - LOG_ERROR("Argument is meaningless for cmd: %d", command); - break; - default: - LOG_ERROR("Unknown command %d", command); - break; + case AT91C_EFC_FCMD_WP: + case AT91C_EFC_FCMD_WPL: + case AT91C_EFC_FCMD_EWP: + case AT91C_EFC_FCMD_EWPL: + /* case AT91C_EFC_FCMD_EPL: */ + /* case AT91C_EFC_FCMD_EPA: */ + case AT91C_EFC_FCMD_SLB: + case AT91C_EFC_FCMD_CLB: + n = (private->size_bytes / private->page_size); + if (argument >= n) + LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); + break; + + case AT91C_EFC_FCMD_SFB: + case AT91C_EFC_FCMD_CFB: + if (argument >= private->chip->details.n_gpnvms) { + LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", + private->chip->details.n_gpnvms); + } + break; + + case AT91C_EFC_FCMD_GETD: + case AT91C_EFC_FCMD_EA: + case AT91C_EFC_FCMD_GLB: + case AT91C_EFC_FCMD_GFB: + case AT91C_EFC_FCMD_STUI: + case AT91C_EFC_FCMD_SPUI: + if (argument != 0) + LOG_ERROR("Argument is meaningless for cmd: %d", command); + break; + default: + LOG_ERROR("Unknown command %d", command); + break; } if (command == AT91C_EFC_FCMD_SPUI) { @@ -2571,18 +2570,18 @@ static void sam3_explain_ckgr_mor(struct sam3_chip *chip) chip->cfg.rc_freq = 0; if (rcen) { switch (v) { - case 0: - chip->cfg.rc_freq = 4 * 1000 * 1000; - break; - case 1: - chip->cfg.rc_freq = 8 * 1000 * 1000; - break; - case 2: - chip->cfg.rc_freq = 12 * 1000 * 1000; - break; - default: - chip->cfg.rc_freq = 0; - break; + case 0: + chip->cfg.rc_freq = 4 * 1000 * 1000; + break; + case 1: + chip->cfg.rc_freq = 8 * 1000 * 1000; + break; + case 2: + chip->cfg.rc_freq = 12 * 1000 * 1000; + break; + default: + chip->cfg.rc_freq = 0; + break; } } @@ -2683,30 +2682,30 @@ static void sam3_explain_mckr(struct sam3_chip *chip) css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2); switch (css & 3) { - case 0: - fin = chip->cfg.slow_freq; - cp = "slowclk"; - break; - case 1: - fin = chip->cfg.mainosc_freq; - cp = "mainosc"; - break; - case 2: - fin = chip->cfg.plla_freq; - cp = "plla"; - break; - case 3: - if (chip->cfg.CKGR_UCKR & (1 << 16)) { - fin = 480 * 1000 * 1000; - cp = "upll"; - } else { - fin = 0; - cp = "upll (*ERROR* UPLL is disabled)"; - } - break; - default: - assert(0); - break; + case 0: + fin = chip->cfg.slow_freq; + cp = "slowclk"; + break; + case 1: + fin = chip->cfg.mainosc_freq; + cp = "mainosc"; + break; + case 2: + fin = chip->cfg.plla_freq; + cp = "plla"; + break; + case 3: + if (chip->cfg.CKGR_UCKR & (1 << 16)) { + fin = 480 * 1000 * 1000; + cp = "upll"; + } else { + fin = 0; + cp = "upll (*ERROR* UPLL is disabled)"; + } + break; + default: + assert(0); + break; } LOG_USER("%s (%3.03f Mhz)", @@ -2714,41 +2713,41 @@ static void sam3_explain_mckr(struct sam3_chip *chip) _tomhz(fin)); pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3); switch (pres & 0x07) { - case 0: - pdiv = 1; - cp = "selected clock"; - break; - case 1: - pdiv = 2; - cp = "clock/2"; - break; - case 2: - pdiv = 4; - cp = "clock/4"; - break; - case 3: - pdiv = 8; - cp = "clock/8"; - break; - case 4: - pdiv = 16; - cp = "clock/16"; - break; - case 5: - pdiv = 32; - cp = "clock/32"; - break; - case 6: - pdiv = 64; - cp = "clock/64"; - break; - case 7: - pdiv = 6; - cp = "clock/6"; - break; - default: - assert(0); - break; + case 0: + pdiv = 1; + cp = "selected clock"; + break; + case 1: + pdiv = 2; + cp = "clock/2"; + break; + case 2: + pdiv = 4; + cp = "clock/4"; + break; + case 3: + pdiv = 8; + cp = "clock/8"; + break; + case 4: + pdiv = 16; + cp = "clock/16"; + break; + case 5: + pdiv = 32; + cp = "clock/32"; + break; + case 6: + pdiv = 64; + cp = "clock/64"; + break; + case 7: + pdiv = 6; + cp = "clock/6"; + break; + default: + assert(0); + break; } LOG_USER("(%s)", cp); fin = fin / pdiv; @@ -3011,39 +3010,39 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command) } switch (bank->base) { - /* at91sam3s and at91sam3n series only has bank 0*/ - /* at91sam3u and at91sam3ax series has the same address for bank 0*/ - case FLASH_BANK_BASE_S: - case FLASH_BANK0_BASE_U: - bank->driver_priv = &chip->details.bank[0]; - bank->bank_number = 0; - chip->details.bank[0].chip = chip; - chip->details.bank[0].bank = bank; - break; - - /* Bank 1 of at91sam3u or at91sam3ax series */ - case FLASH_BANK1_BASE_U: - case FLASH_BANK1_BASE_256K_AX: - case FLASH_BANK1_BASE_512K_AX: - bank->driver_priv = &chip->details.bank[1]; - bank->bank_number = 1; - chip->details.bank[1].chip = chip; - chip->details.bank[1].bank = bank; - break; - - default: - LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x or 0x%08x " - "[at91sam3u series] or 0x%08x [at91sam3s series] or " - "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )", - bank->base, - FLASH_BANK0_BASE_U, - FLASH_BANK1_BASE_U, - FLASH_BANK_BASE_S, - FLASH_BANK_BASE_N, - FLASH_BANK0_BASE_AX, - FLASH_BANK1_BASE_256K_AX, - FLASH_BANK1_BASE_512K_AX); - return ERROR_FAIL; + /* at91sam3s and at91sam3n series only has bank 0*/ + /* at91sam3u and at91sam3ax series has the same address for bank 0*/ + case FLASH_BANK_BASE_S: + case FLASH_BANK0_BASE_U: + bank->driver_priv = &chip->details.bank[0]; + bank->bank_number = 0; + chip->details.bank[0].chip = chip; + chip->details.bank[0].bank = bank; + break; + + /* Bank 1 of at91sam3u or at91sam3ax series */ + case FLASH_BANK1_BASE_U: + case FLASH_BANK1_BASE_256K_AX: + case FLASH_BANK1_BASE_512K_AX: + bank->driver_priv = &chip->details.bank[1]; + bank->bank_number = 1; + chip->details.bank[1].chip = chip; + chip->details.bank[1].bank = bank; + break; + + default: + LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x or 0x%08x " + "[at91sam3u series] or 0x%08x [at91sam3s series] or " + "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )", + bank->base, + FLASH_BANK0_BASE_U, + FLASH_BANK1_BASE_U, + FLASH_BANK_BASE_S, + FLASH_BANK_BASE_N, + FLASH_BANK0_BASE_AX, + FLASH_BANK1_BASE_256K_AX, + FLASH_BANK1_BASE_512K_AX); + return ERROR_FAIL; } /* we initialize after probing. */ @@ -3574,22 +3573,22 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) } switch (CMD_ARGC) { - case 0: - goto showall; - case 1: + case 0: + goto showall; + case 1: + who = -1; + break; + case 2: + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { who = -1; - break; - case 2: - if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { - who = -1; - } else { - uint32_t v32; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); - who = v32; - } - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + } else { + uint32_t v32; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); + who = v32; + } + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (strcmp("show", CMD_ARGV[0]) == 0) { @@ -3641,26 +3640,26 @@ COMMAND_HANDLER(sam3_handle_slowclk_command) return ERROR_OK; switch (CMD_ARGC) { - case 0: - /* show */ - break; - case 1: - { - /* set */ - uint32_t v; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); - if (v > 200000) { - /* absurd slow clock of 200Khz? */ - command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); - return ERROR_COMMAND_SYNTAX_ERROR; - } - chip->cfg.slow_freq = v; - break; - } - default: - /* error */ - command_print(CMD, "Too many parameters"); + case 0: + /* show */ + break; + case 1: + { + /* set */ + uint32_t v; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); + if (v > 200000) { + /* absurd slow clock of 200Khz? */ + command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); return ERROR_COMMAND_SYNTAX_ERROR; + } + chip->cfg.slow_freq = v; + break; + } + default: + /* error */ + command_print(CMD, "Too many parameters"); + return ERROR_COMMAND_SYNTAX_ERROR; } command_print(CMD, "Slowclk freq: %d.%03dkhz", (int)(chip->cfg.slow_freq / 1000), diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index 08f1955778..dd3a1ca3f0 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -1490,40 +1490,39 @@ do_retry: /* Check command & argument */ switch (command) { - - case AT91C_EFC_FCMD_WP: - case AT91C_EFC_FCMD_WPL: - case AT91C_EFC_FCMD_EWP: - case AT91C_EFC_FCMD_EWPL: - /* case AT91C_EFC_FCMD_EPL: */ - case AT91C_EFC_FCMD_EPA: - case AT91C_EFC_FCMD_SLB: - case AT91C_EFC_FCMD_CLB: - n = (private->size_bytes / private->page_size); - if (argument >= n) - LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); - break; - - case AT91C_EFC_FCMD_SFB: - case AT91C_EFC_FCMD_CFB: - if (argument >= private->chip->details.n_gpnvms) { - LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", - private->chip->details.n_gpnvms); - } - break; - - case AT91C_EFC_FCMD_GETD: - case AT91C_EFC_FCMD_EA: - case AT91C_EFC_FCMD_GLB: - case AT91C_EFC_FCMD_GFB: - case AT91C_EFC_FCMD_STUI: - case AT91C_EFC_FCMD_SPUI: - if (argument != 0) - LOG_ERROR("Argument is meaningless for cmd: %d", command); - break; - default: - LOG_ERROR("Unknown command %d", command); - break; + case AT91C_EFC_FCMD_WP: + case AT91C_EFC_FCMD_WPL: + case AT91C_EFC_FCMD_EWP: + case AT91C_EFC_FCMD_EWPL: + /* case AT91C_EFC_FCMD_EPL: */ + case AT91C_EFC_FCMD_EPA: + case AT91C_EFC_FCMD_SLB: + case AT91C_EFC_FCMD_CLB: + n = (private->size_bytes / private->page_size); + if (argument >= n) + LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n); + break; + + case AT91C_EFC_FCMD_SFB: + case AT91C_EFC_FCMD_CFB: + if (argument >= private->chip->details.n_gpnvms) { + LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs", + private->chip->details.n_gpnvms); + } + break; + + case AT91C_EFC_FCMD_GETD: + case AT91C_EFC_FCMD_EA: + case AT91C_EFC_FCMD_GLB: + case AT91C_EFC_FCMD_GFB: + case AT91C_EFC_FCMD_STUI: + case AT91C_EFC_FCMD_SPUI: + if (argument != 0) + LOG_ERROR("Argument is meaningless for cmd: %d", command); + break; + default: + LOG_ERROR("Unknown command %d", command); + break; } if (command == AT91C_EFC_FCMD_SPUI) { @@ -1678,21 +1677,21 @@ static int flashd_erase_pages(struct sam4_bank_private *private, LOG_DEBUG("Here"); uint8_t erase_pages; switch (num_pages) { - case 4: - erase_pages = 0x00; - break; - case 8: - erase_pages = 0x01; - break; - case 16: - erase_pages = 0x02; - break; - case 32: - erase_pages = 0x03; - break; - default: - erase_pages = 0x00; - break; + case 4: + erase_pages = 0x00; + break; + case 8: + erase_pages = 0x01; + break; + case 16: + erase_pages = 0x02; + break; + case 32: + erase_pages = 0x03; + break; + default: + erase_pages = 0x00; + break; } /* AT91C_EFC_FCMD_EPA @@ -2080,18 +2079,18 @@ static void sam4_explain_ckgr_mor(struct sam4_chip *chip) chip->cfg.rc_freq = 0; if (rcen) { switch (v) { - case 0: - chip->cfg.rc_freq = 4 * 1000 * 1000; - break; - case 1: - chip->cfg.rc_freq = 8 * 1000 * 1000; - break; - case 2: - chip->cfg.rc_freq = 12 * 1000 * 1000; - break; - default: - chip->cfg.rc_freq = 0; - break; + case 0: + chip->cfg.rc_freq = 4 * 1000 * 1000; + break; + case 1: + chip->cfg.rc_freq = 8 * 1000 * 1000; + break; + case 2: + chip->cfg.rc_freq = 12 * 1000 * 1000; + break; + default: + chip->cfg.rc_freq = 0; + break; } } @@ -2192,30 +2191,30 @@ static void sam4_explain_mckr(struct sam4_chip *chip) css = sam4_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2); switch (css & 3) { - case 0: - fin = chip->cfg.slow_freq; - cp = "slowclk"; - break; - case 1: - fin = chip->cfg.mainosc_freq; - cp = "mainosc"; - break; - case 2: - fin = chip->cfg.plla_freq; - cp = "plla"; - break; - case 3: - if (chip->cfg.CKGR_UCKR & (1 << 16)) { - fin = 480 * 1000 * 1000; - cp = "upll"; - } else { - fin = 0; - cp = "upll (*ERROR* UPLL is disabled)"; - } - break; - default: - assert(0); - break; + case 0: + fin = chip->cfg.slow_freq; + cp = "slowclk"; + break; + case 1: + fin = chip->cfg.mainosc_freq; + cp = "mainosc"; + break; + case 2: + fin = chip->cfg.plla_freq; + cp = "plla"; + break; + case 3: + if (chip->cfg.CKGR_UCKR & (1 << 16)) { + fin = 480 * 1000 * 1000; + cp = "upll"; + } else { + fin = 0; + cp = "upll (*ERROR* UPLL is disabled)"; + } + break; + default: + assert(0); + break; } LOG_USER("%s (%3.03f Mhz)", @@ -2223,41 +2222,41 @@ static void sam4_explain_mckr(struct sam4_chip *chip) _tomhz(fin)); pres = sam4_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3); switch (pres & 0x07) { - case 0: - pdiv = 1; - cp = "selected clock"; - break; - case 1: - pdiv = 2; - cp = "clock/2"; - break; - case 2: - pdiv = 4; - cp = "clock/4"; - break; - case 3: - pdiv = 8; - cp = "clock/8"; - break; - case 4: - pdiv = 16; - cp = "clock/16"; - break; - case 5: - pdiv = 32; - cp = "clock/32"; - break; - case 6: - pdiv = 64; - cp = "clock/64"; - break; - case 7: - pdiv = 6; - cp = "clock/6"; - break; - default: - assert(0); - break; + case 0: + pdiv = 1; + cp = "selected clock"; + break; + case 1: + pdiv = 2; + cp = "clock/2"; + break; + case 2: + pdiv = 4; + cp = "clock/4"; + break; + case 3: + pdiv = 8; + cp = "clock/8"; + break; + case 4: + pdiv = 16; + cp = "clock/16"; + break; + case 5: + pdiv = 32; + cp = "clock/32"; + break; + case 6: + pdiv = 64; + cp = "clock/64"; + break; + case 7: + pdiv = 6; + cp = "clock/6"; + break; + default: + assert(0); + break; } LOG_USER("(%s)", cp); fin = fin / pdiv; @@ -2504,32 +2503,32 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command) } switch (bank->base) { - /* at91sam4s series only has bank 0*/ - /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/ - case FLASH_BANK_BASE_S: - case FLASH_BANK_BASE_C: - bank->driver_priv = &chip->details.bank[0]; - bank->bank_number = 0; - chip->details.bank[0].chip = chip; - chip->details.bank[0].bank = bank; - break; - - /* Bank 1 of at91sam4sd/at91sam4c32 series */ - case FLASH_BANK1_BASE_1024K_SD: - case FLASH_BANK1_BASE_2048K_SD: - case FLASH_BANK1_BASE_C32: - bank->driver_priv = &chip->details.bank[1]; - bank->bank_number = 1; - chip->details.bank[1].chip = chip; - chip->details.bank[1].bank = bank; - break; - - default: - LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x" - "[at91sam4s series] )", - bank->base, - FLASH_BANK_BASE_S); - return ERROR_FAIL; + /* at91sam4s series only has bank 0*/ + /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/ + case FLASH_BANK_BASE_S: + case FLASH_BANK_BASE_C: + bank->driver_priv = &chip->details.bank[0]; + bank->bank_number = 0; + chip->details.bank[0].chip = chip; + chip->details.bank[0].bank = bank; + break; + + /* Bank 1 of at91sam4sd/at91sam4c32 series */ + case FLASH_BANK1_BASE_1024K_SD: + case FLASH_BANK1_BASE_2048K_SD: + case FLASH_BANK1_BASE_C32: + bank->driver_priv = &chip->details.bank[1]; + bank->bank_number = 1; + chip->details.bank[1].chip = chip; + chip->details.bank[1].bank = bank; + break; + + default: + LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x" + "[at91sam4s series] )", + bank->base, + FLASH_BANK_BASE_S); + return ERROR_FAIL; } /* we initialize after probing. */ @@ -3122,22 +3121,22 @@ COMMAND_HANDLER(sam4_handle_gpnvm_command) } switch (CMD_ARGC) { - case 0: - goto showall; - case 1: + case 0: + goto showall; + case 1: + who = -1; + break; + case 2: + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { who = -1; - break; - case 2: - if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { - who = -1; - } else { - uint32_t v32; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); - who = v32; - } - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + } else { + uint32_t v32; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); + who = v32; + } + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (strcmp("show", CMD_ARGV[0]) == 0) { @@ -3189,26 +3188,26 @@ COMMAND_HANDLER(sam4_handle_slowclk_command) return ERROR_OK; switch (CMD_ARGC) { - case 0: - /* show */ - break; - case 1: - { - /* set */ - uint32_t v; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); - if (v > 200000) { - /* absurd slow clock of 200Khz? */ - command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); - return ERROR_COMMAND_SYNTAX_ERROR; - } - chip->cfg.slow_freq = v; - break; - } - default: - /* error */ - command_print(CMD, "Too many parameters"); + case 0: + /* show */ + break; + case 1: + { + /* set */ + uint32_t v; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v); + if (v > 200000) { + /* absurd slow clock of 200Khz? */ + command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v)); return ERROR_COMMAND_SYNTAX_ERROR; + } + chip->cfg.slow_freq = v; + break; + } + default: + /* error */ + command_print(CMD, "Too many parameters"); + return ERROR_COMMAND_SYNTAX_ERROR; } command_print(CMD, "Slowclk freq: %d.%03dkhz", (int)(chip->cfg.slow_freq / 1000), diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c index ddf42a8c5f..1db15377eb 100644 --- a/src/flash/nor/at91sam4l.c +++ b/src/flash/nor/at91sam4l.c @@ -282,19 +282,19 @@ static int sam4l_probe(struct flash_bank *bank) chip->ram_kb = sam4l_ram_sizes[0xF & (id >> 16)]; switch (0xF & (id >> 8)) { - case 0x07: - chip->flash_kb = 128; - break; - case 0x09: - chip->flash_kb = 256; - break; - case 0x0A: - chip->flash_kb = 512; - break; - default: - LOG_ERROR("Unknown flash size (chip ID is %08" PRIx32 "), assuming 128K", id); - chip->flash_kb = 128; - break; + case 0x07: + chip->flash_kb = 128; + break; + case 0x09: + chip->flash_kb = 256; + break; + case 0x0A: + chip->flash_kb = 512; + break; + default: + LOG_ERROR("Unknown flash size (chip ID is %08" PRIx32 "), assuming 128K", id); + chip->flash_kb = 128; + break; } /* Retrieve the Flash parameters */ diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c index d06c9451ce..316596e6e2 100644 --- a/src/flash/nor/at91sam7.c +++ b/src/flash/nor/at91sam7.c @@ -193,41 +193,41 @@ static void at91sam7_read_clock_info(struct flash_bank *bank) at91sam7_info->mck_valid = 0; at91sam7_info->mck_freq = 0; switch (mckr & PMC_MCKR_CSS) { - case 0: /* Slow Clock */ + case 0: /* Slow Clock */ + at91sam7_info->mck_valid = 1; + tmp = RC_FREQ; + break; + + case 1: /* Main Clock */ + if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { at91sam7_info->mck_valid = 1; - tmp = RC_FREQ; - break; - - case 1: /* Main Clock */ - if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { - at91sam7_info->mck_valid = 1; - tmp = RC_FREQ / 16ul * (mcfr & 0xffff); - } else if (at91sam7_info->ext_freq != 0) { - at91sam7_info->mck_valid = 1; - tmp = at91sam7_info->ext_freq; - } - break; - - case 2: /* Reserved */ - break; - - case 3: /* PLL Clock */ - if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { - target_read_u32(target, CKGR_PLLR, &pllr); - if (!(pllr & CKGR_PLLR_DIV)) - break; /* 0 Hz */ - at91sam7_info->mck_valid = 1; - mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); - /* Integer arithmetic should have sufficient precision - * as long as PLL is properly configured. */ - tmp = mainfreq / (pllr & CKGR_PLLR_DIV)* - (((pllr & CKGR_PLLR_MUL) >> 16) + 1); - } else if ((at91sam7_info->ext_freq != 0) && ((pllr & CKGR_PLLR_DIV) != 0)) { - at91sam7_info->mck_valid = 1; - tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)* - (((pllr & CKGR_PLLR_MUL) >> 16) + 1); - } - break; + tmp = RC_FREQ / 16ul * (mcfr & 0xffff); + } else if (at91sam7_info->ext_freq != 0) { + at91sam7_info->mck_valid = 1; + tmp = at91sam7_info->ext_freq; + } + break; + + case 2: /* Reserved */ + break; + + case 3: /* PLL Clock */ + if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { + target_read_u32(target, CKGR_PLLR, &pllr); + if (!(pllr & CKGR_PLLR_DIV)) + break; /* 0 Hz */ + at91sam7_info->mck_valid = 1; + mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); + /* Integer arithmetic should have sufficient precision + * as long as PLL is properly configured. */ + tmp = mainfreq / (pllr & CKGR_PLLR_DIV) * + (((pllr & CKGR_PLLR_MUL) >> 16) + 1); + } else if ((at91sam7_info->ext_freq != 0) && ((pllr & CKGR_PLLR_DIV) != 0)) { + at91sam7_info->mck_valid = 1; + tmp = at91sam7_info->ext_freq / (pllr & CKGR_PLLR_DIV) * + (((pllr & CKGR_PLLR_MUL) >> 16) + 1); + } + break; } /* Prescaler adjust */ @@ -415,130 +415,130 @@ static int at91sam7_read_part_info(struct flash_bank *bank) /* check flash size */ switch ((cidr >> 8)&0x000F) { - case FLASH_SIZE_8KB: - break; - - case FLASH_SIZE_16KB: - banks_num = 1; - sectors_num = 8; - pages_per_sector = 32; - page_size = 64; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S161/16"; - } - break; - - case FLASH_SIZE_32KB: - banks_num = 1; - sectors_num = 8; - pages_per_sector = 32; - page_size = 128; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S321/32"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE32"; - } - break; - - case FLASH_SIZE_64KB: - banks_num = 1; - sectors_num = 16; - pages_per_sector = 32; - page_size = 128; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S64"; - } - break; - - case FLASH_SIZE_128KB: - banks_num = 1; - sectors_num = 8; - pages_per_sector = 64; - page_size = 256; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S128"; - } - if (arch == 0x71) { - num_nvmbits = 3; - target_name_t = "AT91SAM7XC128"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE128"; - } - if (arch == 0x75) { - num_nvmbits = 3; - target_name_t = "AT91SAM7X128"; - } - break; - - case FLASH_SIZE_256KB: - banks_num = 1; - sectors_num = 16; - pages_per_sector = 64; - page_size = 256; - base_address = 0x00100000; - if (arch == 0x60) { - num_nvmbits = 3; - target_name_t = "AT91SAM7A3"; - } - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S256"; - } - if (arch == 0x71) { - num_nvmbits = 3; - target_name_t = "AT91SAM7XC256"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE256"; - } - if (arch == 0x75) { - num_nvmbits = 3; - target_name_t = "AT91SAM7X256"; - } - break; - - case FLASH_SIZE_512KB: - banks_num = 2; - sectors_num = 16; - pages_per_sector = 64; - page_size = 256; - base_address = 0x00100000; - if (arch == 0x70) { - num_nvmbits = 2; - target_name_t = "AT91SAM7S512"; - } - if (arch == 0x71) { - num_nvmbits = 3; - target_name_t = "AT91SAM7XC512"; - } - if (arch == 0x72) { - num_nvmbits = 3; - target_name_t = "AT91SAM7SE512"; - } - if (arch == 0x75) { - num_nvmbits = 3; - target_name_t = "AT91SAM7X512"; - } - break; + case FLASH_SIZE_8KB: + break; + + case FLASH_SIZE_16KB: + banks_num = 1; + sectors_num = 8; + pages_per_sector = 32; + page_size = 64; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S161/16"; + } + break; + + case FLASH_SIZE_32KB: + banks_num = 1; + sectors_num = 8; + pages_per_sector = 32; + page_size = 128; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S321/32"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE32"; + } + break; + + case FLASH_SIZE_64KB: + banks_num = 1; + sectors_num = 16; + pages_per_sector = 32; + page_size = 128; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S64"; + } + break; + + case FLASH_SIZE_128KB: + banks_num = 1; + sectors_num = 8; + pages_per_sector = 64; + page_size = 256; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S128"; + } + if (arch == 0x71) { + num_nvmbits = 3; + target_name_t = "AT91SAM7XC128"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE128"; + } + if (arch == 0x75) { + num_nvmbits = 3; + target_name_t = "AT91SAM7X128"; + } + break; + + case FLASH_SIZE_256KB: + banks_num = 1; + sectors_num = 16; + pages_per_sector = 64; + page_size = 256; + base_address = 0x00100000; + if (arch == 0x60) { + num_nvmbits = 3; + target_name_t = "AT91SAM7A3"; + } + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S256"; + } + if (arch == 0x71) { + num_nvmbits = 3; + target_name_t = "AT91SAM7XC256"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE256"; + } + if (arch == 0x75) { + num_nvmbits = 3; + target_name_t = "AT91SAM7X256"; + } + break; + + case FLASH_SIZE_512KB: + banks_num = 2; + sectors_num = 16; + pages_per_sector = 64; + page_size = 256; + base_address = 0x00100000; + if (arch == 0x70) { + num_nvmbits = 2; + target_name_t = "AT91SAM7S512"; + } + if (arch == 0x71) { + num_nvmbits = 3; + target_name_t = "AT91SAM7XC512"; + } + if (arch == 0x72) { + num_nvmbits = 3; + target_name_t = "AT91SAM7SE512"; + } + if (arch == 0x75) { + num_nvmbits = 3; + target_name_t = "AT91SAM7X512"; + } + break; - case FLASH_SIZE_1024KB: - break; + case FLASH_SIZE_1024KB: + break; - case FLASH_SIZE_2048KB: - break; + case FLASH_SIZE_2048KB: + break; } if (strcmp(target_name_t, "Unknown") == 0) { diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c index 85a4384200..782c9e8e8e 100644 --- a/src/flash/nor/atsamv.c +++ b/src/flash/nor/atsamv.c @@ -138,21 +138,21 @@ static int samv_erase_pages(struct target *target, { uint8_t erase_pages; switch (num_pages) { - case 4: - erase_pages = 0x00; - break; - case 8: - erase_pages = 0x01; - break; - case 16: - erase_pages = 0x02; - break; - case 32: - erase_pages = 0x03; - break; - default: - erase_pages = 0x00; - break; + case 4: + erase_pages = 0x00; + break; + case 8: + erase_pages = 0x01; + break; + case 16: + erase_pages = 0x02; + break; + case 32: + erase_pages = 0x03; + break; + default: + erase_pages = 0x00; + break; } /* SAMV_EFC_FCMD_EPA @@ -320,18 +320,18 @@ static int samv_probe(struct flash_bank *bank) uint8_t nvm_size_code = (device_id >> 8) & 0xf; switch (nvm_size_code) { - case 10: - bank->size = 512 * 1024; - break; - case 12: - bank->size = 1024 * 1024; - break; - case 14: - bank->size = 2048 * 1024; - break; - default: - LOG_ERROR("unrecognized flash size code: %d", nvm_size_code); - return ERROR_FAIL; + case 10: + bank->size = 512 * 1024; + break; + case 12: + bank->size = 1024 * 1024; + break; + case 14: + bank->size = 2048 * 1024; + break; + default: + LOG_ERROR("unrecognized flash size code: %d", nvm_size_code); + return ERROR_FAIL; } struct samv_flash_bank *samv_info = bank->driver_priv; @@ -600,22 +600,22 @@ COMMAND_HANDLER(samv_handle_gpnvm_command) int who = 0; switch (CMD_ARGC) { - case 0: - goto showall; - case 1: + case 0: + goto showall; + case 1: + who = -1; + break; + case 2: + if (!strcmp(CMD_ARGV[0], "show") && !strcmp(CMD_ARGV[1], "all")) { who = -1; - break; - case 2: - if (!strcmp(CMD_ARGV[0], "show") && !strcmp(CMD_ARGV[1], "all")) { - who = -1; - } else { - uint32_t v32; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); - who = v32; - } - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + } else { + uint32_t v32; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); + who = v32; + } + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } unsigned int v = 0; diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c index 54d61421ce..e97f1ba137 100644 --- a/src/flash/nor/cc26xx.c +++ b/src/flash/nor/cc26xx.c @@ -51,22 +51,22 @@ static uint32_t cc26xx_device_type(uint32_t icepick_id, uint32_t user_id) uint32_t device_type = 0; switch (icepick_id & ICEPICK_ID_MASK) { - case CC26X0_ICEPICK_ID: - device_type = CC26X0_TYPE; - break; - case CC26X1_ICEPICK_ID: - device_type = CC26X1_TYPE; - break; - case CC13X0_ICEPICK_ID: - device_type = CC13X0_TYPE; - break; - case CC13X2_CC26X2_ICEPICK_ID: - default: - if ((user_id & USER_ID_CC13_MASK) != 0) - device_type = CC13X2_TYPE; - else - device_type = CC26X2_TYPE; - break; + case CC26X0_ICEPICK_ID: + device_type = CC26X0_TYPE; + break; + case CC26X1_ICEPICK_ID: + device_type = CC26X1_TYPE; + break; + case CC13X0_ICEPICK_ID: + device_type = CC13X0_TYPE; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + if ((user_id & USER_ID_CC13_MASK) != 0) + device_type = CC13X2_TYPE; + else + device_type = CC26X2_TYPE; + break; } return device_type; @@ -77,17 +77,17 @@ static uint32_t cc26xx_sector_length(uint32_t icepick_id) uint32_t sector_length; switch (icepick_id & ICEPICK_ID_MASK) { - case CC26X0_ICEPICK_ID: - case CC26X1_ICEPICK_ID: - case CC13X0_ICEPICK_ID: - /* Chameleon family device */ - sector_length = CC26X0_SECTOR_LENGTH; - break; - case CC13X2_CC26X2_ICEPICK_ID: - default: - /* Agama family device */ - sector_length = CC26X2_SECTOR_LENGTH; - break; + case CC26X0_ICEPICK_ID: + case CC26X1_ICEPICK_ID: + case CC13X0_ICEPICK_ID: + /* Chameleon family device */ + sector_length = CC26X0_SECTOR_LENGTH; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + /* Agama family device */ + sector_length = CC26X2_SECTOR_LENGTH; + break; } return sector_length; @@ -427,31 +427,31 @@ static int cc26xx_probe(struct flash_bank *bank) /* Set up appropriate flash helper algorithm */ switch (cc26xx_bank->icepick_id & ICEPICK_ID_MASK) { - case CC26X0_ICEPICK_ID: - case CC26X1_ICEPICK_ID: - case CC13X0_ICEPICK_ID: - /* Chameleon family device */ - cc26xx_bank->algo_code = cc26x0_algo; - cc26xx_bank->algo_size = sizeof(cc26x0_algo); - cc26xx_bank->algo_working_size = CC26X0_WORKING_SIZE; - cc26xx_bank->buffer_addr[0] = CC26X0_ALGO_BUFFER_0; - cc26xx_bank->buffer_addr[1] = CC26X0_ALGO_BUFFER_1; - cc26xx_bank->params_addr[0] = CC26X0_ALGO_PARAMS_0; - cc26xx_bank->params_addr[1] = CC26X0_ALGO_PARAMS_1; - max_sectors = CC26X0_MAX_SECTORS; - break; - case CC13X2_CC26X2_ICEPICK_ID: - default: - /* Agama family device */ - cc26xx_bank->algo_code = cc26x2_algo; - cc26xx_bank->algo_size = sizeof(cc26x2_algo); - cc26xx_bank->algo_working_size = CC26X2_WORKING_SIZE; - cc26xx_bank->buffer_addr[0] = CC26X2_ALGO_BUFFER_0; - cc26xx_bank->buffer_addr[1] = CC26X2_ALGO_BUFFER_1; - cc26xx_bank->params_addr[0] = CC26X2_ALGO_PARAMS_0; - cc26xx_bank->params_addr[1] = CC26X2_ALGO_PARAMS_1; - max_sectors = CC26X2_MAX_SECTORS; - break; + case CC26X0_ICEPICK_ID: + case CC26X1_ICEPICK_ID: + case CC13X0_ICEPICK_ID: + /* Chameleon family device */ + cc26xx_bank->algo_code = cc26x0_algo; + cc26xx_bank->algo_size = sizeof(cc26x0_algo); + cc26xx_bank->algo_working_size = CC26X0_WORKING_SIZE; + cc26xx_bank->buffer_addr[0] = CC26X0_ALGO_BUFFER_0; + cc26xx_bank->buffer_addr[1] = CC26X0_ALGO_BUFFER_1; + cc26xx_bank->params_addr[0] = CC26X0_ALGO_PARAMS_0; + cc26xx_bank->params_addr[1] = CC26X0_ALGO_PARAMS_1; + max_sectors = CC26X0_MAX_SECTORS; + break; + case CC13X2_CC26X2_ICEPICK_ID: + default: + /* Agama family device */ + cc26xx_bank->algo_code = cc26x2_algo; + cc26xx_bank->algo_size = sizeof(cc26x2_algo); + cc26xx_bank->algo_working_size = CC26X2_WORKING_SIZE; + cc26xx_bank->buffer_addr[0] = CC26X2_ALGO_BUFFER_0; + cc26xx_bank->buffer_addr[1] = CC26X2_ALGO_BUFFER_1; + cc26xx_bank->params_addr[0] = CC26X2_ALGO_PARAMS_0; + cc26xx_bank->params_addr[1] = CC26X2_ALGO_PARAMS_1; + max_sectors = CC26X2_MAX_SECTORS; + break; } retval = target_read_u32(target, CC26XX_FLASH_SIZE_INFO, &value); @@ -505,25 +505,25 @@ static int cc26xx_info(struct flash_bank *bank, struct command_invocation *cmd) const char *device; switch (cc26xx_bank->device_type) { - case CC26X0_TYPE: - device = "CC26x0"; - break; - case CC26X1_TYPE: - device = "CC26x1"; - break; - case CC13X0_TYPE: - device = "CC13x0"; - break; - case CC13X2_TYPE: - device = "CC13x2"; - break; - case CC26X2_TYPE: - device = "CC26x2"; - break; - case CC26XX_NO_TYPE: - default: - device = "Unrecognized"; - break; + case CC26X0_TYPE: + device = "CC26x0"; + break; + case CC26X1_TYPE: + device = "CC26x1"; + break; + case CC13X0_TYPE: + device = "CC13x0"; + break; + case CC13X2_TYPE: + device = "CC13x2"; + break; + case CC26X2_TYPE: + device = "CC26x2"; + break; + case CC26XX_NO_TYPE: + default: + device = "Unrecognized"; + break; } command_print_sameline(cmd, diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index 2a15e49132..be10d5b2a2 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -945,14 +945,14 @@ int cfi_erase(struct flash_bank *bank, unsigned int first, return ERROR_FLASH_BANK_NOT_PROBED; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_erase(bank, first, last); - case 2: - return cfi_spansion_erase(bank, first, last); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_erase(bank, first, last); + case 2: + return cfi_spansion_erase(bank, first, last); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_OK; @@ -1084,12 +1084,12 @@ int cfi_protect(struct flash_bank *bank, int set, unsigned int first, return ERROR_FLASH_BANK_NOT_PROBED; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_protect(bank, set, first, last); - default: - LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id); - return ERROR_OK; + case 1: + case 3: + return cfi_intel_protect(bank, set, first, last); + default: + LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id); + return ERROR_OK; } } @@ -1100,16 +1100,16 @@ static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd) uint8_t buf[CFI_MAX_BUS_WIDTH]; cfi_command(bank, cmd, buf); switch (bank->bus_width) { - case 1: - return buf[0]; - case 2: - return target_buffer_get_u16(target, buf); - case 4: - return target_buffer_get_u32(target, buf); - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); - return 0; + case 1: + return buf[0]; + case 2: + return target_buffer_get_u16(target, buf); + case 4: + return target_buffer_get_u32(target, buf); + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return 0; } } @@ -1214,22 +1214,22 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer, /* prepare algorithm code for target endian */ switch (bank->bus_width) { - case 1: - target_code_src = word_8_code; - target_code_size = sizeof(word_8_code); - break; - case 2: - target_code_src = word_16_code; - target_code_size = sizeof(word_16_code); - break; - case 4: - target_code_src = word_32_code; - target_code_size = sizeof(word_32_code); - break; - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + case 1: + target_code_src = word_8_code; + target_code_size = sizeof(word_8_code); + break; + case 2: + target_code_src = word_16_code; + target_code_size = sizeof(word_16_code); + break; + case 4: + target_code_src = word_32_code; + target_code_size = sizeof(word_32_code); + break; + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* flash write code */ @@ -1448,22 +1448,22 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, const uint8_t const uint32_t *target_code_src = NULL; switch (bank->bus_width) { - case 2: - /* Check for DQ5 support */ - if (cfi_info->status_poll_mask & (1 << 5)) { - target_code_src = mips_word_16_code; - target_code_size = sizeof(mips_word_16_code); - } else { - LOG_ERROR("Need DQ5 support"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - /* target_code_src = mips_word_16_code_dq7only; */ - /* target_code_size = sizeof(mips_word_16_code_dq7only); */ - } - break; - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); + case 2: + /* Check for DQ5 support */ + if (cfi_info->status_poll_mask & (1 << 5)) { + target_code_src = mips_word_16_code; + target_code_size = sizeof(mips_word_16_code); + } else { + LOG_ERROR("Need DQ5 support"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + /* target_code_src = mips_word_16_code_dq7only; */ + /* target_code_size = sizeof(mips_word_16_code_dq7only); */ + } + break; + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* flash write code */ @@ -1800,49 +1800,49 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff const uint32_t *target_code_src = NULL; switch (bank->bus_width) { - case 1: + case 1: + if (is_armv7m(target_to_armv7m(target))) { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; + } + target_code_src = armv4_5_word_8_code; + target_code_size = sizeof(armv4_5_word_8_code); + break; + case 2: + /* Check for DQ5 support */ + if (cfi_info->status_poll_mask & (1 << 5)) { if (is_armv7m(target_to_armv7m(target))) { - LOG_ERROR("Unknown ARM architecture"); - return ERROR_FAIL; + /* armv7m target */ + target_code_src = armv7m_word_16_code; + target_code_size = sizeof(armv7m_word_16_code); + } else { /* armv4_5 target */ + target_code_src = armv4_5_word_16_code; + target_code_size = sizeof(armv4_5_word_16_code); } - target_code_src = armv4_5_word_8_code; - target_code_size = sizeof(armv4_5_word_8_code); - break; - case 2: - /* Check for DQ5 support */ - if (cfi_info->status_poll_mask & (1 << 5)) { - if (is_armv7m(target_to_armv7m(target))) { - /* armv7m target */ - target_code_src = armv7m_word_16_code; - target_code_size = sizeof(armv7m_word_16_code); - } else { /* armv4_5 target */ - target_code_src = armv4_5_word_16_code; - target_code_size = sizeof(armv4_5_word_16_code); - } - } else { - /* No DQ5 support. Use DQ7 DATA# polling only. */ - if (is_armv7m(target_to_armv7m(target))) { - /* armv7m target */ - target_code_src = armv7m_word_16_code_dq7only; - target_code_size = sizeof(armv7m_word_16_code_dq7only); - } else { /* armv4_5 target */ - target_code_src = armv4_5_word_16_code_dq7only; - target_code_size = sizeof(armv4_5_word_16_code_dq7only); - } - } - break; - case 4: + } else { + /* No DQ5 support. Use DQ7 DATA# polling only. */ if (is_armv7m(target_to_armv7m(target))) { - LOG_ERROR("Unknown ARM architecture"); - return ERROR_FAIL; + /* armv7m target */ + target_code_src = armv7m_word_16_code_dq7only; + target_code_size = sizeof(armv7m_word_16_code_dq7only); + } else { /* armv4_5 target */ + target_code_src = armv4_5_word_16_code_dq7only; + target_code_size = sizeof(armv4_5_word_16_code_dq7only); } - target_code_src = armv4_5_word_32_code; - target_code_size = sizeof(armv4_5_word_32_code); - break; - default: - LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", - bank->bus_width); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + break; + case 4: + if (is_armv7m(target_to_armv7m(target))) { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; + } + target_code_src = armv4_5_word_32_code; + target_code_size = sizeof(armv4_5_word_32_code); + break; + default: + LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes", + bank->bus_width); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* flash write code */ @@ -2172,14 +2172,14 @@ int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address) struct cfi_flash_bank *cfi_info = bank->driver_priv; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_write_word(bank, word, address); - case 2: - return cfi_spansion_write_word(bank, word, address); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_write_word(bank, word, address); + case 2: + return cfi_spansion_write_word(bank, word, address); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_FLASH_OPERATION_FAILED; @@ -2197,14 +2197,14 @@ static int cfi_write_words(struct flash_bank *bank, const uint8_t *word, } switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_write_words(bank, word, wordcount, address); - case 2: - return cfi_spansion_write_words(bank, word, wordcount, address); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_write_words(bank, word, wordcount, address); + case 2: + return cfi_spansion_write_words(bank, word, wordcount, address); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_FLASH_OPERATION_FAILED; @@ -2345,18 +2345,18 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of /* handle blocks of bus_size aligned bytes */ blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */ switch (cfi_info->pri_id) { - /* try block writes (fails without working area) */ - case 1: - case 3: - retval = cfi_intel_write_block(bank, buffer, write_p, blk_count); - break; - case 2: - retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - retval = ERROR_FLASH_OPERATION_FAILED; - break; + /* try block writes (fails without working area) */ + case 1: + case 3: + retval = cfi_intel_write_block(bank, buffer, write_p, blk_count); + break; + case 2: + retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + retval = ERROR_FLASH_OPERATION_FAILED; + break; } if (retval == ERROR_OK) { /* Increment pointers and decrease count on successful block write */ @@ -2581,22 +2581,22 @@ int cfi_probe(struct flash_bank *bank) if (retval != ERROR_OK) return retval; switch (bank->chip_width) { - case 1: - cfi_info->manufacturer = *value_buf0; - cfi_info->device_id = *value_buf1; - break; - case 2: - cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0); - cfi_info->device_id = target_buffer_get_u16(target, value_buf1); - break; - case 4: - cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0); - cfi_info->device_id = target_buffer_get_u32(target, value_buf1); - break; - default: - LOG_ERROR("Unsupported bank chipwidth %u, can't probe memory", - bank->chip_width); - return ERROR_FLASH_OPERATION_FAILED; + case 1: + cfi_info->manufacturer = *value_buf0; + cfi_info->device_id = *value_buf1; + break; + case 2: + cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0); + cfi_info->device_id = target_buffer_get_u16(target, value_buf1); + break; + case 4: + cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0); + cfi_info->device_id = target_buffer_get_u32(target, value_buf1); + break; + default: + LOG_ERROR("Unsupported bank chipwidth %u, can't probe memory", + bank->chip_width); + return ERROR_FLASH_OPERATION_FAILED; } LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", @@ -2734,25 +2734,25 @@ int cfi_probe(struct flash_bank *bank) * the sector layout to be able to apply fixups */ switch (cfi_info->pri_id) { - /* Intel command set (standard and extended) */ - case 0x0001: - case 0x0003: - cfi_read_intel_pri_ext(bank); - break; - /* AMD/Spansion, Atmel, ... command set */ - case 0x0002: - cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* - *default - *for - *all - *CFI - *flashes - **/ - cfi_read_0002_pri_ext(bank); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + /* Intel command set (standard and extended) */ + case 0x0001: + case 0x0003: + cfi_read_intel_pri_ext(bank); + break; + /* AMD/Spansion, Atmel, ... command set */ + case 0x0002: + cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* + *default + *for + *all + *CFI + *flashes + **/ + cfi_read_0002_pri_ext(bank); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } /* return to read array mode @@ -2798,18 +2798,18 @@ int cfi_probe(struct flash_bank *bank) /* apply fixups depending on the primary command set */ switch (cfi_info->pri_id) { - /* Intel command set (standard and extended) */ - case 0x0001: - case 0x0003: - cfi_fixup(bank, cfi_0001_fixups); - break; - /* AMD/Spansion, Atmel, ... command set */ - case 0x0002: - cfi_fixup(bank, cfi_0002_fixups); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + /* Intel command set (standard and extended) */ + case 0x0001: + case 0x0003: + cfi_fixup(bank, cfi_0001_fixups); + break; + /* AMD/Spansion, Atmel, ... command set */ + case 0x0002: + cfi_fixup(bank, cfi_0002_fixups); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size) { @@ -2939,14 +2939,14 @@ int cfi_protect_check(struct flash_bank *bank) return ERROR_FLASH_BANK_NOT_PROBED; switch (cfi_info->pri_id) { - case 1: - case 3: - return cfi_intel_protect_check(bank); - case 2: - return cfi_spansion_protect_check(bank); - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + return cfi_intel_protect_check(bank); + case 2: + return cfi_spansion_protect_check(bank); + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_OK; @@ -3011,16 +3011,16 @@ int cfi_get_info(struct flash_bank *bank, struct command_invocation *cmd) 1 << cfi_info->max_buf_write_size); switch (cfi_info->pri_id) { - case 1: - case 3: - cfi_intel_info(bank, cmd); - break; - case 2: - cfi_spansion_info(bank, cmd); - break; - default: - LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); - break; + case 1: + case 3: + cfi_intel_info(bank, cmd); + break; + case 2: + cfi_spansion_info(bank, cmd); + break; + default: + LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id); + break; } return ERROR_OK; diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c index f8e0886570..2dac45e79a 100644 --- a/src/flash/nor/efm32.c +++ b/src/flash/nor/efm32.c @@ -88,14 +88,14 @@ enum efm32_bank_index { static int efm32x_get_bank_index(target_addr_t base) { switch (base) { - case EFM32_FLASH_BASE: - return EFM32_BANK_INDEX_MAIN; - case EFM32_MSC_USER_DATA: - return EFM32_BANK_INDEX_USER_DATA; - case EFM32_MSC_LOCK_BITS: - return EFM32_BANK_INDEX_LOCK_BITS; - default: - return ERROR_FAIL; + case EFM32_FLASH_BASE: + return EFM32_BANK_INDEX_MAIN; + case EFM32_MSC_USER_DATA: + return EFM32_BANK_INDEX_USER_DATA; + case EFM32_MSC_LOCK_BITS: + return EFM32_BANK_INDEX_LOCK_BITS; + default: + return ERROR_FAIL; } } @@ -282,14 +282,14 @@ static int efm32x_read_info(struct flash_bank *bank) } switch (efm32_info->family_data->series) { - case 0: - efm32x_info->reg_base = EFM32_MSC_REGBASE; - efm32x_info->reg_lock = EFM32_MSC_REG_LOCK; - break; - case 1: - efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1; - efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1; - break; + case 0: + efm32x_info->reg_base = EFM32_MSC_REGBASE; + efm32x_info->reg_lock = EFM32_MSC_REG_LOCK; + break; + case 1: + efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1; + efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1; + break; } if (efm32_info->family_data->msc_regbase != 0) @@ -662,18 +662,18 @@ static int efm32x_get_page_lock(struct flash_bank *bank, size_t page) uint32_t mask = 0; switch (bank->base) { - case EFM32_FLASH_BASE: - dw = efm32x_info->lb_page[page >> 5]; - mask = 1 << (page & 0x1f); - break; - case EFM32_MSC_USER_DATA: - dw = efm32x_info->lb_page[126]; - mask = 0x1; - break; - case EFM32_MSC_LOCK_BITS: - dw = efm32x_info->lb_page[126]; - mask = 0x2; - break; + case EFM32_FLASH_BASE: + dw = efm32x_info->lb_page[page >> 5]; + mask = 1 << (page & 0x1f); + break; + case EFM32_MSC_USER_DATA: + dw = efm32x_info->lb_page[126]; + mask = 0x1; + break; + case EFM32_MSC_LOCK_BITS: + dw = efm32x_info->lb_page[126]; + mask = 0x2; + break; } return (dw & mask) ? 0 : 1; diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c index 207346f10d..0ac5d81dbd 100644 --- a/src/flash/nor/em357.c +++ b/src/flash/nor/em357.c @@ -670,36 +670,36 @@ static int em357_probe(struct flash_bank *bank) em357_info->probed = false; switch (bank->size) { - case 0x10000: - /* 64k -- 64 1k pages */ - num_pages = 64; - page_size = 1024; - break; - case 0x20000: - /* 128k -- 128 1k pages */ - num_pages = 128; - page_size = 1024; - break; - case 0x30000: - /* 192k -- 96 2k pages */ - num_pages = 96; - page_size = 2048; - break; - case 0x40000: - /* 256k -- 128 2k pages */ - num_pages = 128; - page_size = 2048; - break; - case 0x80000: - /* 512k -- 256 2k pages */ - num_pages = 256; - page_size = 2048; - break; - default: - LOG_WARNING("No size specified for em357 flash driver, assuming 192k!"); - num_pages = 96; - page_size = 2048; - break; + case 0x10000: + /* 64k -- 64 1k pages */ + num_pages = 64; + page_size = 1024; + break; + case 0x20000: + /* 128k -- 128 1k pages */ + num_pages = 128; + page_size = 1024; + break; + case 0x30000: + /* 192k -- 96 2k pages */ + num_pages = 96; + page_size = 2048; + break; + case 0x40000: + /* 256k -- 128 2k pages */ + num_pages = 128; + page_size = 2048; + break; + case 0x80000: + /* 512k -- 256 2k pages */ + num_pages = 256; + page_size = 2048; + break; + default: + LOG_WARNING("No size specified for em357 flash driver, assuming 192k!"); + num_pages = 96; + page_size = 2048; + break; } /* Enable FPEC CLK */ diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c index 85c306bd44..82e68de3fb 100644 --- a/src/flash/nor/kinetis.c +++ b/src/flash/nor/kinetis.c @@ -2145,24 +2145,24 @@ static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip) k_chip->max_flash_prog_size = 512; switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) { - case KINETIS_SDID_S32K_DERIVATE_KXX6: - /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */ - /* Non-Interleaved */ - k_chip->pflash_size = 128 << 10; - k_chip->pflash_sector_size = 2 << 10; - /* Non-Interleaved */ - k_chip->nvm_size = 32 << 10; - k_chip->nvm_sector_size = 2 << 10; - break; - case KINETIS_SDID_S32K_DERIVATE_KXX8: - /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */ - /* Non-Interleaved */ - k_chip->pflash_size = 256 << 10; - k_chip->pflash_sector_size = 2 << 10; - /* Non-Interleaved */ - k_chip->nvm_size = 32 << 10; - k_chip->nvm_sector_size = 2 << 10; - break; + case KINETIS_SDID_S32K_DERIVATE_KXX6: + /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */ + /* Non-Interleaved */ + k_chip->pflash_size = 128 << 10; + k_chip->pflash_sector_size = 2 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 32 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; + case KINETIS_SDID_S32K_DERIVATE_KXX8: + /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */ + /* Non-Interleaved */ + k_chip->pflash_size = 256 << 10; + k_chip->pflash_sector_size = 2 << 10; + /* Non-Interleaved */ + k_chip->nvm_size = 32 << 10; + k_chip->nvm_sector_size = 2 << 10; + break; } break; diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c index 8207504b5f..51d5cb504b 100644 --- a/src/flash/nor/kinetis_ke.c +++ b/src/flash/nor/kinetis_ke.c @@ -238,19 +238,18 @@ static int kinetis_ke_prepare_flash(struct flash_bank *bank) * Trim internal clock */ switch (KINETIS_KE_SRSID_SUBFAMID(kinfo->sim_srsid)) { - - case KINETIS_KE_SRSID_KEX2: - /* Both KE02_20 and KE02_40 should get the same trim value */ - trim_value = 0x4C; - break; - - case KINETIS_KE_SRSID_KEX4: - trim_value = 0x54; - break; - - case KINETIS_KE_SRSID_KEX6: - trim_value = 0x58; - break; + case KINETIS_KE_SRSID_KEX2: + /* Both KE02_20 and KE02_40 should get the same trim value */ + trim_value = 0x4C; + break; + + case KINETIS_KE_SRSID_KEX4: + trim_value = 0x54; + break; + + case KINETIS_KE_SRSID_KEX6: + trim_value = 0x58; + break; } result = target_read_u8(target, ICS_C4, &c4); @@ -293,54 +292,52 @@ static int kinetis_ke_prepare_flash(struct flash_bank *bank) * Configure SIM (bus clock) */ switch (KINETIS_KE_SRSID_SUBFAMID(kinfo->sim_srsid)) { + /* KE02 sub-family operates on SIM_BUSDIV */ + case KINETIS_KE_SRSID_KEX2: + bus_reg_val = 0; + bus_reg_addr = SIM_BUSDIV; + bus_clock = 20000000; + break; + + /* KE04 and KE06 sub-family operates on SIM_CLKDIV + * Clocks are divided by: + * DIV1 = core clock = 48MHz + * DIV2 = bus clock = 24Mhz + * DIV3 = timer clocks + * So we need to configure SIM_CLKDIV, DIV1 and DIV2 value + */ + case KINETIS_KE_SRSID_KEX4: + /* KE04 devices have the SIM_CLKDIV register at a different offset + * depending on the pin count. */ + switch (KINETIS_KE_SRSID_PINCOUNT(kinfo->sim_srsid)) { + /* 16, 20 and 24 pins */ + case 1: + case 2: + case 3: + bus_reg_addr = SIM_CLKDIV_KE04_16_20_24; + break; - /* KE02 sub-family operates on SIM_BUSDIV */ - case KINETIS_KE_SRSID_KEX2: - bus_reg_val = 0; - bus_reg_addr = SIM_BUSDIV; - bus_clock = 20000000; + /* 44, 64 and 80 pins */ + case 5: + case 7: + case 8: + bus_reg_addr = SIM_CLKDIV_KE04_44_64_80; break; - /* KE04 and KE06 sub-family operates on SIM_CLKDIV - * Clocks are divided by: - * DIV1 = core clock = 48MHz - * DIV2 = bus clock = 24Mhz - * DIV3 = timer clocks - * So we need to configure SIM_CLKDIV, DIV1 and DIV2 value - */ - case KINETIS_KE_SRSID_KEX4: - /* KE04 devices have the SIM_CLKDIV register at a different offset - * depending on the pin count. */ - switch (... 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