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[PATCH]: 5e1c312b02 flash: nor: prepare for aligning switch and case statements
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From: <ge...@op...> - 2025-07-25 18:29:03
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This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9033 -- gerrit commit 5e1c312b020acd174db85bddc28ba8d9d3beaf72 Author: Antonio Borneo <bor...@gm...> Date: Sat Jun 28 11:08:18 2025 +0200 flash: nor: prepare for aligning switch and case statements To prepare for aligning switch and case statements, fix in advance some checkpatch error due to existing code: - remove useless parenthesis; - uniform braces around if/else statements, - add space around operators. While there: - put the 'default' case as last in the list; - convert format strings to drop cast. Change-Id: I335b200add75b95bf1e908af39e957b61b617e22 Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index b86a18da75..4042d32dec 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -2571,9 +2571,6 @@ static void sam3_explain_ckgr_mor(struct sam3_chip *chip) chip->cfg.rc_freq = 0; if (rcen) { switch (v) { - default: - chip->cfg.rc_freq = 0; - break; case 0: chip->cfg.rc_freq = 4 * 1000 * 1000; break; @@ -2583,6 +2580,9 @@ static void sam3_explain_ckgr_mor(struct sam3_chip *chip) case 2: chip->cfg.rc_freq = 12 * 1000 * 1000; break; + default: + chip->cfg.rc_freq = 0; + break; } } @@ -3011,25 +3011,11 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command) } switch (bank->base) { - default: - LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x " - "[at91sam3u series] or 0x%08x [at91sam3s series] or " - "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )", - ((unsigned int)(bank->base)), - ((unsigned int)(FLASH_BANK0_BASE_U)), - ((unsigned int)(FLASH_BANK1_BASE_U)), - ((unsigned int)(FLASH_BANK_BASE_S)), - ((unsigned int)(FLASH_BANK_BASE_N)), - ((unsigned int)(FLASH_BANK0_BASE_AX)), - ((unsigned int)(FLASH_BANK1_BASE_256K_AX)), - ((unsigned int)(FLASH_BANK1_BASE_512K_AX))); - return ERROR_FAIL; - /* at91sam3s and at91sam3n series only has bank 0*/ /* at91sam3u and at91sam3ax series has the same address for bank 0*/ case FLASH_BANK_BASE_S: case FLASH_BANK0_BASE_U: - bank->driver_priv = &(chip->details.bank[0]); + bank->driver_priv = &chip->details.bank[0]; bank->bank_number = 0; chip->details.bank[0].chip = chip; chip->details.bank[0].bank = bank; @@ -3039,11 +3025,25 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command) case FLASH_BANK1_BASE_U: case FLASH_BANK1_BASE_256K_AX: case FLASH_BANK1_BASE_512K_AX: - bank->driver_priv = &(chip->details.bank[1]); + bank->driver_priv = &chip->details.bank[1]; bank->bank_number = 1; chip->details.bank[1].chip = chip; chip->details.bank[1].bank = bank; break; + + default: + LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x or 0x%08x " + "[at91sam3u series] or 0x%08x [at91sam3s series] or " + "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )", + bank->base, + FLASH_BANK0_BASE_U, + FLASH_BANK1_BASE_U, + FLASH_BANK_BASE_S, + FLASH_BANK_BASE_N, + FLASH_BANK0_BASE_AX, + FLASH_BANK1_BASE_256K_AX, + FLASH_BANK1_BASE_512K_AX); + return ERROR_FAIL; } /* we initialize after probing. */ @@ -3574,22 +3574,22 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) } switch (CMD_ARGC) { - default: - return ERROR_COMMAND_SYNTAX_ERROR; case 0: goto showall; case 1: who = -1; break; case 2: - if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { who = -1; - else { + } else { uint32_t v32; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); who = v32; } break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (strcmp("show", CMD_ARGV[0]) == 0) { diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index 26a803784d..08f1955778 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -2080,9 +2080,6 @@ static void sam4_explain_ckgr_mor(struct sam4_chip *chip) chip->cfg.rc_freq = 0; if (rcen) { switch (v) { - default: - chip->cfg.rc_freq = 0; - break; case 0: chip->cfg.rc_freq = 4 * 1000 * 1000; break; @@ -2092,6 +2089,9 @@ static void sam4_explain_ckgr_mor(struct sam4_chip *chip) case 2: chip->cfg.rc_freq = 12 * 1000 * 1000; break; + default: + chip->cfg.rc_freq = 0; + break; } } @@ -2504,18 +2504,11 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command) } switch (bank->base) { - default: - LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x" - "[at91sam4s series] )", - ((unsigned int)(bank->base)), - ((unsigned int)(FLASH_BANK_BASE_S))); - return ERROR_FAIL; - /* at91sam4s series only has bank 0*/ /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/ case FLASH_BANK_BASE_S: case FLASH_BANK_BASE_C: - bank->driver_priv = &(chip->details.bank[0]); + bank->driver_priv = &chip->details.bank[0]; bank->bank_number = 0; chip->details.bank[0].chip = chip; chip->details.bank[0].bank = bank; @@ -2525,11 +2518,18 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command) case FLASH_BANK1_BASE_1024K_SD: case FLASH_BANK1_BASE_2048K_SD: case FLASH_BANK1_BASE_C32: - bank->driver_priv = &(chip->details.bank[1]); + bank->driver_priv = &chip->details.bank[1]; bank->bank_number = 1; chip->details.bank[1].chip = chip; chip->details.bank[1].bank = bank; break; + + default: + LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x" + "[at91sam4s series] )", + bank->base, + FLASH_BANK_BASE_S); + return ERROR_FAIL; } /* we initialize after probing. */ @@ -3122,22 +3122,22 @@ COMMAND_HANDLER(sam4_handle_gpnvm_command) } switch (CMD_ARGC) { - default: - return ERROR_COMMAND_SYNTAX_ERROR; case 0: goto showall; case 1: who = -1; break; case 2: - if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) + if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) { who = -1; - else { + } else { uint32_t v32; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); who = v32; } break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (strcmp("show", CMD_ARGV[0]) == 0) { diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c index 86c80765fc..d06c9451ce 100644 --- a/src/flash/nor/at91sam7.c +++ b/src/flash/nor/at91sam7.c @@ -199,8 +199,7 @@ static void at91sam7_read_clock_info(struct flash_bank *bank) break; case 1: /* Main Clock */ - if ((mcfr & CKGR_MCFR_MAINRDY) && - (at91sam7_info->ext_freq == 0)) { + if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { at91sam7_info->mck_valid = 1; tmp = RC_FREQ / 16ul * (mcfr & 0xffff); } else if (at91sam7_info->ext_freq != 0) { @@ -213,8 +212,7 @@ static void at91sam7_read_clock_info(struct flash_bank *bank) break; case 3: /* PLL Clock */ - if ((mcfr & CKGR_MCFR_MAINRDY) && - (at91sam7_info->ext_freq == 0)) { + if ((mcfr & CKGR_MCFR_MAINRDY) && at91sam7_info->ext_freq == 0) { target_read_u32(target, CKGR_PLLR, &pllr); if (!(pllr & CKGR_PLLR_DIV)) break; /* 0 Hz */ @@ -224,8 +222,7 @@ static void at91sam7_read_clock_info(struct flash_bank *bank) * as long as PLL is properly configured. */ tmp = mainfreq / (pllr & CKGR_PLLR_DIV)* (((pllr & CKGR_PLLR_MUL) >> 16) + 1); - } else if ((at91sam7_info->ext_freq != 0) && - ((pllr&CKGR_PLLR_DIV) != 0)) { + } else if ((at91sam7_info->ext_freq != 0) && ((pllr & CKGR_PLLR_DIV) != 0)) { at91sam7_info->mck_valid = 1; tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)* (((pllr & CKGR_PLLR_MUL) >> 16) + 1); diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c index d6d8938b67..85a4384200 100644 --- a/src/flash/nor/atsamv.c +++ b/src/flash/nor/atsamv.c @@ -606,9 +606,9 @@ COMMAND_HANDLER(samv_handle_gpnvm_command) who = -1; break; case 2: - if (!strcmp(CMD_ARGV[0], "show") && !strcmp(CMD_ARGV[1], "all")) + if (!strcmp(CMD_ARGV[0], "show") && !strcmp(CMD_ARGV[1], "all")) { who = -1; - else { + } else { uint32_t v32; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32); who = v32; -- |
