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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1086-ga19294909
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From: openocd-gerrit <ope...@us...> - 2025-07-25 16:39:12
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- Log -----------------------------------------------------------------
commit a192949095b3fc10a3916ee1d52d92d3b019fbea
Author: Nicolas Derumigny <nic...@in...>
Date: Tue Nov 5 15:49:04 2024 +0000
jtag: drivers: xlnx-axi-xvc: Add support for Xilinx XVC over direct bus interface (AXI)
This change allow to use direct mapping of the JTAG interface using
Xilinx Virtual Cable (XVC) over AXI. This merges the existing XVC PCIe
code and the patch proposed by Jeremy Garff
(https://review.openocd.org/c/openocd/+/6594).
This is useful when using on a Zynq/ZynqMP/uBlaze host with direct
access to the debug bridge over AXI. You can then use the debug bridge
Xilinx IP (AXIXVC) to debug a remote device.
Signed-off-by: Nicolas Derumigny <nic...@in...>
Change-Id: I934591b489e30b400b87772b1437e6030440904c
Reviewed-on: https://review.openocd.org/c/openocd/+/8595
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/configure.ac b/configure.ac
index 9bbb2c36a..df94e20b8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -177,8 +177,8 @@ m4_define([REMOTE_BITBANG_ADAPTER],
m4_define([LIBJAYLINK_ADAPTERS],
[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
-m4_define([PCIE_ADAPTERS],
- [[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_XVC]]])
+m4_define([XVC_ADAPTERS],
+ [[[xlnx_xvc], [Xilinx XVC PCIe and AXI drives], [XLNX_XVC]]])
m4_define([SERIAL_PORT_ADAPTERS],
[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
@@ -335,7 +335,7 @@ AC_ARG_ADAPTERS([
JTAG_DPI_ADAPTER,
JTAG_VPI_ADAPTER,
RSHIM_ADAPTER,
- PCIE_ADAPTERS,
+ XVC_ADAPTERS,
LIBJAYLINK_ADAPTERS
],[auto])
@@ -644,7 +644,7 @@ PROCESS_ADAPTERS([DMEM_ADAPTER], ["x$is_linux" = "xyes"], [Linux /dev/mem])
PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs])
PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused])
PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
-PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
+PROCESS_ADAPTERS([XVC_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
[internal error: validation should happen beforehand])
PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_spi_spidev_h" = "xyes"],
@@ -840,7 +840,8 @@ m4_foreach([adapterTuple], [USB1_ADAPTERS,
DMEM_ADAPTER,
SYSFSGPIO_ADAPTER,
REMOTE_BITBANG_ADAPTER,
- LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
+ LIBJAYLINK_ADAPTERS, XVC_ADAPTERS,
+ SERIAL_PORT_ADAPTERS,
LINUXSPIDEV_ADAPTER,
VDEBUG_ADAPTER,
JTAG_DPI_ADAPTER,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6d607d697..90ed9d3b6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -613,6 +613,12 @@ emulation model of target hardware.
@item @b{xlnx_pcie_xvc}
@* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
+@* Link: @url{https://www.xilinx.com/products/intellectual-property/debug-bridge.html}
+
+@item @b{xlnx_axi_xvc}
+@* A JTAG driver exposing JTAG to OpenOCD over AXI-mapped registers.
+@* Link: @url{https://docs.amd.com/r/en-US/pg437-axi-jtag/Introduction}
+@* Link: @url{https://china.xilinx.com/support/documentation/application_notes/xapp1251-xvc-zynq-petalinux.pdf}
@item @b{linuxspidev}
@* A SPI based SWD driver using Linux SPI devices.
@@ -3352,6 +3358,21 @@ The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
@end deffn
@end deffn
+@deffn {Interface Driver} {xlnx_axi_xvc}
+This driver supports the Xilinx JTAG mapping over AXI using the AXI to JTAG
+Converter or the AXI-to-JTAG mode of the debug bridge.
+It is commonly found in Xilinx MPSoC based designs. It allows debugging
+fabric based JTAG/SWD devices such as Cortex-M1/M3 or RISC-V softcores. Access to this
+is exposed via extended capability registers in the AXI-mapped configuration space.
+
+@deffn {Config Command} {xlnx_axi_xvc dev_addr} addr
+Specifies the address of the AXI-mapped registers via parameter @var{addr}.
+
+The correct value for @var{addr} is specified in the "Address Editor" tab
+in Vivado.
+@end deffn
+@end deffn
+
@deffn {Interface Driver} {bcm2835gpio}
This GPIO interface is present in Raspberry Pi 0-4 which is a cheap
single-board computer exposing some GPIOs on its expansion header.
diff --git a/src/jtag/drivers/xlnx-xvc.c b/src/jtag/drivers/xlnx-xvc.c
index 5208e2b87..6b3359538 100644
--- a/src/jtag/drivers/xlnx-xvc.c
+++ b/src/jtag/drivers/xlnx-xvc.c
@@ -1,8 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2019 Google, LLC.
- * Author: Moritz Fischer <mo...@go...>
+ * Copyright (C) 2019 Google, LLC.
+ * Moritz Fischer <mo...@go...>
+ *
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates
+ * Jeremy Garff <jer...@wd...>
+ *
+ * Copyright (C) 2024 Inria
+ * Nicolas Derumigny <nic...@in...>
*/
#ifdef HAVE_CONFIG_H
@@ -11,13 +17,14 @@
#include <stdint.h>
#include <stdlib.h>
-#include <math.h>
#include <unistd.h>
#include <linux/pci.h>
+#include <sys/mman.h>
#include <jtag/interface.h>
-#include <jtag/swd.h>
#include <jtag/commands.h>
+#include <jtag/interface.h>
+#include <jtag/swd.h>
#include <helper/replacements.h>
#include <helper/bits.h>
@@ -28,14 +35,24 @@
#define PCIE_EXT_CAP_LST 0x100
-#define XLNX_XVC_EXT_CAP 0x00
-#define XLNX_XVC_VSEC_HDR 0x04
-#define XLNX_XVC_LEN_REG 0x0C
-#define XLNX_XVC_TMS_REG 0x10
-#define XLNX_XVC_TDX_REG 0x14
+#define XLNX_PCIE_XVC_EXT_CAP 0x00
+#define XLNX_PCIE_XVC_VSEC_HDR 0x04
+#define XLNX_PCIE_XVC_LEN_REG 0x0C
+#define XLNX_PCIE_XVC_TMS_REG 0x10
+#define XLNX_PCIE_XVC_TDX_REG 0x14
+
+#define XLNX_PCIE_XVC_CAP_SIZE 0x20
+#define XLNX_PCIE_XVC_VSEC_ID 0x8
+
+#define XLNX_AXI_XVC_LEN_REG 0x00
+#define XLNX_AXI_XVC_TMS_REG 0x04
+#define XLNX_AXI_XVC_TDI_REG 0x08
+#define XLNX_AXI_XVC_TDO_REG 0x0c
+#define XLNX_AXI_XVC_CTRL_REG 0x10
+#define XLNX_AXI_XVC_MAX_REG 0x18
+
+#define XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK 0x01
-#define XLNX_XVC_CAP_SIZE 0x20
-#define XLNX_XVC_VSEC_ID 0x8
#define XLNX_XVC_MAX_BITS 0x20
#define MASK_ACK(x) (((x) >> 9) & 0x7)
@@ -47,8 +64,23 @@ struct xlnx_pcie_xvc {
char *device;
};
+struct xlnx_axi_xvc {
+ int fd;
+ uint32_t *base;
+ char *device_addr;
+ // Defaults to `/dev/mem` if NULL
+ char *device_file;
+};
+
+enum xlnx_xvc_type_t {
+ PCIE,
+ AXI
+};
+
static struct xlnx_pcie_xvc xlnx_pcie_xvc_state;
static struct xlnx_pcie_xvc *xlnx_pcie_xvc = &xlnx_pcie_xvc_state;
+static struct xlnx_axi_xvc xlnx_axi_xvc_state;
+static struct xlnx_axi_xvc *xlnx_axi_xvc = &xlnx_axi_xvc_state;
static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
{
@@ -60,9 +92,9 @@ static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
* space accessor functions
*/
err = pread(xlnx_pcie_xvc->fd, &res, sizeof(res),
- xlnx_pcie_xvc->offset + offset);
+ xlnx_pcie_xvc->offset + offset);
if (err != sizeof(res)) {
- LOG_ERROR("Failed to read offset %x", offset);
+ LOG_ERROR("Failed to read offset 0x%x", offset);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -72,6 +104,19 @@ static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
return ERROR_OK;
}
+static int xlnx_axi_xvc_read_reg(const int offset, uint32_t *val)
+{
+ uintptr_t b = ((uintptr_t)xlnx_axi_xvc->base) + offset;
+ volatile uint32_t *w = (uint32_t *)b;
+
+ if (val) {
+ __atomic_thread_fence(__ATOMIC_SEQ_CST);
+ *val = *w;
+ }
+
+ return ERROR_OK;
+}
+
static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
{
int err;
@@ -81,9 +126,9 @@ static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
* space accessor functions
*/
err = pwrite(xlnx_pcie_xvc->fd, &val, sizeof(val),
- xlnx_pcie_xvc->offset + offset);
+ xlnx_pcie_xvc->offset + offset);
if (err != sizeof(val)) {
- LOG_ERROR("Failed to write offset: %x with value: %" PRIx32,
+ LOG_ERROR("Failed to write offset: 0x%x with value: %" PRIx32,
offset, val);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -91,37 +136,117 @@ static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
return ERROR_OK;
}
+static int xlnx_axi_xvc_write_reg(const int offset, const uint32_t val)
+{
+ uintptr_t b = ((uintptr_t)xlnx_axi_xvc->base) + offset;
+ volatile uint32_t *w = (uint32_t *)b;
+
+ *w = val;
+ __atomic_thread_fence(__ATOMIC_SEQ_CST);
+
+ return ERROR_OK;
+}
+
static int xlnx_pcie_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
uint32_t *tdo)
{
int err;
- err = xlnx_pcie_xvc_write_reg(XLNX_XVC_LEN_REG, num_bits);
+ err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_LEN_REG, num_bits);
if (err != ERROR_OK)
return err;
- err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TMS_REG, tms);
+ err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_TMS_REG, tms);
if (err != ERROR_OK)
return err;
- err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TDX_REG, tdi);
+ err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_TDX_REG, tdi);
if (err != ERROR_OK)
return err;
- err = xlnx_pcie_xvc_read_reg(XLNX_XVC_TDX_REG, tdo);
+ err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_TDX_REG, tdo);
if (err != ERROR_OK)
return err;
if (tdo)
LOG_DEBUG_IO("Transact num_bits: %zu, tms: %" PRIx32 ", tdi: %" PRIx32 ", tdo: %" PRIx32,
- num_bits, tms, tdi, *tdo);
+ num_bits, tms, tdi, *tdo);
else
LOG_DEBUG_IO("Transact num_bits: %zu, tms: %" PRIx32 ", tdi: %" PRIx32 ", tdo: <null>",
- num_bits, tms, tdi);
+ num_bits, tms, tdi);
+ return ERROR_OK;
+}
+
+static int xlnx_axi_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
+ uint32_t *tdo)
+{
+ uint32_t ctrl;
+ int done = 0;
+ int err;
+
+ err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_LEN_REG, num_bits);
+ if (err != ERROR_OK)
+ return err;
+
+ err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_TMS_REG, tms);
+ if (err != ERROR_OK)
+ return err;
+
+ err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_TDI_REG, tdi);
+ if (err != ERROR_OK)
+ return err;
+
+ err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_CTRL_REG, XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK);
+ if (err != ERROR_OK)
+ return err;
+
+ while (!done) {
+ err = xlnx_axi_xvc_read_reg(XLNX_AXI_XVC_CTRL_REG, &ctrl);
+ if (err != ERROR_OK)
+ return err;
+
+ if (!(ctrl & XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK))
+ done = 1;
+
+ /*
+ There is no delay here intentionally. The usleep()
+ function doesn't block and burns CPU cycles anyway.
+ The turnaround time is fast enough at high JTAG rates
+ that adding the call can slow down the overall
+ throughput. So we'll just sacrifice the CPU to get
+ best performance.
+
+ Additionally there is no timeout. The underlying
+ hardware is guaranteed to unset the enable bit within
+ 32 JTAG clock cycles. There is no hardware condition
+ that will keep it set forever. Essentially, the hardware
+ is also our timeout mechanism.
+ */
+ }
+
+ err = xlnx_axi_xvc_read_reg(XLNX_AXI_XVC_TDO_REG, tdo);
+ if (err != ERROR_OK)
+ return err;
+
+ if (tdo)
+ LOG_DEBUG_IO("Transact num_bits: %zu, tms: 0x%x, tdi: 0x%x, tdo: 0x%x",
+ num_bits, tms, tdi, *tdo);
+ else
+ LOG_DEBUG_IO("Transact num_bits: %zu, tms: 0x%x, tdi: 0x%x, tdo: <null>",
+ num_bits, tms, tdi);
return ERROR_OK;
}
-static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
+static int xlnx_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
+ uint32_t *tdo, enum xlnx_xvc_type_t xvc_type)
+{
+ if (xvc_type == PCIE)
+ return xlnx_pcie_xvc_transact(num_bits, tms, tdi, tdo);
+ assert(xvc_type == AXI);
+ return xlnx_axi_xvc_transact(num_bits, tms, tdi, tdo);
+}
+
+static int xlnx_xvc_execute_stableclocks(struct jtag_command *cmd, enum xlnx_xvc_type_t xvc_type)
{
int tms = tap_get_state() == TAP_RESET ? 1 : 0;
size_t left = cmd->cmd.stableclocks->num_cycles;
@@ -132,7 +257,7 @@ static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
while (left) {
write = MIN(XLNX_XVC_MAX_BITS, left);
- err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
+ err = xlnx_xvc_transact(write, tms, 0, NULL, xvc_type);
if (err != ERROR_OK)
return err;
left -= write;
@@ -141,12 +266,12 @@ static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
return ERROR_OK;
}
-static int xlnx_pcie_xvc_execute_statemove(size_t skip)
+static int xlnx_xvc_execute_statemove(size_t skip, enum xlnx_xvc_type_t xvc_type)
{
uint8_t tms_scan = tap_get_tms_path(tap_get_state(),
- tap_get_end_state());
+ tap_get_end_state());
int tms_count = tap_get_tms_path_len(tap_get_state(),
- tap_get_end_state());
+ tap_get_end_state());
int err;
LOG_DEBUG("statemove starting at (skip: %zu) %s end in %s", skip,
@@ -154,7 +279,7 @@ static int xlnx_pcie_xvc_execute_statemove(size_t skip)
tap_state_name(tap_get_end_state()));
- err = xlnx_pcie_xvc_transact(tms_count - skip, tms_scan >> skip, 0, NULL);
+ err = xlnx_xvc_transact(tms_count - skip, tms_scan >> skip, 0, NULL, xvc_type);
if (err != ERROR_OK)
return err;
@@ -163,7 +288,8 @@ static int xlnx_pcie_xvc_execute_statemove(size_t skip)
return ERROR_OK;
}
-static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
+static int xlnx_xvc_execute_runtest(struct jtag_command *cmd,
+ enum xlnx_xvc_type_t xvc_type)
{
int err = ERROR_OK;
@@ -175,7 +301,7 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
if (tap_get_state() != TAP_IDLE) {
tap_set_end_state(TAP_IDLE);
- err = xlnx_pcie_xvc_execute_statemove(0);
+ err = xlnx_xvc_execute_statemove(0, xvc_type);
if (err != ERROR_OK)
return err;
};
@@ -185,7 +311,7 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
while (left) {
write = MIN(XLNX_XVC_MAX_BITS, left);
- err = xlnx_pcie_xvc_transact(write, 0, 0, NULL);
+ err = xlnx_xvc_transact(write, 0, 0, NULL, xvc_type);
if (err != ERROR_OK)
return err;
left -= write;
@@ -193,12 +319,13 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
tap_set_end_state(tmp_state);
if (tap_get_state() != tap_get_end_state())
- err = xlnx_pcie_xvc_execute_statemove(0);
+ err = xlnx_xvc_execute_statemove(0, xvc_type);
return err;
}
-static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
+static int xlnx_xvc_execute_pathmove(struct jtag_command *cmd,
+ enum xlnx_xvc_type_t xvc_type)
{
unsigned int num_states = cmd->cmd.pathmove->num_states;
enum tap_state *path = cmd->cmd.pathmove->path;
@@ -210,9 +337,9 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
for (unsigned int i = 0; i < num_states; i++) {
if (path[i] == tap_state_transition(tap_get_state(), false)) {
- err = xlnx_pcie_xvc_transact(1, 0, 0, NULL);
+ err = xlnx_xvc_transact(1, 0, 0, NULL, xvc_type);
} else if (path[i] == tap_state_transition(tap_get_state(), true)) {
- err = xlnx_pcie_xvc_transact(1, 1, 0, NULL);
+ err = xlnx_xvc_transact(1, 1, 0, NULL, xvc_type);
} else {
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.",
tap_state_name(tap_get_state()),
@@ -229,7 +356,8 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
return ERROR_OK;
}
-static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
+static int xlnx_xvc_execute_scan(struct jtag_command *cmd,
+ enum xlnx_xvc_type_t xvc_type)
{
enum scan_type type = jtag_scan_type(cmd->cmd.scan);
enum tap_state saved_end_state = cmd->cmd.scan->end_state;
@@ -253,13 +381,13 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
*/
if (ir_scan && tap_get_state() != TAP_IRSHIFT) {
tap_set_end_state(TAP_IRSHIFT);
- err = xlnx_pcie_xvc_execute_statemove(0);
+ err = xlnx_xvc_execute_statemove(0, xvc_type);
if (err != ERROR_OK)
goto out_err;
tap_set_end_state(saved_end_state);
} else if (!ir_scan && (tap_get_state() != TAP_DRSHIFT)) {
tap_set_end_state(TAP_DRSHIFT);
- err = xlnx_pcie_xvc_execute_statemove(0);
+ err = xlnx_xvc_execute_statemove(0, xvc_type);
if (err != ERROR_OK)
goto out_err;
tap_set_end_state(saved_end_state);
@@ -271,8 +399,8 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
/* the last TMS should be a 1, to leave the state */
tms = left <= XLNX_XVC_MAX_BITS ? BIT(write - 1) : 0;
tdi = (type != SCAN_IN) ? buf_get_u32(rd_ptr, 0, write) : 0;
- err = xlnx_pcie_xvc_transact(write, tms, tdi, type != SCAN_OUT ?
- &tdo : NULL);
+ err = xlnx_xvc_transact(write, tms, tdi, type != SCAN_OUT ?
+ &tdo : NULL, xvc_type);
if (err != ERROR_OK)
goto out_err;
left -= write;
@@ -285,7 +413,7 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
free(buf);
if (tap_get_state() != tap_get_end_state())
- err = xlnx_pcie_xvc_execute_statemove(1);
+ err = xlnx_xvc_execute_statemove(1, xvc_type);
return err;
@@ -294,19 +422,14 @@ out_err:
return err;
}
-static void xlnx_pcie_xvc_execute_reset(struct jtag_command *cmd)
-{
- LOG_DEBUG("reset trst: %i srst: %i", cmd->cmd.reset->trst,
- cmd->cmd.reset->srst);
-}
-
-static void xlnx_pcie_xvc_execute_sleep(struct jtag_command *cmd)
+static void xlnx_xvc_execute_sleep(struct jtag_command *cmd)
{
LOG_DEBUG("sleep %" PRIu32 "", cmd->cmd.sleep->us);
usleep(cmd->cmd.sleep->us);
}
-static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
+static int xlnx_xvc_execute_tms(struct jtag_command *cmd,
+ enum xlnx_xvc_type_t xvc_type)
{
const size_t num_bits = cmd->cmd.tms->num_bits;
const uint8_t *bits = cmd->cmd.tms->bits;
@@ -320,7 +443,7 @@ static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
while (left) {
write = MIN(XLNX_XVC_MAX_BITS, left);
tms = buf_get_u32(bits, 0, write);
- err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
+ err = xlnx_xvc_transact(write, tms, 0, NULL, xvc_type);
if (err != ERROR_OK)
return err;
left -= write;
@@ -330,29 +453,30 @@ static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
return ERROR_OK;
}
-static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd)
+static int xlnx_xvc_execute_command(struct jtag_command *cmd,
+ enum xlnx_xvc_type_t xvc_type)
{
LOG_DEBUG("%s: cmd->type: %u", __func__, cmd->type);
switch (cmd->type) {
case JTAG_STABLECLOCKS:
- return xlnx_pcie_xvc_execute_stableclocks(cmd);
+ return xlnx_xvc_execute_stableclocks(cmd, xvc_type);
case JTAG_RUNTEST:
- return xlnx_pcie_xvc_execute_runtest(cmd);
+ return xlnx_xvc_execute_runtest(cmd, xvc_type);
case JTAG_TLR_RESET:
tap_set_end_state(cmd->cmd.statemove->end_state);
- return xlnx_pcie_xvc_execute_statemove(0);
+ return xlnx_xvc_execute_statemove(0, xvc_type);
case JTAG_PATHMOVE:
- return xlnx_pcie_xvc_execute_pathmove(cmd);
+ return xlnx_xvc_execute_pathmove(cmd, xvc_type);
case JTAG_SCAN:
- return xlnx_pcie_xvc_execute_scan(cmd);
+ return xlnx_xvc_execute_scan(cmd, xvc_type);
case JTAG_RESET:
- xlnx_pcie_xvc_execute_reset(cmd);
+ LOG_INFO("WARN: XVC driver has no reset.");
break;
case JTAG_SLEEP:
- xlnx_pcie_xvc_execute_sleep(cmd);
+ xlnx_xvc_execute_sleep(cmd);
break;
case JTAG_TMS:
- return xlnx_pcie_xvc_execute_tms(cmd);
+ return xlnx_xvc_execute_tms(cmd, xvc_type);
default:
LOG_ERROR("BUG: Unknown JTAG command type encountered.");
return ERROR_JTAG_QUEUE_FAILED;
@@ -361,13 +485,14 @@ static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd)
return ERROR_OK;
}
-static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
+static int xlnx_xvc_execute_queue(struct jtag_command *cmd_queue,
+ enum xlnx_xvc_type_t xvc_type)
{
struct jtag_command *cmd = cmd_queue;
int ret;
while (cmd) {
- ret = xlnx_pcie_xvc_execute_command(cmd);
+ ret = xlnx_xvc_execute_command(cmd, xvc_type);
if (ret != ERROR_OK)
return ret;
@@ -378,6 +503,15 @@ static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
return ERROR_OK;
}
+static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
+{
+ return xlnx_xvc_execute_queue(cmd_queue, PCIE);
+}
+
+static int xlnx_axi_xvc_execute_queue(struct jtag_command *cmd_queue)
+{
+ return xlnx_xvc_execute_queue(cmd_queue, AXI);
+}
static int xlnx_pcie_xvc_init(void)
{
@@ -399,8 +533,8 @@ static int xlnx_pcie_xvc_init(void)
* vendor specific header */
xlnx_pcie_xvc->offset = PCIE_EXT_CAP_LST;
while (xlnx_pcie_xvc->offset <= PCI_CFG_SPACE_EXP_SIZE - sizeof(cap) &&
- xlnx_pcie_xvc->offset >= PCIE_EXT_CAP_LST) {
- err = xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP, &cap);
+ xlnx_pcie_xvc->offset >= PCIE_EXT_CAP_LST) {
+ err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_EXT_CAP, &cap);
if (err != ERROR_OK)
return err;
LOG_DEBUG("Checking capability at 0x%x; id=0x%04" PRIx32 " version=0x%" PRIx32 " next=0x%" PRIx32,
@@ -409,7 +543,7 @@ static int xlnx_pcie_xvc_init(void)
PCI_EXT_CAP_VER(cap),
PCI_EXT_CAP_NEXT(cap));
if (PCI_EXT_CAP_ID(cap) == PCI_EXT_CAP_ID_VNDR) {
- err = xlnx_pcie_xvc_read_reg(XLNX_XVC_VSEC_HDR, &vh);
+ err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_VSEC_HDR, &vh);
if (err != ERROR_OK)
return err;
LOG_DEBUG("Checking possible match at 0x%x; id: 0x%" PRIx32 "; rev: 0x%" PRIx32 "; length: 0x%" PRIx32,
@@ -417,14 +551,14 @@ static int xlnx_pcie_xvc_init(void)
PCI_VNDR_HEADER_ID(vh),
PCI_VNDR_HEADER_REV(vh),
PCI_VNDR_HEADER_LEN(vh));
- if ((PCI_VNDR_HEADER_ID(vh) == XLNX_XVC_VSEC_ID) &&
- (PCI_VNDR_HEADER_LEN(vh) == XLNX_XVC_CAP_SIZE))
+ if ((PCI_VNDR_HEADER_ID(vh) == XLNX_PCIE_XVC_VSEC_ID) &&
+ (PCI_VNDR_HEADER_LEN(vh) == XLNX_PCIE_XVC_CAP_SIZE))
break;
}
xlnx_pcie_xvc->offset = PCI_EXT_CAP_NEXT(cap);
}
- if ((xlnx_pcie_xvc->offset > PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||
- xlnx_pcie_xvc->offset < PCIE_EXT_CAP_LST) {
+ if ((xlnx_pcie_xvc->offset > PCI_CFG_SPACE_EXP_SIZE - XLNX_PCIE_XVC_CAP_SIZE) ||
+ xlnx_pcie_xvc->offset < PCIE_EXT_CAP_LST) {
close(xlnx_pcie_xvc->fd);
return ERROR_JTAG_INIT_FAILED;
}
@@ -434,6 +568,44 @@ static int xlnx_pcie_xvc_init(void)
return ERROR_OK;
}
+static int xlnx_axi_xvc_init(void)
+{
+ uint64_t baseaddr;
+
+ if (xlnx_axi_xvc->device_addr) {
+ baseaddr = strtoul(xlnx_axi_xvc->device_addr, NULL, 0);
+ } else {
+ LOG_ERROR("Please set device addr.");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ if (xlnx_axi_xvc->device_file) {
+ LOG_INFO("Opening %s for AXI communication", xlnx_axi_xvc->device_file);
+ xlnx_axi_xvc->fd = open(xlnx_axi_xvc->device_file, O_RDWR | O_SYNC);
+ } else {
+ LOG_INFO("Opening /dev/mem for AXI communication");
+ xlnx_axi_xvc->fd = open("/dev/mem", O_RDWR | O_SYNC);
+ }
+
+ if (xlnx_axi_xvc->fd < 0) {
+ LOG_ERROR("Failed to open device file, check permissions.");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ xlnx_axi_xvc->base = mmap(0, XLNX_AXI_XVC_MAX_REG, PROT_READ | PROT_WRITE,
+ MAP_SHARED, xlnx_axi_xvc->fd, baseaddr);
+ if (xlnx_axi_xvc->base == MAP_FAILED) {
+ LOG_ERROR("mmap() failed, check permissions.");
+ close(xlnx_axi_xvc->fd);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ LOG_INFO("Mapped Xilinx XVC/AXI vaddr %p paddr 0x%" PRIx64,
+ xlnx_axi_xvc->base, baseaddr);
+
+ return ERROR_OK;
+}
+
static int xlnx_pcie_xvc_quit(void)
{
int err;
@@ -445,21 +617,55 @@ static int xlnx_pcie_xvc_quit(void)
return ERROR_OK;
}
+static int xlnx_axi_xvc_quit(void)
+{
+ int err;
+
+ munmap(xlnx_axi_xvc->base, XLNX_AXI_XVC_MAX_REG);
+ free(xlnx_pcie_xvc->device);
+ free(xlnx_axi_xvc->device_file);
+ free(xlnx_axi_xvc->device_addr);
+
+ err = close(xlnx_axi_xvc->fd);
+ if (err)
+ return err;
+
+ return ERROR_OK;
+}
+
COMMAND_HANDLER(xlnx_pcie_xvc_handle_config_command)
{
- if (CMD_ARGC < 1)
+ if (CMD_ARGC != 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- /* we can't really free this in a safe manner, so at least
- * limit the memory we're leaking by freeing the old one first
- * before allocating a new one ...
- */
free(xlnx_pcie_xvc->device);
xlnx_pcie_xvc->device = strdup(CMD_ARGV[0]);
return ERROR_OK;
}
+COMMAND_HANDLER(xlnx_axi_xvc_handle_dev_addr_command)
+{
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ free(xlnx_axi_xvc->device_addr);
+
+ xlnx_axi_xvc->device_addr = strdup(CMD_ARGV[0]);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(xlnx_axi_xvc_handle_dev_file_command)
+{
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ free(xlnx_axi_xvc->device_file);
+
+ xlnx_axi_xvc->device_file = strdup(CMD_ARGV[0]);
+ return ERROR_OK;
+}
+
static const struct command_registration xlnx_pcie_xvc_subcommand_handlers[] = {
{
.name = "config",
@@ -482,11 +688,45 @@ static const struct command_registration xlnx_pcie_xvc_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
+static const struct command_registration xlnx_axi_xvc_subcommand_handlers[] = {
+ {
+ .name = "dev_addr",
+ .handler = xlnx_axi_xvc_handle_dev_addr_command,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure XVC/AXI JTAG device memory address",
+ .usage = "addr",
+ },
+ {
+ .name = "dev_file",
+ .handler = xlnx_axi_xvc_handle_dev_file_command,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure XVC/AXI JTAG device file location",
+ .usage = "addr",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration xlnx_axi_xvc_command_handlers[] = {
+ {
+ .name = "xlnx_axi_xvc",
+ .mode = COMMAND_ANY,
+ .help = "perform xlnx_axi_xvc management",
+ .chain = xlnx_axi_xvc_subcommand_handlers,
+ .usage = "",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
static struct jtag_interface xlnx_pcie_xvc_jtag_ops = {
.execute_queue = &xlnx_pcie_xvc_execute_queue,
};
-static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
+static struct jtag_interface xlnx_axi_xvc_jtag_ops = {
+ .execute_queue = &xlnx_axi_xvc_execute_queue,
+};
+
+static int xlnx_xvc_swd_sequence(const uint8_t *seq, size_t length,
+ enum xlnx_xvc_type_t xvc_type)
{
size_t left, write;
uint32_t send;
@@ -496,7 +736,7 @@ static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
while (left) {
write = MIN(XLNX_XVC_MAX_BITS, left);
send = buf_get_u32(seq, 0, write);
- err = xlnx_pcie_xvc_transact(write, send, 0, NULL);
+ err = xlnx_xvc_transact(write, send, 0, NULL, xvc_type);
if (err != ERROR_OK)
return err;
left -= write;
@@ -506,21 +746,22 @@ static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
return ERROR_OK;
}
-static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
+static int xlnx_xvc_swd_switch_seq(enum swd_special_seq seq,
+ enum xlnx_xvc_type_t xvc_type)
{
switch (seq) {
case LINE_RESET:
LOG_DEBUG("SWD line reset");
- return xlnx_pcie_xvc_swd_sequence(swd_seq_line_reset,
- swd_seq_line_reset_len);
+ return xlnx_xvc_swd_sequence(swd_seq_line_reset,
+ swd_seq_line_reset_len, xvc_type);
case JTAG_TO_SWD:
LOG_DEBUG("JTAG-to-SWD");
- return xlnx_pcie_xvc_swd_sequence(swd_seq_jtag_to_swd,
- swd_seq_jtag_to_swd_len);
+ return xlnx_xvc_swd_sequence(swd_seq_jtag_to_swd,
+ swd_seq_jtag_to_swd_len, xvc_type);
case SWD_TO_JTAG:
LOG_DEBUG("SWD-to-JTAG");
- return xlnx_pcie_xvc_swd_sequence(swd_seq_swd_to_jtag,
- swd_seq_swd_to_jtag_len);
+ return xlnx_xvc_swd_sequence(swd_seq_swd_to_jtag,
+ swd_seq_swd_to_jtag_len, xvc_type);
default:
LOG_ERROR("Sequence %d not supported", seq);
return ERROR_FAIL;
@@ -529,19 +770,31 @@ static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
return ERROR_OK;
}
+static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
+{
+ return xlnx_xvc_swd_switch_seq(seq, PCIE);
+}
+
+static int xlnx_axi_xvc_swd_switch_seq(enum swd_special_seq seq)
+{
+ return xlnx_xvc_swd_switch_seq(seq, AXI);
+}
+
static int queued_retval;
-static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
- uint32_t ap_delay_clk);
+static void xlnx_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+ uint32_t ap_delay_clk,
+ enum xlnx_xvc_type_t xvc_type);
-static void swd_clear_sticky_errors(void)
+static void swd_clear_sticky_errors(enum xlnx_xvc_type_t xvc_type)
{
- xlnx_pcie_xvc_swd_write_reg(swd_cmd(false, false, DP_ABORT),
- STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
+ xlnx_xvc_swd_write_reg(swd_cmd(false, false, DP_ABORT),
+ STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0, xvc_type);
}
-static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
- uint32_t ap_delay_clk)
+static void xlnx_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
+ uint32_t ap_delay_clk,
+ enum xlnx_xvc_type_t xvc_type)
{
uint32_t res, ack, rpar;
int err;
@@ -550,23 +803,23 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
cmd |= SWD_CMD_START | SWD_CMD_PARK;
/* cmd + ack */
- err = xlnx_pcie_xvc_transact(12, cmd, 0, &res);
+ err = xlnx_xvc_transact(12, cmd, 0, &res, xvc_type);
if (err != ERROR_OK)
goto err_out;
ack = MASK_ACK(res);
/* read data */
- err = xlnx_pcie_xvc_transact(32, 0, 0, &res);
+ err = xlnx_xvc_transact(32, 0, 0, &res, xvc_type);
if (err != ERROR_OK)
goto err_out;
/* parity + trn */
- err = xlnx_pcie_xvc_transact(2, 0, 0, &rpar);
+ err = xlnx_xvc_transact(2, 0, 0, &rpar, xvc_type);
if (err != ERROR_OK)
goto err_out;
- LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+ LOG_DEBUG("%s %s %s reg %X = %08" PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -583,19 +836,19 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
if (value)
*value = res;
if (cmd & SWD_CMD_APNDP)
- err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+ err = xlnx_xvc_transact(ap_delay_clk, 0, 0, NULL, xvc_type);
queued_retval = err;
return;
case SWD_ACK_WAIT:
LOG_DEBUG_IO("SWD_ACK_WAIT");
- swd_clear_sticky_errors();
+ swd_clear_sticky_errors(xvc_type);
return;
case SWD_ACK_FAULT:
LOG_DEBUG_IO("SWD_ACK_FAULT");
queued_retval = ack;
return;
default:
- LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+ LOG_DEBUG_IO("No valid acknowledge: ack=%02" PRIx32, ack);
queued_retval = ack;
return;
}
@@ -603,8 +856,21 @@ err_out:
queued_retval = err;
}
-static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
uint32_t ap_delay_clk)
+{
+ xlnx_xvc_swd_read_reg(cmd, value, ap_delay_clk, PCIE);
+}
+
+static void xlnx_axi_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
+ uint32_t ap_delay_clk)
+{
+ xlnx_xvc_swd_read_reg(cmd, value, ap_delay_clk, AXI);
+}
+
+static void xlnx_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+ uint32_t ap_delay_clk,
+ enum xlnx_xvc_type_t xvc_type)
{
uint32_t res, ack;
int err;
@@ -613,23 +879,23 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
cmd |= SWD_CMD_START | SWD_CMD_PARK;
/* cmd + trn + ack */
- err = xlnx_pcie_xvc_transact(13, cmd, 0, &res);
+ err = xlnx_xvc_transact(13, cmd, 0, &res, xvc_type);
if (err != ERROR_OK)
goto err_out;
ack = MASK_ACK(res);
/* write data */
- err = xlnx_pcie_xvc_transact(32, value, 0, NULL);
+ err = xlnx_xvc_transact(32, value, 0, NULL, xvc_type);
if (err != ERROR_OK)
goto err_out;
/* parity + trn */
- err = xlnx_pcie_xvc_transact(2, parity_u32(value), 0, NULL);
+ err = xlnx_xvc_transact(2, parity_u32(value), 0, NULL, xvc_type);
if (err != ERROR_OK)
goto err_out;
- LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+ LOG_DEBUG("%s %s %s reg %X = %08" PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -640,19 +906,19 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
switch (ack) {
case SWD_ACK_OK:
if (cmd & SWD_CMD_APNDP)
- err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+ err = xlnx_xvc_transact(ap_delay_clk, 0, 0, NULL, xvc_type);
queued_retval = err;
return;
case SWD_ACK_WAIT:
LOG_DEBUG_IO("SWD_ACK_WAIT");
- swd_clear_sticky_errors();
+ swd_clear_sticky_errors(xvc_type);
return;
case SWD_ACK_FAULT:
LOG_DEBUG_IO("SWD_ACK_FAULT");
queued_retval = ack;
return;
default:
- LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+ LOG_DEBUG_IO("No valid acknowledge: ack=%02" PRIx32, ack);
queued_retval = ack;
return;
}
@@ -661,12 +927,24 @@ err_out:
queued_retval = err;
}
-static int xlnx_pcie_xvc_swd_run_queue(void)
+static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+ uint32_t ap_delay_clk)
+{
+ xlnx_xvc_swd_write_reg(cmd, value, ap_delay_clk, PCIE);
+}
+
+static void xlnx_axi_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+ uint32_t ap_delay_clk)
+{
+ xlnx_xvc_swd_write_reg(cmd, value, ap_delay_clk, AXI);
+}
+
+static int xlnx_xvc_swd_run_queue(enum xlnx_xvc_type_t xvc_type)
{
int err;
/* we want at least 8 idle cycles between each transaction */
- err = xlnx_pcie_xvc_transact(8, 0, 0, NULL);
+ err = xlnx_xvc_transact(8, 0, 0, NULL, xvc_type);
if (err != ERROR_OK)
return err;
@@ -677,19 +955,37 @@ static int xlnx_pcie_xvc_swd_run_queue(void)
return err;
}
-static int xlnx_pcie_xvc_swd_init(void)
+static int xlnx_pcie_xvc_swd_run_queue(void)
+{
+ return xlnx_xvc_swd_run_queue(PCIE);
+}
+
+static int xlnx_axi_xvc_swd_run_queue(void)
+{
+ return xlnx_xvc_swd_run_queue(AXI);
+}
+
+static int xlnx_xvc_swd_init(void)
{
return ERROR_OK;
}
static const struct swd_driver xlnx_pcie_xvc_swd_ops = {
- .init = xlnx_pcie_xvc_swd_init,
+ .init = xlnx_xvc_swd_init,
.switch_seq = xlnx_pcie_xvc_swd_switch_seq,
.read_reg = xlnx_pcie_xvc_swd_read_reg,
.write_reg = xlnx_pcie_xvc_swd_write_reg,
.run = xlnx_pcie_xvc_swd_run_queue,
};
+static const struct swd_driver xlnx_axi_xvc_swd_ops = {
+ .init = xlnx_xvc_swd_init,
+ .switch_seq = xlnx_axi_xvc_swd_switch_seq,
+ .read_reg = xlnx_axi_xvc_swd_read_reg,
+ .write_reg = xlnx_axi_xvc_swd_write_reg,
+ .run = xlnx_axi_xvc_swd_run_queue,
+};
+
struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
.name = "xlnx_pcie_xvc",
.transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD,
@@ -702,3 +998,16 @@ struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
.jtag_ops = &xlnx_pcie_xvc_jtag_ops,
.swd_ops = &xlnx_pcie_xvc_swd_ops,
};
+
+struct adapter_driver xlnx_axi_xvc_adapter_driver = {
+ .name = "xlnx_axi_xvc",
+ .transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD,
+ .transport_preferred_id = TRANSPORT_JTAG,
+ .commands = xlnx_axi_xvc_command_handlers,
+
+ .init = &xlnx_axi_xvc_init,
+ .quit = &xlnx_axi_xvc_quit,
+
+ .jtag_ops = &xlnx_axi_xvc_jtag_ops,
+ .swd_ops = &xlnx_axi_xvc_swd_ops,
+};
diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index 834997361..fb26c94ad 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -411,6 +411,7 @@ extern struct adapter_driver usbprog_adapter_driver;
extern struct adapter_driver vdebug_adapter_driver;
extern struct adapter_driver vsllink_adapter_driver;
extern struct adapter_driver xds110_adapter_driver;
+extern struct adapter_driver xlnx_axi_xvc_adapter_driver;
extern struct adapter_driver xlnx_pcie_xvc_adapter_driver;
#endif /* OPENOCD_JTAG_INTERFACE_H */
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 4bb2822d1..099b84425 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -156,7 +156,8 @@ struct adapter_driver *adapter_drivers[] = {
&xds110_adapter_driver,
#endif
#if BUILD_XLNX_XVC == 1
- &xlnx_pcie_xvc_adapter_driver,
+ &xlnx_pcie_xvc_adapter_driver,
+ &xlnx_axi_xvc_adapter_driver,
#endif
NULL,
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index 2d8ebf041..88d802fcb 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -413,6 +413,12 @@ proc xlnx_pcie_xvc_config args {
eval xlnx_pcie_xvc config $args
}
+lappend _telnet_autocomplete_skip xlnx_axi_xvc_config
+proc xlnx_axi_xvc_config args {
+ echo "DEPRECATED! use 'xlnx_axi_xvc config' not 'xlnx_axi_xvc_config'"
+ eval xlnx_axi_xvc config $args
+}
+
lappend _telnet_autocomplete_skip ulink_download_firmware
proc ulink_download_firmware args {
echo "DEPRECATED! use 'ulink download_firmware' not 'ulink_download_firmware'"
commit 8cdf8cb99567654ff2b33feb781680159c9fbd63
Author: Nicolas Derumigny <nic...@in...>
Date: Mon Jun 30 11:21:18 2025 +0200
driver: jtag: rename xlnx-pcie-xvc to xlnx-xvc
Rename xlnx-pcie-xvc.c to xlnx-xvc.c in provision for AXI support
Signed-off-by: Nicolas Derumigny <nic...@in...>
Change-Id: I287fdcb8edf97f48c6f8614ac4c456f8ba197011
Reviewed-on: https://review.openocd.org/c/openocd/+/8980
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/configure.ac b/configure.ac
index 453cbcfb5..9bbb2c36a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -178,7 +178,7 @@ m4_define([LIBJAYLINK_ADAPTERS],
[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
m4_define([PCIE_ADAPTERS],
- [[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_PCIE_XVC]]])
+ [[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_XVC]]])
m4_define([SERIAL_PORT_ADAPTERS],
[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index b0dd8e3ad..e55e0478c 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -179,8 +179,8 @@ endif
if LINUXSPIDEV
DRIVERFILES += %D%/linuxspidev.c
endif
-if XLNX_PCIE_XVC
-DRIVERFILES += %D%/xlnx-pcie-xvc.c
+if XLNX_XVC
+DRIVERFILES += %D%/xlnx-xvc.c
endif
if BCM2835GPIO
DRIVERFILES += %D%/bcm2835gpio.c
diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-xvc.c
similarity index 100%
rename from src/jtag/drivers/xlnx-pcie-xvc.c
rename to src/jtag/drivers/xlnx-xvc.c
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 834247245..4bb2822d1 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -155,7 +155,7 @@ struct adapter_driver *adapter_drivers[] = {
#if BUILD_XDS110 == 1
&xds110_adapter_driver,
#endif
-#if BUILD_XLNX_PCIE_XVC == 1
+#if BUILD_XLNX_XVC == 1
&xlnx_pcie_xvc_adapter_driver,
#endif
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 11 +-
doc/openocd.texi | 21 +
src/jtag/drivers/Makefile.am | 4 +-
src/jtag/drivers/{xlnx-pcie-xvc.c => xlnx-xvc.c} | 523 ++++++++++++++++++-----
src/jtag/interface.h | 1 +
src/jtag/interfaces.c | 5 +-
src/jtag/startup.tcl | 6 +
7 files changed, 455 insertions(+), 116 deletions(-)
rename src/jtag/drivers/{xlnx-pcie-xvc.c => xlnx-xvc.c} (50%)
hooks/post-receive
--
Main OpenOCD repository
|
