Menu
▾
▴
[PATCH]: 6f89bd4b49 target: Use 'bool' data type for 'mmu_enabled'
|
From: <ge...@op...> - 2025-07-09 15:14:36
|
This is an automated email from Gerrit. "zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8988 -- gerrit commit 6f89bd4b49ff68297ade78b191ec95b32725c223 Author: Marc Schink <de...@za...> Date: Wed Jul 9 11:31:37 2025 +0000 target: Use 'bool' data type for 'mmu_enabled' The variables are already used in some parts of the code as boolean value but have the wrong data type. Change-Id: I2c4955a6ed463fabf63a1dbd79145cb63bc7a99c Signed-off-by: Marc Schink <de...@za...> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 101cb14408..f6fc6db4e6 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1100,10 +1100,9 @@ static int aarch64_post_debug_entry(struct target *target) armv8_read_mpidr(armv8); } if (armv8->is_armv8r) { - armv8->armv8_mmu.mmu_enabled = 0; + armv8->armv8_mmu.mmu_enabled = false; } else { - armv8->armv8_mmu.mmu_enabled = - (aarch64->system_control_reg & 0x1U) ? 1 : 0; + armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U; } armv8->armv8_mmu.armv8_cache.d_u_cache_enabled = (aarch64->system_control_reg & 0x4U) ? 1 : 0; diff --git a/src/target/arm720t.c b/src/target/arm720t.c index d1433dde72..c9ee62d3d1 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -198,7 +198,7 @@ static int arm720t_post_debug_entry(struct target *target) return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg); - arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0; + arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; @@ -354,7 +354,7 @@ static int arm720t_soft_reset_halt(struct target *target) retval = arm720t_disable_mmu_caches(target, 1, 1, 1); if (retval != ERROR_OK) return retval; - arm720t->armv4_5_mmu.mmu_enabled = 0; + arm720t->armv4_5_mmu.mmu_enabled = false; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; @@ -407,7 +407,7 @@ static int arm720t_init_arch_info(struct target *target, arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches; arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches; arm720t->armv4_5_mmu.has_tiny_pages = 0; - arm720t->armv4_5_mmu.mmu_enabled = 0; + arm720t->armv4_5_mmu.mmu_enabled = false; return ERROR_OK; } diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 95cfd7ceb2..9faae9a474 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -425,8 +425,7 @@ int arm920t_post_debug_entry(struct target *target) &arm920t->armv4_5_mmu.armv4_5_cache); } - arm920t->armv4_5_mmu.mmu_enabled = - (arm920t->cp15_control_reg & 0x1U) ? 1 : 0; + arm920t->armv4_5_mmu.mmu_enabled = arm920t->cp15_control_reg & 0x1U; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0; arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = @@ -778,7 +777,7 @@ int arm920t_soft_reset_halt(struct target *target) arm->pc->valid = true; arm920t_disable_mmu_caches(target, 1, 1, 1); - arm920t->armv4_5_mmu.mmu_enabled = 0; + arm920t->armv4_5_mmu.mmu_enabled = false; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; @@ -819,7 +818,7 @@ static int arm920t_init_arch_info(struct target *target, arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches; arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches; arm920t->armv4_5_mmu.has_tiny_pages = 1; - arm920t->armv4_5_mmu.mmu_enabled = 0; + arm920t->armv4_5_mmu.mmu_enabled = false; /* disabling linefills leads to lockups, so keep them enabled for now * this doesn't affect correctness, but might affect timing issues, if diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 0531106562..922b02013f 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -440,7 +440,7 @@ static int arm926ejs_post_debug_entry(struct target *target) armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache); } - arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0; + arm926ejs->armv4_5_mmu.mmu_enabled = arm926ejs->cp15_control_reg & 0x1U; arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0; arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0; @@ -575,7 +575,7 @@ int arm926ejs_soft_reset_halt(struct target *target) retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1); if (retval != ERROR_OK) return retval; - arm926ejs->armv4_5_mmu.mmu_enabled = 0; + arm926ejs->armv4_5_mmu.mmu_enabled = false; arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; @@ -689,7 +689,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches; arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches; arm926ejs->armv4_5_mmu.has_tiny_pages = 1; - arm926ejs->armv4_5_mmu.mmu_enabled = 0; + arm926ejs->armv4_5_mmu.mmu_enabled = false; arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason; diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h index 774f1056eb..bb30e807f4 100644 --- a/src/target/armv4_5_mmu.h +++ b/src/target/armv4_5_mmu.h @@ -21,7 +21,7 @@ struct armv4_5_mmu_common { int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache); struct armv4_5_cache_common armv4_5_cache; int has_tiny_pages; - int mmu_enabled; + bool mmu_enabled; }; int armv4_5_mmu_translate_va(struct target *target, diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 2706c4629b..69e223ddb2 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -81,7 +81,7 @@ struct armv7a_mmu_common { int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer); struct armv7a_cache_common armv7a_cache; - uint32_t mmu_enabled; + bool mmu_enabled; }; struct armv7a_common { diff --git a/src/target/armv8.h b/src/target/armv8.h index 64ca5ec9d4..32c0dc32be 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -179,7 +179,7 @@ struct armv8_mmu_common { int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer); struct armv8_cache_common armv8_cache; - uint32_t mmu_enabled; + bool mmu_enabled; }; struct armv8_common { diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 2ebbf65774..3d979bbabd 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1122,10 +1122,9 @@ static int cortex_a_post_debug_entry(struct target *target) armv7a_identify_cache(target); if (armv7a->is_armv7r) { - armv7a->armv7a_mmu.mmu_enabled = 0; + armv7a->armv7a_mmu.mmu_enabled = false; } else { - armv7a->armv7a_mmu.mmu_enabled = - (cortex_a->cp15_control_reg & 0x1U) ? 1 : 0; + armv7a->armv7a_mmu.mmu_enabled = cortex_a->cp15_control_reg & 0x1U; } armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled = (cortex_a->cp15_control_reg & 0x4U) ? 1 : 0; diff --git a/src/target/fa526.c b/src/target/fa526.c index d832d3e7d1..254e5be6e3 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -315,7 +315,7 @@ static int fa526_init_arch_info(struct target *target, arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches; arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches; arm920t->armv4_5_mmu.has_tiny_pages = 1; - arm920t->armv4_5_mmu.mmu_enabled = 0; + arm920t->armv4_5_mmu.mmu_enabled = false; /* disabling linefills leads to lockups, so keep them enabled for now * this doesn't affect correctness, but might affect timing issues, if diff --git a/src/target/xscale.c b/src/target/xscale.c index 84318a905f..b3d43ec7e9 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -982,7 +982,7 @@ static int xscale_debug_entry(struct target *target) xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); - xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0; + xscale->armv4_5_mmu.mmu_enabled = xscale->cp15_control_reg & 0x1U; xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0; xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = @@ -3007,7 +3007,7 @@ static int xscale_init_arch_info(struct target *target, xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches; xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches; xscale->armv4_5_mmu.has_tiny_pages = 1; - xscale->armv4_5_mmu.mmu_enabled = 0; + xscale->armv4_5_mmu.mmu_enabled = false; return ERROR_OK; } -- |
