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[PATCH]: 4867b41059 target: Use 'bool' data type for {i, d_u}_cache_enabled
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From: <ge...@op...> - 2025-07-09 15:14:37
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This is an automated email from Gerrit. "zapb <de...@za...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8992 -- gerrit commit 4867b41059001a2ab9724a84de7efd07796868c0 Author: Marc Schink <de...@za...> Date: Wed Jul 9 12:06:59 2025 +0000 target: Use 'bool' data type for {i,d_u}_cache_enabled The variables are already used as boolean value but have the wrong data type. Change-Id: Ia4c63d04fdd61bfd48e353fde9984b0e6cefbd8b Signed-off-by: Marc Schink <de...@za...> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 51ef1a82ac..d1ff023d98 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1105,9 +1105,9 @@ static int aarch64_post_debug_entry(struct target *target) armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U; } armv8->armv8_mmu.armv8_cache.d_u_cache_enabled = - (aarch64->system_control_reg & 0x4U) ? 1 : 0; + aarch64->system_control_reg & 0x4U; armv8->armv8_mmu.armv8_cache.i_cache_enabled = - (aarch64->system_control_reg & 0x1000U) ? 1 : 0; + aarch64->system_control_reg & 0x1000U; return ERROR_OK; } diff --git a/src/target/arm720t.c b/src/target/arm720t.c index c708c1daad..933b49bebc 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -199,8 +199,9 @@ static int arm720t_post_debug_entry(struct target *target) LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg); arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U; - arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0; - arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; + arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = + arm720t->cp15_control_reg & 0x4U; + arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false; /* save i/d fault status and address register */ retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg); @@ -355,8 +356,8 @@ static int arm720t_soft_reset_halt(struct target *target) if (retval != ERROR_OK) return retval; arm720t->armv4_5_mmu.mmu_enabled = false; - arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; - arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; + arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false; + arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false; retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); if (retval != ERROR_OK) diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 4f19affac5..4dd5763539 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -427,9 +427,9 @@ int arm920t_post_debug_entry(struct target *target) arm920t->armv4_5_mmu.mmu_enabled = arm920t->cp15_control_reg & 0x1U; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = - (arm920t->cp15_control_reg & 0x4U) ? 1 : 0; + arm920t->cp15_control_reg & 0x4U; arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = - (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0; + arm920t->cp15_control_reg & 0x1000U; /* save i/d fault status and address register * FIXME use opcode macros */ @@ -778,8 +778,8 @@ int arm920t_soft_reset_halt(struct target *target) arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = false; - arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; - arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; + arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false; + arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false; return target_call_event_callbacks(target, TARGET_EVENT_HALTED); } diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 8c31765e1b..587f25061f 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -441,8 +441,10 @@ static int arm926ejs_post_debug_entry(struct target *target) } arm926ejs->armv4_5_mmu.mmu_enabled = arm926ejs->cp15_control_reg & 0x1U; - arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0; - arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0; + arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = + arm926ejs->cp15_control_reg & 0x4U; + arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = + arm926ejs->cp15_control_reg & 0x1000U; /* save i/d fault status and address register */ retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr); @@ -576,8 +578,8 @@ int arm926ejs_soft_reset_halt(struct target *target) if (retval != ERROR_OK) return retval; arm926ejs->armv4_5_mmu.mmu_enabled = false; - arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; - arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; + arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false; + arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false; return target_call_event_callbacks(target, TARGET_EVENT_HALTED); } diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h index 3659941e52..63fbdff33a 100644 --- a/src/target/armv4_5_cache.h +++ b/src/target/armv4_5_cache.h @@ -24,8 +24,8 @@ struct armv4_5_cache_common { int separate; /* separate caches or unified cache */ struct armv4_5_cachesize d_u_size; /* data cache */ struct armv4_5_cachesize i_size; /* instruction cache */ - int i_cache_enabled; - int d_u_cache_enabled; + bool i_cache_enabled; + bool d_u_cache_enabled; }; int armv4_5_identify_cache(uint32_t cache_type_reg, diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 69e223ddb2..0c5e0f90f6 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -63,8 +63,8 @@ struct armv7a_cache_common { uint32_t dminline; /* minimum d-cache linelen */ uint32_t iminline; /* minimum i-cache linelen */ struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */ - int i_cache_enabled; - int d_u_cache_enabled; + bool i_cache_enabled; + bool d_u_cache_enabled; /* outer unified cache if some */ struct armv7a_l2x_cache *outer_cache; int (*flush_all_data_cache)(struct target *target); diff --git a/src/target/armv8.h b/src/target/armv8.h index 32c0dc32be..51b8b00cd4 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -156,8 +156,8 @@ struct armv8_cache_common { uint32_t iminline; uint32_t dminline; struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */ - int i_cache_enabled; - int d_u_cache_enabled; + bool i_cache_enabled; + bool d_u_cache_enabled; /* l2 external unified cache if some */ void *l2_cache; diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index d694ec0f28..69bc0920b3 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1127,9 +1127,9 @@ static int cortex_a_post_debug_entry(struct target *target) armv7a->armv7a_mmu.mmu_enabled = cortex_a->cp15_control_reg & 0x1U; } armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled = - (cortex_a->cp15_control_reg & 0x4U) ? 1 : 0; + cortex_a->cp15_control_reg & 0x4U; armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled = - (cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0; + cortex_a->cp15_control_reg & 0x1000U; cortex_a->curr_mode = armv7a->arm.core_mode; /* switch to SVC mode to read DACR */ diff --git a/src/target/xscale.c b/src/target/xscale.c index 7eaef6b8c8..783628b128 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -984,9 +984,9 @@ static int xscale_debug_entry(struct target *target) buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); xscale->armv4_5_mmu.mmu_enabled = xscale->cp15_control_reg & 0x1U; xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = - (xscale->cp15_control_reg & 0x4U) ? 1 : 0; + xscale->cp15_control_reg & 0x4U; xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = - (xscale->cp15_control_reg & 0x1000U) ? 1 : 0; + xscale->cp15_control_reg & 0x1000U; /* tracing enabled, read collected trace data */ if (xscale->trace.mode != XSCALE_TRACE_DISABLED) { -- |
