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[PATCH]: 12e7e1e2bf tcl: add support for stm32mp2xx targets and boards
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From: <ge...@op...> - 2025-07-04 15:20:15
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This is an automated email from Gerrit. "Antonio Borneo <bor...@gm...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8985 -- gerrit commit 12e7e1e2bf3e5a8d9b15336012fa7a95629a3284 Author: Antonio Borneo <bor...@gm...> Date: Fri Jul 4 16:37:38 2025 +0200 tcl: add support for stm32mp2xx targets and boards Add support for the targets stm32mp21x, stm32mp23x and stm32mp25x. Add support for the boards stm32mp23x-dk and stm32mp25x-dk. The board stm32mp21x-dk has no configuration file as it only provides a generic JTAG/SWD connector for the stm32mp21x SoC. Change-Id: I0256bebd8a5d5600066d8ae191d83344a35d3d37 Signed-off-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/board/st/stm32mp23x-dk.cfg b/tcl/board/st/stm32mp23x-dk.cfg new file mode 100644 index 0000000000..1f660f19ed --- /dev/null +++ b/tcl/board/st/stm32mp23x-dk.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# MB1605 with stm32mp23x +# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html + +source [find interface/stlink.cfg] + +transport select swd + +source [find target/st/stm32mp23x.cfg] + +reset_config srst_only diff --git a/tcl/board/st/stm32mp25x-dk.cfg b/tcl/board/st/stm32mp25x-dk.cfg new file mode 100644 index 0000000000..182f1d00ce --- /dev/null +++ b/tcl/board/st/stm32mp25x-dk.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# MB1605 +# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html + +source [find interface/stlink.cfg] + +transport select swd + +source [find target/st/stm32mp25x.cfg] + +reset_config srst_only diff --git a/tcl/target/st/stm32mp21x.cfg b/tcl/target/st/stm32mp21x.cfg new file mode 100644 index 0000000000..22532031ff --- /dev/null +++ b/tcl/target/st/stm32mp21x.cfg @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STMicroelectronics STM32MP21x +# STM32MP21x devices support both JTAG and SWD transports. + +# HLA does not support multi-cores nor custom CSW nor AP other than 0 +if { [using_hla] } { + echo "ERROR: HLA transport cannot work with this target." + shutdown +} + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32mp21x +} + +# Set to 0 to prevent CPU examine. Default examine them +if { ! [info exists EN_CA35] } { set EN_CA35 1 } +if { ! [info exists EN_CM33] } { set EN_CM33 1 } + +set _ENDIAN little + +# jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } { + set _CPUTAPID 0x6ba02477 + } +} + +# Chip Level TAP Controller, only in jtag mode +if { [info exists CLCTAPID] } { + set _CLCTAPID $CLCTAPID +} else { + set _CLCTAPID 0x16503041 +} + +swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f +if { [using_jtag] } { + swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5 +} + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap + +# define AXI & APB Memory Access Ports +# NOTE: do not change the order of target create +target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0 +target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1 +target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 2 +target create $_CHIPNAME.ap3 mem_ap -dap $_CHIPNAME.dap -ap-num 3 -defer-examine + +# define the Cortex-A35 +cti create $_CHIPNAME.cti.a35 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80220000 +target create $_CHIPNAME.a35 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase 0x80210000 \ + -cti $_CHIPNAME.cti.a35 -defer-examine + +# define the Cortex-M33 +target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine +cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xe0042000 + +# define the system CTIs +cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80080000 +cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80090000 + +swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x800A0000 +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80040000 + +targets $_CHIPNAME.a35 + +reset_config srst_pulls_trst + +adapter speed 5000 +adapter srst pulse_width 200 +# wait 1 seconds for bootrom +adapter srst delay 1000 + +# set CSW for AXI +$_CHIPNAME.dap apsel 2 +$_CHIPNAME.dap apcsw 0x12800000 + +# mmw with target selection +proc target_mmw {target reg setbits clearbits} { + set val [eval $target read_memory $reg 32 1] + set val [expr {($val & ~$clearbits) | $setbits}] + eval $target mww $reg $val +} + +lappend _telnet_autocomplete_skip _enable_debug +# Uses AP0 and AXI +proc _enable_debug {} { + # Enable DBGMCU clock in RC + $::_CHIPNAME.axi mww 0x44200520 0x500 + + # set debug enable bits in DBGMCU_CR to get ap3/cm33 visible + $::_CHIPNAME.ap0 mww 0x80001004 0x7 + + # Freeze watchdogs on CPU halt + $::_CHIPNAME.axi mww 0x440a003c 0x00000026 + $::_CHIPNAME.axi mww 0x440a0040 0x00000038 +} + +lappend _telnet_autocomplete_skip _rcc_enable_traceclk +# Uses AXI +proc _rcc_enable_traceclk {} { + # set bit TRACEEN in RCC_DBGCFGR to clock TPIU + target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0 +} + +lappend _telnet_autocomplete_skip _handshake_with_wrapper +# Uses AP0, AP1 and AP3 +proc _handshake_with_wrapper { halt } { + set dbgmcu_cr 0 + catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80001004 32 1]} + if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} { + echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n" + return + } + + if { $halt } { + if { $::EN_CA35 } { + $::_CHIPNAME.ap1 arp_examine + $::_CHIPNAME.ap1 arp_halt + $::_CHIPNAME.ap1 mww 0x80210300 0 + target_mmw $::_CHIPNAME.ap1 0x80210088 0x00004000 0 + } + if { $::EN_CM33 } { + $::_CHIPNAME.ap3 arp_examine + $::_CHIPNAME.ap3 arp_halt + $::_CHIPNAME.ap3 mww 0xe000edf0 0xa05f0001 + } + } + + # alert wrapper that debugger is ready + $::_CHIPNAME.ap0 mww 0x80001004 0x07 +} + +lappend _telnet_autocomplete_skip _enable_dbgmcu_on_devboot +# In DEV BOOT the BootROM does not completes the sequence to enable the +# visibility of DBGMCU on AP0. +# Write a value in DBGMCU_DBG_AUTH_DEV from CID1. +# Returns 1 if DEV BOOT is detected +# Uses AP2 (AXI bus) +proc _enable_dbgmcu_on_devboot {} { + $::_CHIPNAME.axi mww 0x44230004 0 + set boot_pins [expr {[$::_CHIPNAME.axi read_memory 0x44230000 32 1] & 0xf}] + if {$boot_pins != 0x3 && $boot_pins != 0xc} { + return 0 + } + + set rifsc_rimc_cr [$::_CHIPNAME.axi read_memory 0x42080c00 32 1] + if {$rifsc_rimc_cr != 0x00008710} { + echo "RIFSC_RIMC_CR modified, skip activation of DBGMCU" + return 1 + } + + # Enable DBGMCU clock in RC + $::_CHIPNAME.axi mww 0x44200520 0x500 + + # Change DAP (AXI) CID, write in DBGMCU, set back DAP CID + $::_CHIPNAME.axi mww 0x42080c00 0x00008110 + $::_CHIPNAME.axi mww 0x440A0104 1 + $::_CHIPNAME.axi mww 0x42080c00 0x00008710 + return 1 +} + +$_CHIPNAME.m33 configure -event reset-assert { } + +$_CHIPNAME.axi configure -event reset-assert-post { adapter assert srst } + +$_CHIPNAME.axi configure -event reset-deassert-pre { + adapter deassert srst deassert trst + $::_CHIPNAME.axi arp_examine + set is_dev_boot [_enable_dbgmcu_on_devboot] + if { !$is_dev_boot } { _handshake_with_wrapper $halt} + _enable_debug + _rcc_enable_traceclk + if { $::EN_CA35 } { $::_CHIPNAME.a35 arp_examine; if {$halt} {$::_CHIPNAME.a35 arp_halt} } + if { $::EN_CM33 } { + $::_CHIPNAME.ap3 arp_examine + $::_CHIPNAME.m33 arp_examine + if {$halt} {$::_CHIPNAME.ap3 arp_halt; $::_CHIPNAME.m33 arp_halt} + } +} + +$_CHIPNAME.axi configure -event examine-end { + set is_dev_boot [_enable_dbgmcu_on_devboot] + if {$is_dev_boot} {echo "Dev boot detected"} + _enable_debug + _rcc_enable_traceclk + if { $::EN_CA35 } { $::_CHIPNAME.a35 arp_examine } + if { $::EN_CM33 } { $::_CHIPNAME.ap3 arp_examine; $::_CHIPNAME.m33 arp_examine } +} diff --git a/tcl/target/st/stm32mp23x.cfg b/tcl/target/st/stm32mp23x.cfg new file mode 100644 index 0000000000..ad148608bc --- /dev/null +++ b/tcl/target/st/stm32mp23x.cfg @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STMicroelectronics STM32MP23x +# STM32MP23x devices support both JTAG and SWD transports. + +# HLA does not support multi-cores nor custom CSW nor AP other than 0 +if { [using_hla] } { + echo "ERROR: HLA transport cannot work with this target." + shutdown +} + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32mp23x +} + +# Set to 0 to prevent CPU examine. Default examine them +if { ! [info exists EN_CA35_0] } { set EN_CA35_0 1 } +if { ! [info exists EN_CA35_1] } { set EN_CA35_1 1 } +if { ! [info exists EN_CM33] } { set EN_CM33 1 } + +set _ENDIAN little + +# jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } { + set _CPUTAPID 0x6ba02477 + } +} + +# Chip Level TAP Controller, only in jtag mode +if { [info exists CLCTAPID] } { + set _CLCTAPID $CLCTAPID +} else { + set _CLCTAPID 0x16505041 +} + +swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f +if { [using_jtag] } { + swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5 +} + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap + +# define AXI & APB Memory Access Ports +# NOTE: do not change the order of target create +target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0 +target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4 +target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine + +# define the first Cortex-A35 +cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000 +target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \ + -cti $_CHIPNAME.cti.a35_0 -defer-examine + +# define the second Cortex-A35 +cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000 +target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \ + -cti $_CHIPNAME.cti.a35_1 -defer-examine + +# define the Cortex-M33 +target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine +cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000 + +# define the system CTIs +cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000 +cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000 + +swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000 +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000 + +targets $_CHIPNAME.a35_0 + +target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1 +$_CHIPNAME.a35_0 configure -rtos hwthread +$_CHIPNAME.a35_1 configure -rtos hwthread + +reset_config srst_gates_jtag srst_pulls_trst + +adapter speed 5000 +adapter srst pulse_width 200 +# wait 1 seconds for bootrom +adapter srst delay 1000 + +# set CSW for AXI +$_CHIPNAME.dap apsel 4 +$_CHIPNAME.dap apcsw 0x12800000 + +# mmw with target selection +proc target_mmw {target reg setbits clearbits} { + set val [eval $target read_memory $reg 32 1] + set val [expr {($val & ~$clearbits) | $setbits}] + eval $target mww $reg $val +} + +lappend _telnet_autocomplete_skip _enable_debug +# Uses AP0 and AXI +proc _enable_debug {} { + # set debug enable bits in DBGMCU_CR to get ap8/cm33 visible + $::_CHIPNAME.ap0 mww 0x80010004 0x17 + + # Freeze watchdogs on CPU halt + $::_CHIPNAME.axi mww 0x4a010008 0x00000000 + $::_CHIPNAME.axi mww 0x4a01003c 0x00000026 + $::_CHIPNAME.axi mww 0x4a010040 0x00000038 + $::_CHIPNAME.axi mww 0x4a010044 0x00000400 + $::_CHIPNAME.axi mww 0x4a010048 0x00000400 + $::_CHIPNAME.axi mww 0x4a01004c 0x00000600 +} + +lappend _telnet_autocomplete_skip _rcc_enable_traceclk +# Uses AXI +proc _rcc_enable_traceclk {} { + # set bit TRACEEN in RCC_DBGCFGR to clock TPIU + target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0 +} + +lappend _telnet_autocomplete_skip _handshake_with_wrapper +# Uses AP0 +proc _handshake_with_wrapper { halt } { + set dbgmcu_cr 0 + catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]} + if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} { + echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n" + return; + } + + if { $halt } { + if { $::EN_CA35_0 || $::EN_CA35_1 } { + $::_CHIPNAME.ap0 arp_examine + $::_CHIPNAME.ap0 arp_halt + } + if { $::EN_CA35_0 } { + $::_CHIPNAME.ap0 mww 0x80210300 0 + target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0 + } + if { $::EN_CA35_1 } { + $::_CHIPNAME.ap0 mww 0x80310300 0 + target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0 + } + if { $::EN_CM33 } { + $::_CHIPNAME.ap8 arp_examine + $::_CHIPNAME.ap8 arp_halt + $::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001 + } + } + + # alert wrapper that debugger is ready + $::_CHIPNAME.ap0 mww 0x80010004 0x17 +} + +$_CHIPNAME.m33 configure -event reset-assert { } + +$_CHIPNAME.axi configure -event reset-assert-post { adapter assert srst } + +$_CHIPNAME.axi configure -event reset-deassert-pre { + adapter deassert srst deassert trst + + $::_CHIPNAME.ap0 arp_examine + _handshake_with_wrapper $halt + + $::_CHIPNAME.axi arp_examine + _enable_debug + _rcc_enable_traceclk + if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine; if {$halt} {$::_CHIPNAME.a35_0 arp_halt} } + if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine; if {$halt} {$::_CHIPNAME.a35_1 arp_halt} } + if { $::EN_CM33 } { + $::_CHIPNAME.ap8 arp_examine + $::_CHIPNAME.m33 arp_examine + if {$halt} {$::_CHIPNAME.m33 arp_halt} + } +} + +$_CHIPNAME.axi configure -event examine-end { + _enable_debug + _rcc_enable_traceclk + if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine } + if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine } + if { $::EN_CM33 } { $::_CHIPNAME.ap8 arp_examine; $::_CHIPNAME.m33 arp_examine } +} diff --git a/tcl/target/st/stm32mp25x.cfg b/tcl/target/st/stm32mp25x.cfg new file mode 100644 index 0000000000..97802903fb --- /dev/null +++ b/tcl/target/st/stm32mp25x.cfg @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STMicroelectronics STM32MP25x +# STM32MP25x devices support both JTAG and SWD transports. + +# HLA does not support multi-cores nor custom CSW nor AP other than 0 +if { [using_hla] } { + echo "ERROR: HLA transport cannot work with this target." + shutdown +} + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32mp25x +} + +# Set to 0 to prevent CPU examine. Default examine them +if { ! [info exists EN_CA35_0] } { set EN_CA35_0 1 } +if { ! [info exists EN_CA35_1] } { set EN_CA35_1 1 } +if { ! [info exists EN_CM33] } { set EN_CM33 1 } +if { ! [info exists EN_CM0P] } { set EN_CM0P 1 } + +set _ENDIAN little + +# jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } { + set _CPUTAPID 0x6ba02477 + } +} + +# Chip Level TAP Controller, only in jtag mode +if { [info exists CLCTAPID] } { + set _CLCTAPID $CLCTAPID +} else { + set _CLCTAPID 0x16505041 +} + +swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f +if { [using_jtag] } { + swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5 +} + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap + +# define AXI & APB Memory Access Ports +# NOTE: do not change the order of target create +target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0 +target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4 +target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 -defer-examine +target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine + +# define the first Cortex-A35 +cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000 +target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \ + -cti $_CHIPNAME.cti.a35_0 -defer-examine + +# define the second Cortex-A35 +cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000 +target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \ + -cti $_CHIPNAME.cti.a35_1 -defer-examine + +# define the Cortex-M33 +target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine +cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000 + +# define the Cortex-M0+ +target create $_CHIPNAME.m0p cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine +cti create $_CHIPNAME.cti.m0p -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xf0000000 + +# define the system CTIs +cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000 +cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000 + +swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000 +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000 + +targets $_CHIPNAME.a35_0 + +target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1 +$_CHIPNAME.a35_0 configure -rtos hwthread +$_CHIPNAME.a35_1 configure -rtos hwthread + +reset_config srst_gates_jtag srst_pulls_trst + +adapter speed 5000 +adapter srst pulse_width 200 +# wait 1 seconds for bootrom +adapter srst delay 1000 + +# set CSW for AXI +$_CHIPNAME.dap apsel 4 +$_CHIPNAME.dap apcsw 0x12800000 + +# mmw with target selection +proc target_mmw {target reg setbits clearbits} { + set val [eval $target read_memory $reg 32 1] + set val [expr {($val & ~$clearbits) | $setbits}] + eval $target mww $reg $val +} + +lappend _telnet_autocomplete_skip _enable_ap2_cm0p +proc _enable_ap2_cm0p {} { + # set bits C3LPEN and C3EN in RCC_C3CFGR to enable AP2 and CM0+ clock + target_mmw $::_CHIPNAME.axi 0x54200490 6 0 +} + +lappend _telnet_autocomplete_skip _enable_debug +# Uses AP0 and AXI +proc _enable_debug {} { + # set debug enable bits in DBGMCU_CR to get ap2/cm0+ and ap8/cm33 visible + # set DBG_SWD_SEL_N bit in DBGMCU_CR to get ap2/cm0+ on main debug interface + $::_CHIPNAME.ap0 mww 0x80010004 0x17 + + if { $::EN_CM0P } { + _enable_ap2_cm0p + } + + # Freeze watchdogs on CPU halt + $::_CHIPNAME.axi mww 0x4a010008 0x00000000 + $::_CHIPNAME.axi mww 0x4a01003c 0x00000026 + $::_CHIPNAME.axi mww 0x4a010040 0x00000038 + $::_CHIPNAME.axi mww 0x4a010044 0x00000400 + $::_CHIPNAME.axi mww 0x4a010048 0x00000400 + $::_CHIPNAME.axi mww 0x4a01004c 0x00000600 +} + +lappend _telnet_autocomplete_skip _rcc_enable_traceclk +# Uses AXI +proc _rcc_enable_traceclk {} { + # set bit TRACEEN in RCC_DBGCFGR to clock TPIU + target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0 +} + +lappend _telnet_autocomplete_skip _handshake_with_wrapper +# Uses AP0 +proc _handshake_with_wrapper { halt } { + set dbgmcu_cr 0 + catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]} + if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} { + echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n" + return; + } + + if { $halt } { + if { $::EN_CA35_0 || $::EN_CA35_1 } { + $::_CHIPNAME.ap0 arp_examine + $::_CHIPNAME.ap0 arp_halt + } + if { $::EN_CA35_0 } { + $::_CHIPNAME.ap0 mww 0x80210300 0 + target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0 + } + if { $::EN_CA35_1 } { + $::_CHIPNAME.ap0 mww 0x80310300 0 + target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0 + } + if { $::EN_CM33 } { + $::_CHIPNAME.ap8 arp_examine + $::_CHIPNAME.ap8 arp_halt + $::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001 + } + } + + # alert wrapper that debugger is ready + $::_CHIPNAME.ap0 mww 0x80010004 0x17 +} + +$_CHIPNAME.m33 configure -event reset-assert { } +$_CHIPNAME.m0p configure -event reset-assert { } + +$_CHIPNAME.axi configure -event reset-assert-post { adapter assert srst } + +$_CHIPNAME.axi configure -event reset-deassert-pre { + adapter deassert srst deassert trst + + $::_CHIPNAME.ap0 arp_examine + _handshake_with_wrapper $halt + + $::_CHIPNAME.axi arp_examine + _enable_debug + _rcc_enable_traceclk + if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine; if {$halt} {$::_CHIPNAME.a35_0 arp_halt} } + if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine; if {$halt} {$::_CHIPNAME.a35_1 arp_halt} } + if { $::EN_CM0P } { $::_CHIPNAME.ap2 arp_examine; $::_CHIPNAME.m0p arp_examine } + if { $::EN_CM33 } { + $::_CHIPNAME.ap8 arp_examine + $::_CHIPNAME.m33 arp_examine + if {$halt} {$::_CHIPNAME.m33 arp_halt} + } +} + +$_CHIPNAME.m0p configure -event examine-start { _enable_ap2_cm0p } + +$_CHIPNAME.axi configure -event examine-end { + _enable_debug + _rcc_enable_traceclk + if { $::EN_CA35_0 } { $::_CHIPNAME.a35_0 arp_examine } + if { $::EN_CA35_1 } { $::_CHIPNAME.a35_1 arp_examine } + if { $::EN_CM33 } { $::_CHIPNAME.ap8 arp_examine; $::_CHIPNAME.m33 arp_examine } + if { $::EN_CM0P } { $::_CHIPNAME.ap2 arp_examine; $::_CHIPNAME.m0p arp_examine } +} -- |
