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[PATCH]: 8b01049032 tcl/target/max32xxx: Update max32xxx tcl files to use new flashing algorithm
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From: <ge...@op...> - 2025-06-30 09:55:04
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This is an automated email from Gerrit. "Henrik Mau <hen...@an...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8976 -- gerrit commit 8b01049032df7210122ccb005f560c566463aead Author: Henrik Mau <hen...@an...> Date: Mon Jun 30 10:48:04 2025 +0100 tcl/target/max32xxx: Update max32xxx tcl files to use new flashing algorithm The max32xxx tcl files have been updated to work with the new flashing algorithm. A new max32xxx.cfg file contains common configuration and functionality. Change-Id: Ifaed58836d221ece6192faafa382b30fb72c77a6 Signed-off-by: Henrik Mau <hen...@an...> diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg index f3a9f84c88..b5bccb3084 100644 --- a/tcl/target/max32620.cfg +++ b/tcl/target/max32620.cfg @@ -1,32 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-or-later # Maxim Integrated MAX32620 OpenOCD target configuration file -# www.maximintegrated.com -# adapter speed -adapter speed 4000 - -# reset pin configuration +# Set the reset pin configuration reset_config srst_only +adapter srst delay 200 -if {[using_jtag]} { - jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version - jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version -} else { - swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version -} - -dap create max32620.dap -chain-position max32620.cpu +# Set flash parameters +set FLASH_BASE 0x0 +set FLASH_SIZE 0x200000 +set FLC_BASE 0x40002000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_OPTIONS 0x00 -# target configuration -target create max32620.cpu cortex_m -dap max32620.dap -max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 +# Setup the reserved TAP +set RSV_TAP 1 -# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] -# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> -# max32620 flash base address 0x00000000 -# max32620 flash size 0x200000 (2MB) -# max32620 FLC base address 0x40002000 -# max32620 sector (page) size 0x2000 (8kB) -# max32620 clock speed 96 (MHz) -flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96 +source [find target/max32xxx.cfg] \ No newline at end of file diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg index 90eb392668..8a52b0d6b1 100644 --- a/tcl/target/max32625.cfg +++ b/tcl/target/max32625.cfg @@ -1,32 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-or-later # Maxim Integrated MAX32625 OpenOCD target configuration file -# www.maximintegrated.com -# adapter speed -adapter speed 4000 - -# reset pin configuration +# Set the reset pin configuration reset_config srst_only +adapter srst delay 200 -if {[using_jtag]} { - jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version - jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version -} else { - swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version -} - -dap create max32625.dap -chain-position max32625.cpu +# Set flash parameters +set FLASH_BASE 0x0 +set FLASH_SIZE 0x80000 +set FLC_BASE 0x40002000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_OPTIONS 0x00 -# target configuration -target create max32625.cpu cortex_m -dap max32625.dap -max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 +# Setup the reserved TAP +set RSV_TAP 1 -# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] -# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> -# max32625 flash base address 0x00000000 -# max32625 flash size 0x80000 (512k) -# max32625 FLC base address 0x40002000 -# max32625 sector (page) size 0x2000 (8kB) -# max32625 clock speed 96 (MHz) -flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96 +source [find target/max32xxx.cfg] \ No newline at end of file diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg index 852e04af1e..39b6663403 100644 --- a/tcl/target/max3263x.cfg +++ b/tcl/target/max3263x.cfg @@ -1,32 +1,40 @@ # SPDX-License-Identifier: GPL-2.0-or-later # Maxim Integrated MAX3263X OpenOCD target configuration file -# www.maximintegrated.com -# adapter speed -adapter speed 4000 +# Set the reset pin configuration +reset_config none -# reset pin configuration -reset_config srst_only +# Set flash parameters +set FLASH_BASE 0x0 +set FLASH_SIZE 0x200000 +set FLC_BASE 0x40002000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_OPTIONS 0x00 -if {[using_jtag]} { - jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version - jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version -} else { - swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version -} +# Setup the reserved TAP +set RSV_TAP 1 + +source [find target/max32xxx.cfg] + +# Create custom reset sequence +$_CHIPNAME.cpu configure -event reset-init { -dap create max3263x.dap -chain-position max3263x.cpu + # Reset the peripherals + mww 0x40000848 0xFFFFFFFF + mww 0x4000084C 0xFFFFFFFF -# target configuration -target create max3263x.cpu cortex_m -dap max3263x.dap -max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 + sleep 10 -# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] -# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> -# max3263x flash base address 0x00000000 -# max3263x flash size 0x200000 (2MB) -# max3263x FLC base address 0x40002000 -# max3263x sector (page) size 0x2000 (8kB) -# max3263x clock speed 96 (MHz) -flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96 + mww 0x40000848 0x0 + mww 0x4000084C 0x0 + + # Reset the SP + set SP_ADDR [mrw 0x0] + reg sp $SP_ADDR + + # Reset the PC to the Reset_Handler + set RESET_HANDLER_ADDR [mrw 0x4] + reg pc $RESET_HANDLER_ADDR +} diff --git a/tcl/target/max32xxx.cfg b/tcl/target/max32xxx.cfg new file mode 100644 index 0000000000..66c7135731 --- /dev/null +++ b/tcl/target/max32xxx.cfg @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Maxim Integrated max32xxx OpenOCD drver configuration file + +source [find mem_helper.tcl] +source [find target/swj-dp.tcl] + +# Set the adapter speed +if { [info exists ADAPTER_KHZ] } { + set _ADAPTER_KHZ $ADAPTER_KHZ +} else { + set _ADAPTER_KHZ 2000 +} +adapter speed $_ADAPTER_KHZ + +# Target configuration +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME max32xxx +} + +# Add reserved TAP +if { [using_jtag] && [info exists RSV_TAP] } { + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version + jtag newtap rsvtap tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version +} else { + swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version +} + + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap + +# Enable thread-aware debugging +$_CHIPNAME.cpu configure -rtos auto + +# Setup working area +if { [info exists WORK_START] } { + set _WORK_START $WORK_START +} else { + set _WORK_START 0x20005000 +} + +if { [info exists WORK_SIZE] } { + set _WORK_SIZE $WORK_SIZE +} else { + set _WORK_SIZE 0x8000 +} + +$_CHIPNAME.cpu configure -work-area-phys $_WORK_START -work-area-size $_WORK_SIZE + +# Configure flash driver +if { [info exists FLASH_BASE] } { + set _FLASH_BASE $FLASH_BASE +} else { + set _FLASH_BASE 0x10000000 +} + +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + set _FLASH_SIZE 0x10000 +} + +if { [info exists FLC_BASE] } { + set _FLC_BASE $FLC_BASE +} else { + set _FLC_BASE 0x40029000 +} + +if { [info exists FLASH_SECTOR] } { + set _FLASH_SECTOR $FLASH_SECTOR +} else { + set _FLASH_SECTOR 0x2000 +} + +if { [info exists FLASH_CLK] } { + set _FLASH_CLK $FLASH_CLK +} else { + set _FLASH_CLK 96 +} + +# OPTIONS_128 0x01 /* Perform 128 bit flash writes */ +# OPTIONS_ENC 0x02 /* Encrypt the flash contents */ +# OPTIONS_AUTH 0x04 /* Authenticate the flash contents */ +# OPTIONS_COUNT 0x08 /* Add counter values to authentication */ +# OPTIONS_INTER 0x10 /* Interleave the authentication and count values*/ +# OPTIONS_RELATIVE_XOR 0x20 /* Only XOR the offset of the address when encrypting */ +# OPTIONS_KEYSIZE 0x40 /* Use a 256 bit KEY */ + +if { [info exists FLASH_OPTIONS] } { + set _FLASH_OPTIONS $FLASH_OPTIONS +} else { + set _FLASH_OPTIONS 0 +} + +flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \ +$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_OPTIONS + +# call allow_low_pwr_dbg to set this to 1 +set ALLOW_LOW_PWR_DBG 0 + +proc allow_low_pwr_dbg {} { + global ALLOW_LOW_PWR_DBG + + # set our low-power debug flag + set ALLOW_LOW_PWR_DBG 1 +} + +# enable debug in case of low-power mode +proc enable_debug {} { + set DBGKEY 0xA05F0000 + set C_DEBUGEN 0x00000001 + set C_HALT 0x00000002 + + echo "Enable debug to connect in low-power mode" + + # enable debug + mww 0xE000EDF0 [expr {$DBGKEY | $C_HALT | $C_DEBUGEN}] + + # allow for time waking up + sleep 500 +} + +$_CHIPNAME.cpu configure -event reset-deassert-post { + global ALLOW_LOW_PWR_DBG + + if { $ALLOW_LOW_PWR_DBG == 1 } { + enable_debug + } +} + +# first thing called once target examined flag is set +# $_CHIPNAME.cpu configure -event examine-first { +# global ALLOW_LOW_PWR_DBG + +# if { $ALLOW_LOW_PWR_DBG == 1 } { +# enable_debug +# } +# } -- |
