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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1070-g8194fc48b
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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:36:24
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- Log -----------------------------------------------------------------
commit 8194fc48bd3f06071a9068e385a122499447340a
Author: Marc Schink <de...@za...>
Date: Fri Jun 20 11:18:03 2025 +0200
tcl/board: Add config for TMS570LS12x development kit
Tested on the corresponding hardware.
Change-Id: Ic98141c450bb981cc7853c93b38195c7930bc7d3
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8969
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/ti/launchxl2-tms57012.cfg b/tcl/board/ti/launchxl2-tms57012.cfg
new file mode 100644
index 000000000..99cb26e20
--- /dev/null
+++ b/tcl/board/ti/launchxl2-tms57012.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hercules TMS570LS12x LaunchPad Development Kit
+# https://www.ti.com/tool/LAUNCHXL2-TMS57012
+
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+source [find target/ti_tms570ls1x.cfg]
commit c6f18633522e8cbc80e2abb5cf5e87da13440b92
Author: Marc Schink <de...@za...>
Date: Fri Jun 20 10:47:23 2025 +0200
target/armv4: Use command_print() instead of LOG_ERROR()
Use command_print() in order to provide an error message to the caller.
Change-Id: I9f1a2ef07a102e1d6e755f3680bed0f7183b5c9c
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8968
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 22cdba8ce..d90761569 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -842,7 +842,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
}
if (!is_arm_mode(arm->core_mode)) {
- LOG_ERROR("not a valid arm core mode - communication failure?");
+ command_print(CMD, "not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}
@@ -954,7 +954,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
struct target *target = get_current_target(CMD_CTX);
if (!target) {
- LOG_ERROR("No target selected");
+ command_print(CMD, "No target selected");
return ERROR_FAIL;
}
commit 56c24b9eb22c690f62fc173fe2fbd649070ae3d6
Author: Marc Schink <de...@za...>
Date: Fri Jun 20 10:44:21 2025 +0200
target/armv4: Use LOG_TARGET_xxx()
Use LOG_TARGET_xxx() for log messages as it is used for other targets.
While at it, rework the log messages. For example by removing spaces or
punctuation marks at the end of the message.
Change-Id: I295001876d40527ec8f35c2aec8d562a29e57b26
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8967
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 597dc8990..22cdba8ce 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -437,7 +437,7 @@ const int armv4_5_core_reg_map[9][17] = {
static const char *arm_core_state_string(struct arm *arm)
{
if (arm->core_state > ARRAY_SIZE(arm_state_strings)) {
- LOG_ERROR("core_state exceeds table size");
+ LOG_TARGET_ERROR(arm->target, "core_state exceeds table size");
return "Unknown";
}
@@ -483,20 +483,20 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
if (cpsr & (1 << 5)) { /* T */
if (cpsr & (1 << 24)) { /* J */
- LOG_WARNING("ThumbEE -- incomplete support");
+ LOG_TARGET_WARNING(arm->target, "ThumbEE -- incomplete support");
state = ARM_STATE_THUMB_EE;
} else
state = ARM_STATE_THUMB;
} else {
if (cpsr & (1 << 24)) { /* J */
- LOG_ERROR("Jazelle state handling is BROKEN!");
+ LOG_TARGET_ERROR(arm->target, "Jazelle state handling is broken");
state = ARM_STATE_JAZELLE;
} else
state = ARM_STATE_ARM;
}
arm->core_state = state;
- LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
+ LOG_TARGET_DEBUG(arm->target, "set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
arm_mode_name(mode),
arm_core_state_string(arm));
}
@@ -521,7 +521,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
return NULL;
if (!arm->map) {
- LOG_ERROR("Register map is not available yet, the target is not fully initialised");
+ LOG_TARGET_ERROR(arm->target, "Register map is not available yet, the target is not fully initialised");
r = arm->core_cache->reg_list + regnum;
} else
r = arm->core_cache->reg_list + arm->map[regnum];
@@ -530,7 +530,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
* that doesn't support it...
*/
if (!r) {
- LOG_ERROR("Invalid CPSR mode");
+ LOG_TARGET_ERROR(arm->target, "Invalid CPSR mode");
r = arm->core_cache->reg_list + regnum;
}
@@ -631,7 +631,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
*/
if (armv4_5_target->core_mode !=
(enum arm_mode)(value & 0x1f)) {
- LOG_DEBUG("changing ARM core mode to '%s'",
+ LOG_TARGET_DEBUG(target, "changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
value &= ~((1 << 24) | (1 << 5));
uint8_t t[4];
@@ -798,7 +798,7 @@ int arm_arch_state(struct target *target)
struct arm *arm = target_to_arm(target);
if (arm->common_magic != ARM_COMMON_MAGIC) {
- LOG_ERROR("BUG: called for a non-ARM target");
+ LOG_TARGET_ERROR(target, "BUG: called for a non-ARM target");
return ERROR_FAIL;
}
@@ -806,7 +806,7 @@ int arm_arch_state(struct target *target)
if (target->semihosting && target->semihosting->hit_fileio)
return ERROR_OK;
- LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+ LOG_TARGET_USER(target, "target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
arm_core_state_string(arm),
debug_reason_name(target),
@@ -1291,7 +1291,7 @@ int arm_get_gdb_reg_list(struct target *target,
unsigned int i;
if (!is_arm_mode(arm->core_mode)) {
- LOG_ERROR("not a valid arm core mode - communication failure?");
+ LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}
@@ -1362,7 +1362,7 @@ int arm_get_gdb_reg_list(struct target *target,
return ERROR_OK;
default:
- LOG_ERROR("not a valid register class type in query.");
+ LOG_TARGET_ERROR(target, "not a valid register class type in query");
return ERROR_FAIL;
}
}
@@ -1391,8 +1391,7 @@ static int armv4_5_run_algorithm_completion(struct target *target,
/* fast exit: ARMv5+ code can use BKPT */
if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
- LOG_WARNING(
- "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
+ LOG_TARGET_ERROR(target, "reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
return ERROR_TARGET_TIMEOUT;
}
@@ -1417,10 +1416,10 @@ int armv4_5_run_algorithm_inner(struct target *target,
int i;
int retval = ERROR_OK;
- LOG_DEBUG("Running algorithm");
+ LOG_TARGET_DEBUG(target, "Running algorithm");
if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
- LOG_ERROR("current target isn't an ARMV4/5 target");
+ LOG_TARGET_ERROR(target, "current target isn't an ARMV4/5 target");
return ERROR_TARGET_INVALID;
}
@@ -1430,13 +1429,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
}
if (!is_arm_mode(arm->core_mode)) {
- LOG_ERROR("not a valid arm core mode - communication failure?");
+ LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}
/* armv5 and later can terminate with BKPT instruction; less overhead */
if (!exit_point && arm->arch == ARM_ARCH_V4) {
- LOG_ERROR("ARMv4 target needs HW breakpoint location");
+ LOG_TARGET_ERROR(target, "ARMv4 target needs HW breakpoint location");
return ERROR_FAIL;
}
@@ -1470,12 +1469,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
if (!reg) {
- LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+ LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (reg->size != reg_params[i].size) {
- LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+ LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size",
reg_params[i].reg_name);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1491,12 +1490,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
else if (arm->core_state == ARM_STATE_THUMB)
exit_breakpoint_size = 2;
else {
- LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
+ LOG_TARGET_ERROR(target, "BUG: can't execute algorithms when not in ARM or Thumb state");
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
- LOG_DEBUG("setting core_mode: 0x%2.2x",
+ LOG_TARGET_DEBUG(target, "setting core_mode: 0x%2.2x",
arm_algorithm_info->core_mode);
buf_set_u32(arm->cpsr->value, 0, 5,
arm_algorithm_info->core_mode);
@@ -1509,7 +1508,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
retval = breakpoint_add(target, exit_point,
exit_breakpoint_size, BKPT_HARD);
if (retval != ERROR_OK) {
- LOG_ERROR("can't add HW breakpoint to terminate algorithm");
+ LOG_TARGET_ERROR(target, "can't add HW breakpoint to terminate algorithm");
return ERROR_TARGET_FAILURE;
}
}
@@ -1542,13 +1541,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
reg_params[i].reg_name,
false);
if (!reg) {
- LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+ LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
retval = ERROR_COMMAND_SYNTAX_ERROR;
continue;
}
if (reg->size != reg_params[i].size) {
- LOG_ERROR(
+ LOG_TARGET_ERROR(target,
"BUG: register '%s' size doesn't match reg_params[i].size",
reg_params[i].reg_name);
retval = ERROR_COMMAND_SYNTAX_ERROR;
@@ -1667,7 +1666,7 @@ int arm_checksum_memory(struct target *target,
if (retval == ERROR_OK)
*checksum = buf_get_u32(reg_params[0].value, 0, 32);
else
- LOG_ERROR("error executing ARM crc algorithm");
+ LOG_TARGET_ERROR(target, "error executing ARM CRC algorithm");
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
@@ -1702,7 +1701,7 @@ int arm_blank_check_memory(struct target *target,
assert(sizeof(check_code_le) % 4 == 0);
if (erased_value != 0xff) {
- LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
+ LOG_TARGET_ERROR(target, "Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
erased_value);
return ERROR_FAIL;
}
@@ -1781,7 +1780,7 @@ static int arm_default_mrc(struct target *target, int cpnum,
uint32_t crn, uint32_t crm,
uint32_t *value)
{
- LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
+ LOG_TARGET_ERROR(target, "%s doesn't implement MRC", target_type_name(target));
return ERROR_FAIL;
}
@@ -1789,7 +1788,7 @@ static int arm_default_mrrc(struct target *target, int cpnum,
uint32_t op, uint32_t crm,
uint64_t *value)
{
- LOG_ERROR("%s doesn't implement MRRC", target_type_name(target));
+ LOG_TARGET_ERROR(target, "%s doesn't implement MRRC", target_type_name(target));
return ERROR_FAIL;
}
@@ -1798,7 +1797,7 @@ static int arm_default_mcr(struct target *target, int cpnum,
uint32_t crn, uint32_t crm,
uint32_t value)
{
- LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
+ LOG_TARGET_ERROR(target, "%s doesn't implement MCR", target_type_name(target));
return ERROR_FAIL;
}
@@ -1806,7 +1805,7 @@ static int arm_default_mcrr(struct target *target, int cpnum,
uint32_t op, uint32_t crm,
uint64_t value)
{
- LOG_ERROR("%s doesn't implement MCRR", target_type_name(target));
+ LOG_TARGET_ERROR(target, "%s doesn't implement MCRR", target_type_name(target));
return ERROR_FAIL;
}
commit 7fa8a5c257dcf3dbf072103f69959448e57dfa2c
Author: Marc Schink <de...@za...>
Date: Fri Jun 20 10:30:03 2025 +0200
target/armv7a: Use LOG_TARGET_xxx()
Use LOG_TARGET_xxx() to indicate which target the message belongs to.
Change-Id: Ic40c61a779c1a1ebdc96ebc56b27541fff5e6205
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8966
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 651241b77..2bbafd420 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -68,9 +68,9 @@ static void armv7a_show_fault_registers(struct target *target)
if (retval != ERROR_OK)
goto done;
- LOG_USER("Data fault registers DFSR: %8.8" PRIx32
+ LOG_TARGET_USER(target, "Data fault registers DFSR: %8.8" PRIx32
", DFAR: %8.8" PRIx32, dfsr, dfar);
- LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+ LOG_TARGET_USER(target, "Instruction fault registers IFSR: %8.8" PRIx32
", IFAR: %8.8" PRIx32, ifsr, ifar);
done:
@@ -134,7 +134,7 @@ int armv7a_read_ttbcr(struct target *target)
if (retval != ERROR_OK)
goto done;
- LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+ LOG_TARGET_DEBUG(target, "ttbcr %" PRIx32, ttbcr);
ttbcr_n = ttbcr & 0x7;
armv7a->armv7a_mmu.ttbcr = ttbcr;
@@ -169,7 +169,7 @@ int armv7a_read_ttbcr(struct target *target)
armv7a->armv7a_mmu.ttbr_mask[0] = 7 << (32 - ttbcr_n);
}
- LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+ LOG_TARGET_DEBUG(target, "ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
(ttbcr_n != 0) ? "used" : "not used",
armv7a->armv7a_mmu.ttbr_mask[0],
armv7a->armv7a_mmu.ttbr_mask[1]);
@@ -248,14 +248,13 @@ static int armv7a_read_mpidr(struct target *target)
/* Is register in Multiprocessing Extensions register format? */
if (mpidr & MPIDR_MP_EXT) {
- LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
+ LOG_TARGET_DEBUG(target, "%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
armv7a->multi_processor_system = (mpidr >> 30) & 1;
armv7a->multi_threading_processor = (mpidr >> 24) & 1;
armv7a->level2_id = (mpidr >> 16) & 0xf;
armv7a->cluster_id = (mpidr >> 8) & 0xf;
armv7a->cpu_id = mpidr & 0xf;
- LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
- target_name(target),
+ LOG_TARGET_INFO(target, "MPIDR level2 %x, cluster %x, core %x, %s, %s",
armv7a->level2_id,
armv7a->cluster_id,
armv7a->cpu_id,
@@ -263,7 +262,7 @@ static int armv7a_read_mpidr(struct target *target)
armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
} else
- LOG_DEBUG("MPIDR not in multiprocessor format");
+ LOG_TARGET_DEBUG(target, "MPIDR not in multiprocessor format");
done:
dpm->finish(dpm);
@@ -338,7 +337,7 @@ int armv7a_identify_cache(struct target *target)
cache->iminline = 4UL << (ctr & 0xf);
cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
- LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
+ LOG_TARGET_DEBUG(target, "ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
ctr, cache->iminline, cache->dminline);
/* retrieve CLIDR
@@ -350,7 +349,7 @@ int armv7a_identify_cache(struct target *target)
goto done;
cache->loc = (clidr & 0x7000000) >> 24;
- LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
+ LOG_TARGET_DEBUG(target, "Number of cache levels to PoC %" PRId32, cache->loc);
/* retrieve selected cache for later restore
* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
@@ -378,13 +377,13 @@ int armv7a_identify_cache(struct target *target)
goto done;
cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
- LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+ LOG_TARGET_DEBUG(target, "data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
cache->arch[cl].d_u_size.index,
cache->arch[cl].d_u_size.index_shift,
cache->arch[cl].d_u_size.way,
cache->arch[cl].d_u_size.way_shift);
- LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+ LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
cache->arch[cl].d_u_size.linelen,
cache->arch[cl].d_u_size.cachesize,
cache->arch[cl].d_u_size.associativity);
@@ -398,13 +397,13 @@ int armv7a_identify_cache(struct target *target)
goto done;
cache->arch[cl].i_size = decode_cache_reg(cache_reg);
- LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+ LOG_TARGET_DEBUG(target, "instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
cache->arch[cl].i_size.index,
cache->arch[cl].i_size.index_shift,
cache->arch[cl].i_size.way,
cache->arch[cl].i_size.way_shift);
- LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+ LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
cache->arch[cl].i_size.linelen,
cache->arch[cl].i_size.cachesize,
cache->arch[cl].i_size.associativity);
@@ -445,7 +444,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
armv7a->debug_base + CPUDBG_VCR,
&vcr);
if (ret < 0) {
- LOG_ERROR("Failed to read VCR register\n");
+ LOG_TARGET_ERROR(target, "Failed to read VCR register");
return ret;
}
@@ -458,7 +457,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
armv7a->debug_base + CPUDBG_VCR,
vcr);
if (ret < 0)
- LOG_ERROR("Failed to write VCR register\n");
+ LOG_TARGET_ERROR(target, "Failed to write VCR register");
return ret;
}
@@ -489,18 +488,18 @@ int armv7a_arch_state(struct target *target)
struct arm *arm = &armv7a->arm;
if (armv7a->common_magic != ARMV7_COMMON_MAGIC) {
- LOG_ERROR("BUG: called for a non-ARMv7A target");
+ LOG_TARGET_ERROR(target, "BUG: called for a non-ARMv7A target");
return ERROR_COMMAND_SYNTAX_ERROR;
}
arm_arch_state(target);
if (armv7a->is_armv7r) {
- LOG_USER("D-Cache: %s, I-Cache: %s",
+ LOG_TARGET_USER(target, "D-Cache: %s, I-Cache: %s",
state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
} else {
- LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+ LOG_TARGET_USER(target, "MMU: %s, D-Cache: %s, I-Cache: %s",
state[armv7a->armv7a_mmu.mmu_enabled],
state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
-----------------------------------------------------------------------
Summary of changes:
src/target/armv4_5.c | 63 ++++++++++++++++++-------------------
src/target/armv7a.c | 37 +++++++++++-----------
tcl/board/ti/launchxl2-tms57012.cfg | 10 ++++++
3 files changed, 59 insertions(+), 51 deletions(-)
create mode 100644 tcl/board/ti/launchxl2-tms57012.cfg
hooks/post-receive
--
Main OpenOCD repository
|
