From: openocd-gerrit <ope...@us...> - 2025-03-15 10:15:45
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This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 9e5ffed7d6f045f86a35beab461018bab2c1da0c (commit) via a2c3c791ad86b12f7a689697166c46cb60db3c8b (commit) via a8555b0b6d3e3c3150786550686292b1e69ec985 (commit) from 5300242a3edad9924ed75119320e0fccc5afd614 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 9e5ffed7d6f045f86a35beab461018bab2c1da0c Author: Shivasharan Nagalikar <shi...@ti...> Date: Wed Feb 19 13:57:35 2025 +0530 tcl/target/ti_k3: Add support for AM263P AM263P[1] adds additional features to AM263 SoC. [2] provides a detailed list of differences, however, the key difference from processor usage perspective is the increased SRAM and Remote L2(RL2) Cache for improved performance of R5F. To differentiate the DIE ID is different, however rest of the processor description remain compatible to AM263, hence reuse the definition. [1] https://www.ti.com/product/AM263P4 [2] https://www.ti.com/lit/pdf/spradb3 Change-Id: If47935caf1f995d7e606547e0d6545c39544678a Signed-off-by: Shivasharan Nagalikar <shi...@ti...> Reviewed-on: https://review.openocd.org/c/openocd/+/8770 Reviewed-by: Nishanth Menon <nm...@ti...> Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index dbf8962cb..2feffb92e 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -6,6 +6,8 @@ # Has 4 R5 Cores, M4F and an M3 # * AM263: https://www.ti.com/lit/pdf/spruj17 # Has 4 R5 Cores and an M3 +# * AM263P: https://www.ti.com/lit/pdf/spruj55 +# Has 4 R5 Cores and an M4F # * AM273: https://www.ti.com/lit/pdf/spruiu0 # Has 2 R5 Cores and an M3 # * AM625: https://www.ti.com/lit/pdf/spruiv7a @@ -87,6 +89,7 @@ set _powerap_sprec_reset 0xf0 # Set configuration overrides for each SOC switch $_soc { + am263p - am263 { set _K3_DAP_TAPID 0x2bb7d02f @@ -104,6 +107,10 @@ switch $_soc { set _r5_ap_num 5 set _power_ap_num 7 + + if { "$_soc" == "am263p" } { + set _K3_DAP_TAPID 0x1bb9502f + } } am273 { set _K3_DAP_TAPID 0x1bb6a02f commit a2c3c791ad86b12f7a689697166c46cb60db3c8b Author: Shivasharan Nagalikar <shi...@ti...> Date: Wed Feb 19 13:53:03 2025 +0530 tcl/target/ti_k3: Add support for system reset using powerAP TI K3 Debug systems have a Power Access Port (Power-AP) which allows for functionality such as reset via debugger that using the SPREC register. SoCs/Boards that do not have support for SRST or TRST can make use of this to force a system reset via debug access. Change-Id: Ic5f9cc7f7fba77b353b0c0b42d8afc02502251a0 Signed-off-by: Shivasharan Nagalikar <shi...@ti...> Reviewed-on: https://review.openocd.org/c/openocd/+/8769 Reviewed-by: Nishanth Menon <nm...@ti...> Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index b033ca978..dbf8962cb 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -79,6 +79,12 @@ set _gp_mcu_ap_unlock_offsets {0xf0 0x60} # Generic mem-ap port number set _mem_ap_num 2 +# Generic AP_SEL PWR Register number +set _power_ap_num 3 + +# Generic SPREC RESET BANK and Field number +set _powerap_sprec_reset 0xf0 + # Set configuration overrides for each SOC switch $_soc { am263 { @@ -96,6 +102,8 @@ switch $_soc { set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000} set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000} set _r5_ap_num 5 + + set _power_ap_num 7 } am273 { set _K3_DAP_TAPID 0x1bb6a02f @@ -513,3 +521,10 @@ if { 0 == [string compare [adapter name] dmem ] } { # AXI AP access port for SoC address map target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num } + +# Reset system using (Debug Reset) SPREC Register,SYSTEMRESET bit field via apreg +proc dbg_sys_reset {} { + $::_CHIPNAME.dap apreg $::_power_ap_num $::_powerap_sprec_reset 0x1 +} + +add_help_text dbg_sys_reset "Debugger initiated system reset attempt via Power-AP" commit a8555b0b6d3e3c3150786550686292b1e69ec985 Author: Nishanth Menon <nm...@ti...> Date: Mon Mar 3 06:57:23 2025 -0600 tcl/board: Add TI am62levm config Add basic connection details with AM62l SK/EVM For further details, see: https://www.ti.com/tool/TMDS62LEVM Change-Id: Ic957a904dfe01951396f9767479884f2a121b181 Co-developed-by: Bryan Brattlof <bb...@ti...> Signed-off-by: Bryan Brattlof <bb...@ti...> Signed-off-by: Nishanth Menon <nm...@ti...> Reviewed-on: https://review.openocd.org/c/openocd/+/8799 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/tcl/board/ti_am62levm.cfg b/tcl/board/ti_am62levm.cfg new file mode 100644 index 000000000..6debdd49f --- /dev/null +++ b/tcl/board/ti_am62levm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments AM62L EVM: +# Links: https://www.ti.com/tool/TMDS62LEVM +# + +# the AM62L3 EVM/SK has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am62l +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 ----------------------------------------------------------------------- Summary of changes: tcl/board/{ti_j722sevm.cfg => ti_am62levm.cfg} | 9 +++++---- tcl/target/ti_k3.cfg | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+), 4 deletions(-) copy tcl/board/{ti_j722sevm.cfg => ti_am62levm.cfg} (63%) hooks/post-receive -- Main OpenOCD repository |