From: openocd-gerrit <ope...@us...> - 2025-01-06 05:01:53
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 250ab1008b4d5f9520066df28170c42fc8b40af4 (commit) from 5233312ea5725dfcb8b8e0baee103017531ba54f (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 250ab1008b4d5f9520066df28170c42fc8b40af4 Author: David (Pololu) <dev...@po...> Date: Wed Dec 18 13:49:00 2024 -0800 flash/stm32l4x: add STM32C071xx support I successfully programmed a NUCLEO-C071RB with these changes. Change-Id: Ib57a77fa18f8a0e8c882e2250d6111c588d76887 Signed-off-by: David (Pololu) <dev...@po...> Reviewed-on: https://review.openocd.org/c/openocd/+/8525 Tested-by: jenkins Reviewed-by: Tomas Vanek <va...@fb...> diff --git a/doc/openocd.texi b/doc/openocd.texi index 594f7a7f0..7c5f84c55 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -8001,7 +8001,7 @@ The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @deffn {Flash Driver} {stm32l4x} -All members of the STM32 G0, G4, L4, L4+, L5, U0, U5, WB and WL +All members of the STM32 C0, G0, G4, L4, L4+, L5, U0, U5, WB and WL microcontroller families from STMicroelectronics include internal flash and use ARM Cortex-M0+, M4 and M33 cores. The driver automatically recognizes a number of these chips using diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index d2e8f3050..3062fca72 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -303,6 +303,10 @@ static const struct stm32l4_rev stm32c03xx_revs[] = { { 0x1000, "A" }, { 0x1001, "Z" }, }; +static const struct stm32l4_rev stm32c071xx_revs[] = { + { 0x1001, "Z" }, +}; + static const struct stm32l4_rev stm32g05_g06xx_revs[] = { { 0x1000, "A" }, }; @@ -442,6 +446,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_base = 0x1FFF7000, .otp_size = 1024, }, + { + .id = DEVID_STM32C071XX, + .revs = stm32c071xx_revs, + .num_revs = ARRAY_SIZE(stm32c071xx_revs), + .device_str = "STM32C071xx", + .max_flash_size_kb = 128, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF75A0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, + }, { .id = DEVID_STM32U53_U54XX, .revs = stm32u53_u54xx_revs, @@ -1989,6 +2005,7 @@ static int stm32l4_probe(struct flash_bank *bank) case DEVID_STM32L43_L44XX: case DEVID_STM32C01XX: case DEVID_STM32C03XX: + case DEVID_STM32C071XX: case DEVID_STM32G05_G06XX: case DEVID_STM32G07_G08XX: case DEVID_STM32U031XX: diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h index b1e8f9870..f152c9f30 100644 --- a/src/flash/nor/stm32l4x.h +++ b/src/flash/nor/stm32l4x.h @@ -108,6 +108,7 @@ #define DEVID_STM32U57_U58XX 0x482 #define DEVID_STM32U073_U083XX 0x489 #define DEVID_STM32WBA5X 0x492 +#define DEVID_STM32C071XX 0x493 #define DEVID_STM32WB1XX 0x494 #define DEVID_STM32WB5XX 0x495 #define DEVID_STM32WB3XX 0x496 diff --git a/tcl/board/st_nucleo_c0.cfg b/tcl/board/st_nucleo_c0.cfg new file mode 100644 index 000000000..7d0767592 --- /dev/null +++ b/tcl/board/st_nucleo_c0.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find interface/stlink.cfg] + +transport select dapdirect_swd + +source [find target/stm32c0x.cfg] + +reset_config srst_only ----------------------------------------------------------------------- Summary of changes: doc/openocd.texi | 2 +- src/flash/nor/stm32l4x.c | 17 +++++++++++++++++ src/flash/nor/stm32l4x.h | 1 + tcl/board/{st_nucleo_wb55.cfg => st_nucleo_c0.cfg} | 6 +----- 4 files changed, 20 insertions(+), 6 deletions(-) copy tcl/board/{st_nucleo_wb55.cfg => st_nucleo_c0.cfg} (58%) hooks/post-receive -- Main OpenOCD repository |